A method and device for controlling onboard high-speed switching and storage integrated cache

Abstract

The present invention discloses a method for controlling an integrated cache of onboard high-speed switching and storage, comprising: dividing the cache into a plurality of blocks by a preset minimum unit or an integer multiple of the minimum unit, wherein each block is composed of a meta area and a data area; receiving a data packet from an input port, and storing the received data in a corresponding cache; and in the case where a cache address larger than the minimum unit is empty after each block receives corresponding data, dividing the empty cache address into independent blocks by a preset minimum unit or an integer multiple of the minimum unit. The present invention can effectively improve the utilization rate and access speed of the cache space. If a data block is only partially occupied, it can be split into smaller blocks by a unit of 64 bytes, and a head and tail pointer is defined for each new data block to improve the storage efficiency. If the occupancy rate of the data block is low, the smaller data blocks can be merged with the corresponding head and tail pointers, thereby improving the real-time performance of network device scheduling.

Description

Technical Field

[0001] The present invention belongs to the field of aerospace communication technology, and in particular relates to a method, device, equipment and storage medium for controlling a spaceborne high-speed switching and storage integrated cache. Background Art

[0002] With the rapid development of my country's aerospace industry, the demand for data interaction between satellite-borne single machines has been continuously increasing, which has put forward higher requirements for the information exchange capabilities on the satellite. The multi-connection data interaction mode has become a development trend. In this context, building a distributed Ethernet network based on multiple platforms on the satellite is an effective way to solve these problems. However, traditional Ethernet networks have data transmission conflicts, which has a serious impact on the reliability and real-time performance of on-board data transmission.

[0003] Time-triggered Ethernet is a new type of real-time industrial control Ethernet with high real-time performance, high resource utilization and high fault tolerance, which has been widely used in the industrial field. As a distributed network, time-triggered Ethernet has a communication rate of more than 1Gbps, and adds time attributes and multiple fault-tolerant designs in the network to ensure the reliable transmission of time-critical messages. It has many superior characteristics such as high determinism and high real-time performance. It is gradually applied to the field of aerospace communication technology.

[0004] However, the satellite-borne time-triggered network introduces two types of triggering services: time triggering and event triggering. For time-triggered services, the triggering of all network services is based on a pre-planned global timing. When the global clock reaches a specific time point, the transmission of service data is triggered. In the corresponding event-triggered transmission time slot, since the transmission time of the event-triggered services of each end system is uncertain, conflicts may occur during the transmission process. The switch will open up a certain depth of data frame cache space on each switching end node to temporarily cache the conflicting data, and maintain a data frame queue for each output port, outputting the data in sequence with a first-in-first-out scheduling strategy to prevent transmission packet loss caused by conflicts in sending data. In the satellite-borne context, since there are many types of data, there are often a lot of conflicting data, which also causes the problem of low efficiency in the use of cache space, which needs to be solved urgently. Summary of the invention

[0005] The purpose of the present invention is to provide a method, device, equipment and storage medium for onboard high-speed switching and storage integrated cache control. The method, device, equipment and storage medium provide a flexible and fast cache control method to solve the defect of low cache space utilization efficiency in the prior art.

[0006] To solve the above problems, the technical solution of the present invention is: a method for controlling an onboard high-speed switching and storage integrated cache, comprising: dividing the cache into multiple blocks according to a preset minimum unit or an integer multiple of the minimum unit, wherein each block consists of a meta area and a data area, the meta area records the information of the data block, and the data area is a truly allocated memory area; receiving a data packet from an input port, and storing the received data in a corresponding cache; after each block receives the corresponding data and still has an empty cache address that is larger than the minimum unit, dividing the empty cache address into independent blocks according to a preset minimum unit or an integer multiple of the minimum unit.

[0007] In one embodiment of the present invention, the size of the data area of ​​the block is 64 bytes or an integral multiple of 64 bytes.

[0008] In one embodiment of the present invention, the information of the data block recorded in the meta area includes the data area size, a free flag, and a pointer.

[0009] In one embodiment of the present invention, the first byte address of the data area is the returned address.

[0010] In one embodiment of the present invention, when a data packet is received through an input port, an empty data area is searched from the beginning in the block, the corresponding data packet is stored and the starting address is returned.

[0011] In one embodiment of the present invention, when the size of the received data packet is larger than the first data area found, the data areas of the remaining one or more blocks are merged to cache the data packet.

[0012] In one embodiment of the present invention, when the received data packet is a multicast packet, the high-order address is used for matching and the low-order address is used as the index of the cache block; when the received data packet is a broadcast packet or a unicast packet, the given index is used and a block in the multicast cache is used.

[0013] Based on the same concept, the present invention also provides a satellite-borne high-speed switching and storage integrated cache control device, including: a partition unit, used to divide the cache into multiple blocks according to a preset minimum unit or an integer multiple of the minimum unit, wherein each block is composed of a meta area and a data area, the meta area records the information of the data block, and the data area is a truly allocated memory area; a cache unit, used to receive data packets from an input port and store the received data into a corresponding cache; a reorganization unit, used to divide the empty cache address into independent blocks according to a preset minimum unit or an integer multiple of the minimum unit after each block has received the corresponding data and still has an empty cache address larger than the minimum unit; or, when the size of the received data packet is larger than the first data area found, merge the data areas of the remaining one or more blocks to cache the data packet.

[0014] Based on the same concept, the present invention also provides an electronic device, comprising: a memory, the memory is used to store a processing program; a processor, the processor implements the on-board high-speed switching storage integrated cache control method when executing the processing program.

[0015] Based on the same concept, the present invention also provides a readable storage medium, on which a processing program is stored. When the processing program is executed by a processor, the on-board high-speed switching storage integrated cache control method is implemented.

[0016] Due to the adoption of the above technical solution, the present invention has the following advantages and positive effects compared with the prior art:

[0017] The advantages of the present invention are mainly aimed at cache management, which can effectively improve the utilization rate and access speed of cache space. If a data block is only partially occupied, it can be split into smaller data blocks with 64 bytes as a unit, and head and tail pointers are defined for each new data block to improve storage efficiency. If the occupancy rate of the data block is low, the smaller data blocks can be merged into a larger data block, and the corresponding head and tail pointers can be merged, which is convenient for management and improves the real-time performance of network device scheduling. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 The switch hardware architecture of the present invention;

[0019] Figure 2 This is a frame exchange architecture diagram of the present invention;

[0020] Figure 3 This is a schematic diagram of cache space division;

[0021] Figure 4 This is a flow chart of the onboard high-speed switching and storage integrated cache control method of the present invention;

[0022] Figure 5 FIG. 4 is a schematic diagram of a switch according to an embodiment of the present invention. DETAILED DESCRIPTION

[0023] The technical solution proposed by the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent according to the following description and claims.

[0024] For event-triggered services, all network services are triggered based on specific events, which are often changes in service and network status. Since network status changes are difficult to predict, the transmission of event-triggered services is usually uncertain in time. In the corresponding event-triggered transmission time slot, since the transmission time of event-triggered services of each end system is uncertain, conflicts may occur during the transmission process.

[0025] The internal components of the satellite-borne high-reliability real-time network end node equipment include timestamp processing layer, arrival time scheduling and departure time scheduling layer, destination query and redundancy elimination layer, and switching layer. The function of cache control is to put the data packets from the host port into the corresponding cache according to the preset rules.

[0026] Embodiment 1

[0027] See also Figures 1 to 5 The technical solution of the present invention is: a method for controlling an integrated cache of onboard high-speed switching storage, comprising: dividing the cache into a plurality of blocks by a preset minimum unit or an integer multiple of the minimum unit, wherein each block is composed of a meta area and a data area, the meta area records the information of the data block, and the data area is a real allocated memory area; receiving a data packet from an input port, and storing the received data in a corresponding cache; and when a cache address larger than the minimum unit is empty after each block receives the corresponding data, dividing the empty cache address into independent blocks by a preset minimum unit or an integer multiple of the minimum unit.

[0028] The above method realizes efficient use of the cache area and fast reading and writing by dividing the cache area into areas of different sizes. The present invention divides the cache block into areas of different sizes and organizes the heap memory space in the form of blocks. Each block consists of a meta area and a data area. The meta area records the information of the data block (data area size, free flag, pointer, etc.). The data area is the real allocated memory area, and the first byte address of the data area is the returned address. The sizes of the data area are 64 bytes, 128 bytes, and 256 bytes respectively.

[0029] In one embodiment of the present invention, the size of the data area of ​​the block is 64 bytes or an integral multiple of 64 bytes.

[0030] In one embodiment of the present invention, the information of the data block recorded in the meta area includes the data area size, a free flag, and a pointer.

[0031] In one embodiment of the present invention, the first byte address of the data area is the returned address.

[0032] In one embodiment of the present invention, when a data packet is received through an input port, an empty data area is searched from the beginning in the block, the corresponding data packet is stored and the starting address is returned.

[0033] In one embodiment of the present invention, when the size of the received data packet is larger than the first data area found, the data areas of the remaining one or more blocks are merged to cache the data packet.

[0034] In one embodiment of the present invention, when the received data packet is a multicast packet, the high-order address is used for matching and the low-order address is used as the index of the cache block; when the received data packet is a broadcast packet or a unicast packet, the given index is used and a block in the multicast cache is used.

[0035] See also Figure 5 , which is the cache management process in the frame switching process. All frame switching planes in the switch share a dual-port DDR to store the switched TT frames, RC frames, BE frames, and PCF frames. Figure 2 As shown, each frame arriving from the port (pdata) is first written into the designated location in the DDR (Double Data Rate, double rate synchronous dynamic random access memory) according to the offline planning result after time analysis by the time synchronization module (timestamp). For TT frames, the DDR read-write control logic of the TT switching plane in a specific time slot will read the TT frame designated by the offline planning, and after being buffered by the schedule_cache plan cache, it will be sent to the corresponding schedule_port plan port module. The scheduler module will generate the corresponding RISC-V instructions in advance according to the offline scheduling table, and execute the transmission and reception of the TT data frame in the module according to the RISC-V instructions, thereby playing the channel control function. The TT data frame is then sent out through the lookup module according to the lookup table stored in the lookup module to query the corresponding sending port.

[0036] Embodiment 2

[0037] Based on the same concept, the present invention also provides a satellite-borne high-speed switching and storage integrated cache control device, including: a partition unit, used to divide the cache into multiple blocks according to a preset minimum unit or an integer multiple of the minimum unit, wherein each block is composed of a meta area and a data area, the meta area records the information of the data block, and the data area is a truly allocated memory area; a cache unit, used to receive data packets from an input port and store the received data into a corresponding cache; a reorganization unit, used to divide the empty cache address into independent blocks according to a preset minimum unit or an integer multiple of the minimum unit after each block has received the corresponding data and still has an empty cache address larger than the minimum unit; or, when the size of the received data packet is larger than the first data area found, merge the data areas of the remaining one or more blocks to cache the data packet.

[0038] Embodiment 3

[0039] Based on the same concept, the present invention also provides an electronic device, comprising: a memory, the memory is used to store a processing program; a processor, the processor implements the on-board high-speed switching storage integrated cache control method when executing the processing program.

[0040] Based on the same concept, the present invention also provides a readable storage medium, on which a processing program is stored. When the processing program is executed by a processor, the on-board high-speed switching storage integrated cache control method is implemented.

[0041] If the onboard high-speed switching storage integrated cache control method is implemented in the form of program instructions and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this embodiment is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of software. The computer software is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present disclosure. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc., various media that can store program codes.

[0042] Those skilled in the art can clearly understand that, for the sake of convenience and brevity in description, the identification content specifically executed by the above-described system and device can refer to the corresponding process in the aforementioned method embodiment.

[0043] The embodiments of the present invention are described in detail above in conjunction with the accompanying drawings, but the present invention is not limited to the above embodiments. Even if various changes are made to the present invention, if these changes fall within the scope of the claims of the present invention and their equivalents, they still fall within the protection scope of the present invention.

Claims

1. A method for controlling onboard high-speed switching and storage integrated cache, characterized in that: include: Divide the cache into multiple blocks based on the preset minimum unit or integer multiples of the minimum unit, where each block consists of a meta area and a data area. The meta area records the information of the data block, and the data area is the actual allocated memory area. Receive data packets from the input port and store the received data in the corresponding cache; when receiving data packets through the input port, search for an empty data area from the beginning in the block, store the corresponding data packet and return the starting address; In the case that after each block has received the corresponding data and still has an empty cache address larger than the minimum unit, the empty cache address is divided into independent blocks according to a preset minimum unit or an integer multiple of the minimum unit; in the case that the size of the received data packet is larger than the first data area found, the data areas of the remaining one or more blocks are merged to cache the data packet; in the case that the received data packet is a multicast packet, the high-order address is used for matching and the low-order address is used as the index of the cache block; in the case that the received data packet is a broadcast packet or a unicast packet, a given index is used to use a block in the multicast cache.

2. The on-board high-speed switching storage integrated cache control method according to claim 1, characterized in that: The size of the data area of ​​the block is 64 bytes or an integral multiple of 64 bytes.

3. The on-board high-speed switching storage integrated cache control method according to claim 1, characterized in that: The meta area records the information of the data block including the data area size, free flag, and pointer.

4. The on-board high-speed switching storage integrated cache control method according to claim 1, characterized in that: The first byte address of the data area is the returned address.

5. A satellite-borne high-speed switching and storage integrated cache control device, characterized in that: include: Partition unit, used to divide the cache into multiple blocks with a preset minimum unit or an integer multiple of the minimum unit, where each block consists of a meta area and a data area. The meta area records the information of the data block, and the data area is the actual allocated memory area; The cache unit is used to receive data packets from the input port and store the received data in the corresponding cache; when receiving a data packet through the input port, it searches for an empty data area from the beginning in the block, stores the corresponding data packet and returns the starting address; A reorganization unit is used to divide the empty cache address into independent blocks by a preset minimum unit or an integer multiple of the minimum unit when a cache address larger than the minimum unit is empty after each block has received the corresponding data; or, when the size of the received data packet is larger than the first data area found, merge the data areas of the remaining one or more blocks to cache the data packet; when the received data packet is a multicast packet, use the high-order address for matching and use the low-order address as the index of the cache block; when the received data packet is a broadcast packet or a unicast packet, use a given index and use a block in the multicast cache.

6. An electronic device, characterized in that: include: A memory, the memory being used to store a processing program; A processor, wherein when executing the processing program, the processor implements the on-board high-speed switching storage integrated cache control method as described in any one of claims 1 to 4.

7. A readable storage medium, characterized in that: The readable storage medium stores a processing program, and when the processing program is executed by the processor, the on-board high-speed switching storage integrated cache control method as described in any one of claims 1 to 4 is implemented.

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