A video preview method, apparatus, device, and storage medium

Abstract

The present application discloses a video preview method, an apparatus, a video preview device and a computer-readable storage medium. The video preview device is respectively connected to N conversion chips through N interfaces, and each of the conversion chips is connected to M cameras. The method includes: creating N×M display windows and initializing V4L2 device nodes; receiving N MIPI signals sent by the N conversion chips; wherein each of the conversion chips converts M camera signals collected by the M cameras into one MIPI signal; decomposing each MIPI signal into M MIPI sub-signals, and sending each MIPI sub-signal to the corresponding display window through multiplexing the V4L2 device nodes, so that each display window displays the corresponding video based on the received MIPI sub-signal. The present application can simultaneously implement the preview of N×M channels of camera videos.

Description

Technical Field

[0001] This application relates to the field of computer technology, and more specifically, to a video preview method, an apparatus, a video preview device, and a computer-readable storage medium. Background Art

[0002] In the related art, the AIS (Automotive imaging system) architecture on the Qualcomm platform can support simultaneous preview of multiple camera signals. A conversion chip is externally disposed on the hardware to convert 4-channel camera signals into MIPI (Mobile Industry Processor Interface) signals. On the software side, the V4L2 (Video for linux2) interface is registered in the android system to obtain video data for each channel, and ultimately, simultaneous preview of up to 4 cameras can be achieved. However, for some scenarios that require preview of more camera videos, the demand cannot be met yet.

[0003] Therefore, how to achieve simultaneous preview of multiple camera videos is a technical problem that needs to be solved by those skilled in the art. Summary of the Invention

[0004] The purpose of this application is to provide a video preview method, an apparatus, a video preview device, and a computer-readable storage medium, which achieve simultaneous preview of multiple camera videos.

[0005] To achieve the above purpose, this application provides a video preview method, which is applied to a video preview device. The video preview device is respectively connected to N conversion chips through N interfaces, and each conversion chip is connected to M cameras. The method includes:

[0006] Create N×M display windows and initialize the V4L2 device node;

[0007] Receive N MIPI signals sent by the N conversion chips; wherein, each conversion chip converts M camera signals collected by the M cameras into one MIPI signal;

[0008] Decompose each MIPI signal into M MIPI sub-signals, and send each MIPI sub-signal to the corresponding display window through multiplexing the V4L2 device node, so that each display window displays the corresponding video based on the received MIPI sub-signal.

[0009] Wherein, before creating the N×M display windows, it further includes:

[0010] Register N camera drivers and N MIPI drivers; wherein, each of the camera drivers and each MIPI driver is used to communicate with a corresponding conversion chip.

[0011] Wherein, the decomposing each MIPI signal into M MIPI sub-signals includes:

[0012] In each MIPI driver, according to the identifiers corresponding to the M cameras respectively, decompose each MIPI signal into M MIPI sub-signals by using virtual channels.

[0013] Wherein, the creating N×M display windows and initializing the V4L2 device nodes includes:

[0014] Create N threads, and use each thread to create M display windows respectively, and initialize the V4L2 device nodes corresponding to each MIPI.

[0015] Wherein, before creating the N threads, it further includes:

[0016] Register the V4L2 device nodes; wherein, the V4L2 device nodes include CSID nodes, ISPIF nodes and VFE nodes.

[0017] Wherein, if N is 2, then the registering the V4L2 device nodes includes:

[0018] Register ISPIF nodes, a first CSID node, a second CSID node, a first VFE node and a second VFE node;

[0019] Correspondingly, the creating N threads, using each thread to create M display windows respectively, and initializing the V4L2 device nodes corresponding to each MIPI includes:

[0020] Create a first thread and a second thread, and use the first thread and the second thread to create M display windows respectively;

[0021] Use the first thread to initialize the ISPIF node, the first CSID node and the first VFE node corresponding to the first MIPI;

[0022] Use the second thread to initialize the ISPIF node, the second CSID node and the second VFE node corresponding to the second MIPI;

[0023] Correspondingly, the receiving N MIPI signals sent by the N conversion chips includes:

[0024] Use the first thread to receive the first MIPI signal sent by the first conversion chip, and use the second thread to receive the second MIPI signal sent by the second conversion chip;

[0025] Correspondingly, the step of decomposing each MIPI signal into M MIPI sub-signals and sending each MIPI sub-signal to the corresponding display window by multiplexing the V4L2 device node includes:

[0026] Use the first thread to decompose the first MIPI signal into M first MIPI sub-signals, and use the second thread to decompose the second MIPI signal into M second MIPI sub-signals;

[0027] Use the first thread to send the M first MIPI sub-signals to the corresponding display window through the ISPIF node, the first CSID node, and the first VFE node;

[0028] Use the second thread to send the M second MIPI sub-signals to the corresponding display window through the ISPIF node, the second CSID node, and the second VFE node.

[0029] To achieve the above object, the present application provides a video preview device, which is applied to a video preview device. The video preview device is connected to N conversion chips through N interfaces, and each conversion chip is connected to M cameras. The device includes:

[0030] A creation module, configured to create N×M display windows and initialize the V4L2 device node;

[0031] A receiving module, configured to receive N MIPI signals sent by the N conversion chips; wherein, each conversion chip converts M camera signals collected by the M cameras into one MIPI signal;

[0032] A sending module, configured to decompose each MIPI signal into M MIPI sub-signals, and send each MIPI sub-signal to the corresponding display window by multiplexing the V4L2 device node, so that each display window displays the corresponding video based on the received MIPI sub-signal.

[0033] To achieve the above object, the present application provides a video preview device, including:

[0034] A memory, configured to store a computer program;

[0035] A processor, configured to implement the steps of the above video preview method when executing the computer program.

[0036] To achieve the above object, the present application provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the above video preview method are implemented.

[0037] As can be seen from the above solution, a video preview method provided by the present application is applied to a video preview device. The video preview device is respectively connected to N conversion chips through N interfaces, and each conversion chip is connected to M cameras. The method includes: creating N×M display windows and initializing V4L2 device nodes; receiving N MIPI signals sent by the N conversion chips; wherein each conversion chip converts M camera signals collected by the M cameras into one MIPI signal; decomposing each MIPI signal into M MIPI sub-signals, and sending each MIPI sub-signal to the corresponding display window through multiplexing the V4L2 device nodes, so that each display window displays the corresponding video based on the received MIPI sub-signal.

[0038] Thus, in the video preview method provided by the present application, N MIPI signals can be received simultaneously through N conversion chips, and at the same time, each conversion chip is respectively connected to M cameras, so that M camera signals can be received simultaneously. By multiplexing the V4L2 device nodes, preview of N×M channels of camera videos can be achieved simultaneously. The present application also discloses a video preview device, a video preview device and a computer-readable storage medium, which can also achieve the above technical effects.

[0039] It should be understood that the above general description and the following detailed description are only exemplary and do not limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings. The drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification, and are used together with the following specific embodiments to explain the present disclosure, but do not constitute a limitation to the present disclosure. In the drawings:

[0041] Figure 1 is a flowchart of a video preview method shown according to an exemplary embodiment;

[0042] Figure 2 is a flowchart of another video preview method shown according to an exemplary embodiment;

[0043] Figure 3 Flow chart of yet another video preview method shown according to an exemplary embodiment;

[0044] Figure 4 Structural diagram of a video preview device shown according to an exemplary embodiment;

[0045] Figure 5 Structural diagram of a video preview device shown according to an exemplary embodiment. Detailed implementation manners

[0046] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application. In addition, in the embodiments of the present application, "first", "second", etc. are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence.

[0047] The embodiments of the present application disclose a video preview method, and the execution subject is a video preview device. In terms of software, the video preview device can be implemented based on the AIS architecture. In terms of hardware, N interfaces are respectively connected to N conversion chips. The interface can specifically be a CSIPHY (camera serial interface physical) interface. Each conversion chip is connected to M cameras. That is, in this embodiment, N×M channels of camera videos can be previewed through the video preview device. Due to the interface limitation of the conversion chip, generally speaking, the conversion chip can be connected to 4 cameras, that is, M is 4. The value of N depends on the number of interfaces included in the video preview device and the operating ability of the chips in the video preview device.

[0048] See Figure 1 , a flow chart of a video preview method shown according to an exemplary embodiment, as Figure 1 shown, includes:

[0049] S101: Create N×M display windows and initialize the V4L2 device node;

[0050] In this step, N×M display windows are created, and each display window is used to display one channel of camera video. Then, the V4L2 device nodes are initialized, which may include CSID (camera serial interface decoder) nodes, ISPIF (Image Signal Processor interface) nodes, and VFE (Video front end) nodes.

[0051] As a feasible implementation manner, this step may include: creating N threads, and using each of the threads to create M display windows respectively, and initializing the V4L2 device nodes corresponding to each channel of MIPI. In a specific implementation, N threads are created, and each thread corresponds to one channel of MIPI, that is, each thread is used to create M display windows and initialize the V4L2 device nodes corresponding to each channel of MIPI. The N threads can execute the corresponding operations in parallel. The number of different types of nodes initialized for each channel of MIPI is not limited here. For example, for the ISPIF node, generally only 1 ISPIF node is included in the AIS architecture. Therefore, 1 ISPIF node is initialized for each channel of MIPI and reused in subsequent transmission. For the CSID node, generally 4 CSID nodes are included in the AIS architecture. Therefore, 1 CSID node can be initialized for each channel of MIPI, or 2 CSID nodes can be initialized for each channel of MIPI. For the VFE node, generally 2 VFE nodes are included in the AIS architecture. Therefore, 1 VFE node can be initialized for each channel of MIPI.

[0052] S102: Receive N channels of MIPI signals sent by the N conversion chips; wherein, each of the conversion chips converts M channels of camera signals collected by the M cameras into one channel of MIPI signal;

[0053] In a specific implementation, the cameras collect camera signals and send them to the corresponding conversion chips. After each conversion chip receives the M channels of camera signals of the M cameras connected to it, it converts the M channels of camera signals into one channel of MIPI signal and transmits it to the video preview device through the corresponding interface, that is, the video preview device receives N channels of MIPI signals through the N conversion chips.

[0054] S103: Decompose each channel of the MIPI signal into M channels of MIPI sub-signals, and send each channel of the MIPI sub-signal to the corresponding display window by multiplexing the V4L2 device nodes, so that each display window displays the corresponding video based on the received MIPI sub-signal.

[0055] In this step, each received MIPI signal is decomposed into M MIPI sub-signals by using virtual channels. The camera signals collected by each camera contain its own identifier. It can be understood that there is a corresponding data stream identifier for each camera signal. Correspondingly, the received MIPI signal can be decomposed into M MIPI sub-signals according to the identifier (data stream identifier) corresponding to the camera.

[0056] Furthermore, format conversion is performed on each MIPI sub-signal to convert it into a format that can be displayed by the display window, and then it is sent to the corresponding display window. Each display window displays the corresponding video. That is, each display window object waits and receives the corresponding video data in a loop according to the data stream identifier and then displays it, and then releases the data buffer, and so on in a loop.

[0057] It should be noted that since the number of different types of V4L2 device nodes in the AIS architecture cannot reach N×M, it is impossible to transmit each MIPI sub-signal through a different V4L2 device node. Therefore, in this embodiment, different types of V4L2 device nodes need to be multiplexed to realize sending M MIPI sub-signals to M display windows. Specifically, each MIPI sub-signal needs to be transmitted to the corresponding display window through the ISPIF node, CSID node, and VFE node in sequence. Generally, the AIS architecture includes 1 ISPIF node, 4 CSID nodes, and 2 VFE nodes. As a feasible implementation, all MIPI sub-signals share 1 ISPIF node, (N×M) / 4 MIPI sub-signals share 1 CSID node, and (N×M) / 2 MIPI sub-signals share 1 VFE node.

[0058] It can be seen that the video preview method provided by the embodiment of the present application can simultaneously receive N MIPI signals through N conversion chips, and each conversion chip is respectively connected to M cameras and can simultaneously receive M camera signals. By multiplexing V4L2 device nodes, the preview of N×M camera videos can be simultaneously realized.

[0059] The embodiment of the present application discloses a video preview method. Compared with the previous embodiment, this embodiment further explains and optimizes the technical solution. Specifically:

[0060] See Figure 2 , according to the flowchart of another video preview method shown in an exemplary embodiment, as Figure 2 shown, including:

[0061] S201: Register N camera drivers and N MIPI drivers; wherein, each of the camera drivers and each of the MIPI drivers is used to communicate with the corresponding conversion chip;

[0062] In this step, the main program registers N camera drivers and N MIPI drivers in the AIS architecture. The camera drivers and MIPI drivers are used to communicate with the corresponding conversion chips when starting up to transmit MIPI signals. The N MIPI drivers include their respective initialization parameters, corresponding CSID channels, ISPIF channels, VFE channels, etc. The initialization parameters can be camera parameters, display parameters, etc. The N MIPI signals can ensure the mutual independence of the subsequent N MIPI signals.

[0063] S202: Register V4L2 device nodes; among them, the V4L2 device nodes include CSID nodes, ISPIF nodes, and VFE nodes;

[0064] In this step, the main program registers V4L2 device nodes in the android system, which include CSID nodes, ISPIF nodes, and VFE nodes. The number of different types of nodes in this embodiment is not limited. For example, for ISPIF nodes, generally only 1 ISPIF node is included in the AIS architecture, so 1 ISPIF node is registered. For CSID nodes and VFE nodes, generally multiple CSID nodes and VFE nodes are included in the AIS architecture, so 1 or more CSID nodes and VFE nodes can be registered. It can be understood that in order to reduce the subsequent reuse of nodes, as many nodes as possible can be registered in this step to improve the reliability of subsequent signal transmission.

[0065] S203: Create N threads, and use each thread to create M display windows respectively, and initialize the V4L2 device nodes corresponding to each MIPI signal path;

[0066] S204: Use the N threads to receive N MIPI signals sent by the N conversion chips respectively; among them, each conversion chip converts M camera signals collected by the M cameras into one MIPI signal;

[0067] S205: Use each thread to decompose each MIPI signal into M MIPI sub-signals according to the identifiers corresponding to the M cameras in each MIPI driver, and use virtual channels;

[0068] S206: Use each thread to send each MIPI sub-signal to the corresponding display window through the corresponding CSID node, ISPIF node, and VFE node, so that each display window can display the corresponding video based on the received MIPI sub-signal.

[0069] An embodiment of the present application discloses a video preview method. Compared with the previous embodiment, the technical solution in this embodiment is further described and optimized. Specifically: In this embodiment, a first conversion chip and a second conversion chip are externally disposed on the video preview device and are respectively connected to four cameras. The first conversion chip is connected to the CSIPHY1 interface of the video preview device, and the second conversion chip is connected to the CSIPHY_{2} interface of the video preview device.

[0070] See Figure 3 , a flowchart of another video preview method shown according to an exemplary embodiment, as Figure 3 shown, includes:

[0071] S301: Register two camera drivers and two MIPI drivers; wherein, each of the camera drivers and each MIPI driver is used to communicate with the corresponding conversion chip;

[0072] S302: Register an ISPIF node, a first CSID node, a second CSID node, a first VFE node, and a second VFE node;

[0073] S303: Create a first thread and a second thread;

[0074] In this embodiment, the main program registers two camera drivers and two MIPI drivers, registers an ISPIF node, a first CSID node, a second CSID node, a first VFE node, and a second VFE node, and creates two threads, namely the first thread and the second thread.

[0075] S304: Use the first thread to create four display windows;

[0076] S305: Use the second thread to create four display windows;

[0077] S306: Use the first thread to initialize the ISPIF node, the first CSID node, and the first VFE node corresponding to the first MIPI;

[0078] S307: Use the second thread to initialize the ISPIF node, the second CSID node, and the second VFE node corresponding to the second MIPI;

[0079] S308: Use the first thread to receive the first MIPI signal sent by the first conversion chip;

[0080] S309: Use the second thread to receive the second MIPI signal sent by the second conversion chip;

[0081] S310: Use the first thread to decompose the first MIPI signal into four first MIPI sub - signals;

[0082] S311: Use the second thread to decompose the second MIPI signal into four second MIPI sub - signals;

[0083] S312: Use the first thread to send the four first MIPI sub - signals to corresponding display windows through the ISPIF node, the first CSID node, and the first VFE node;

[0084] S313: Use the second thread to send the four second MIPI sub - signals to corresponding display windows through the ISPIF node, the second CSID node, and the second VFE node.

[0085] In this embodiment, the first thread is used to create four display windows, initialize the ISPIF node, the first CSID node, and the first VFE node corresponding to the first MIPI, receive the first MIPI signal sent by the first conversion chip, decompose the first MIPI signal into four first MIPI sub - signals, and send the four first MIPI sub - signals to corresponding display windows through the ISPIF node, the first CSID node, and the first VFE node. The second thread is used to create four display windows, initialize the ISPIF node, the second CSID node, and the second VFE node corresponding to the second MIPI, receive the second MIPI signal sent by the second conversion chip, decompose the second MIPI signal into four second MIPI sub - signals, and send the four second MIPI sub - signals to corresponding display windows through the ISPIF node, the second CSID node, and the second VFE node.

[0086] It can be seen that in this embodiment, 8 - channel camera video can be previewed simultaneously through two conversion chips.

[0087] Next, a video preview device provided by an embodiment of the present application will be introduced. A video preview device described below can be referred to each other with a video preview method described above.

[0088] See Figure 4 , a structural diagram of a video preview device shown according to an exemplary embodiment, as Figure 4 shown, includes:

[0089] A creation module 401, configured to create N×M display windows and initialize V4L2 device nodes;

[0090] A receiving module 402, configured to receive N MIPI signals sent by the N conversion chips; wherein, each of the conversion chips converts M camera signals collected by M cameras into one MIPI signal.

[0091] A sending module 403, configured to decompose each MIPI signal into M MIPI sub-signals, and send each MIPI sub-signal to a corresponding display window through multiplexing the V4L2 device node, so that each display window displays a corresponding video based on the received MIPI sub-signal.

[0092] It can be seen that the video preview device provided by the embodiment of the present application can simultaneously receive N MIPI signals through N conversion chips, and each conversion chip is respectively connected to M cameras, so that M camera signals can be received simultaneously. By multiplexing the V4L2 device node, preview of N×M channels of camera videos can be realized simultaneously.

[0093] Based on the above embodiment, as a preferred embodiment, it further includes:

[0094] A first registration module, configured to register N camera drivers and N MIPI drivers; wherein, each camera driver and each MIPI driver are used to communicate with a corresponding conversion chip.

[0095] Based on the above embodiment, as a preferred embodiment, the sending module 403 includes:

[0096] A decomposition unit, configured to decompose each MIPI signal into M MIPI sub-signals by using virtual channels according to the identifiers respectively corresponding to M cameras in each MIPI driver.

[0097] A sending unit, configured to send each MIPI sub-signal to a corresponding display window through multiplexing the V4L2 device node, so that each display window displays a corresponding video based on the received MIPI sub-signal.

[0098] Based on the above embodiment, as a preferred embodiment, the creating module 401 is specifically configured to: create N threads, use each thread to respectively create M display windows, and initialize the V4L2 device nodes corresponding to each MIPI.

[0099] Based on the above embodiment, as a preferred embodiment, it further includes:

[0100] A second registration module, configured to register V4L2 device nodes; wherein, the V4L2 device nodes include CSID nodes, ISPIF nodes and VFE nodes.

[0101] Based on the above embodiments, as a preferred embodiment, if N is 2, the second registration module is specifically configured to: register an ISPIF node, a first CSID node, a second CSID node, a first VFE node, and a second VFE node;

[0102] Correspondingly, the creation module 401 is specifically configured to: create a first thread and a second thread, and use the first thread and the second thread to create M display windows respectively; use the first thread to initialize the ISPIF node, the first CSID node, and the first VFE node corresponding to the first path of MIPI; use the second thread to initialize the ISPIF node, the second CSID node, and the second VFE node corresponding to the second path of MIPI;

[0103] Correspondingly, the receiving module 402 is specifically configured to: use the first thread to receive the first path of MIPI signal sent by the first conversion chip, and use the second thread to receive the second path of MIPI signal sent by the second conversion chip;

[0104] Correspondingly, the sending module 403 is specifically configured to: use the first thread to decompose the first path of MIPI signal into M first MIPI sub-signals, and use the second thread to decompose the second path of MIPI signal into M second MIPI sub-signals; use the first thread to send the M first MIPI sub-signals to the corresponding display windows through the ISPIF node, the first CSID node, and the first VFE node; use the second thread to send the M second MIPI sub-signals to the corresponding display windows through the ISPIF node, the second CSID node, and the second VFE node.

[0105] Regarding the device in the above embodiments, the specific manners in which each module performs operations have been described in detail in the embodiments related to the method, and will not be elaborated herein.

[0106] Based on the hardware implementation of the above program modules, and in order to implement the method of the embodiments of the present application, the embodiments of the present application further provide a video preview device, Figure 5 Shown is a structural diagram of a video preview device according to an exemplary embodiment, as Figure 5 shown, the video preview device includes:

[0107] A communication interface 1, capable of interacting with other devices such as network devices for information;

[0108] A processor 2, connected to the communication interface 1 to implement information interaction with other devices, and when running a computer program, executes the video preview method provided by one or more of the above technical solutions. And the computer program is stored on the memory 3.

[0109] Of course, in actual applications, the various components in the video preview device are coupled together through the bus system 4. It can be understood that the bus system 4 is used to implement the connection and communication between these components. In addition to the data bus, the bus system 4 also includes a power bus, a control bus, and a status signal bus. However, for the sake of clear illustration, in Figure 5 all kinds of buses are labeled as the bus system 4.

[0110] The memory 3 in the embodiment of the present application is used to store various types of data to support the operation of the video preview device. Examples of these data include: any computer program for operating on the video preview device.

[0111] It can be understood that the memory 3 can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM, Read Only Memory), a programmable read-only memory (PROM, Programmable Read-Only Memory), an erasable programmable read-only memory (EPROM, Erasable Programmable Read-Only Memory), an electrically erasable programmable read-only memory (EEPROM, Electrically Erasable Programmable Read-Only Memory), a ferromagnetic random access memory (FRAM, ferromagnetic random access memory), a flash memory (Flash Memory), a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM, Compact Disc Read-Only Memory); the magnetic surface memory can be a disk memory or a tape memory. The volatile memory can be a random access memory (RAM, Random Access Memory), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as a static random access memory (SRAM, Static Random Access Memory), a synchronous static random access memory (SSRAM, Synchronous Static Random Access Memory), a dynamic random access memory (DRAM, Dynamic Random Access Memory), a synchronous dynamic random access memory (SDRAM, Synchronous Dynamic Random Access Memory), a double data rate synchronous dynamic random access memory (DDR SDRAM, Double Data Rate Synchronous Dynamic Random Access Memory), an enhanced synchronous dynamic random access memory (ESDRAM, Enhanced Synchronous Dynamic Random Access Memory), a sync link dynamic random access memory (SLDRAM, SyncLink Dynamic Random Access Memory), and a direct rambus random access memory (DRRAM, Direct Rambus Random Access Memory).The memory 3 described in the embodiments of the present application is intended to include, but is not limited to, these and any other suitable types of memories.

[0112] The method disclosed in the embodiments of the present application above can be applied to the processor 2 or implemented by the processor 2. The processor 2 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit in the hardware of the processor 2 or the instructions in the form of software. The above-mentioned processor 2 may be a general-purpose processor, a DSP, or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The processor 2 can implement or execute each method, step, and logic block diagram disclosed in the embodiments of the present application. The general-purpose processor may be a microprocessor or any conventional processor, etc. Combining the steps of the method disclosed in the embodiments of the present application, it can be directly embodied as being executed and completed by the hardware decoding processor, or executed and completed by the combination of the hardware and software modules in the decoding processor. The software module may be located in the storage medium, and this storage medium is located in the memory 3. The processor 2 reads the program in the memory 3 and combines its hardware to complete the steps of the foregoing method.

[0113] When the processor 2 executes the program, it implements the corresponding processes in each method of the embodiments of the present application. For the sake of brevity, it will not be elaborated here.

[0114] In an exemplary embodiment, the embodiments of the present application also provide a storage medium, namely a computer storage medium, specifically a computer-readable storage medium. For example, it includes the memory 3 storing a computer program, and the above computer program can be executed by the processor 2 to complete the steps described in the foregoing method. The computer-readable storage medium may be a FRAM, ROM, PROM, EPROM, EEPROM, Flash Memory, magnetic surface memory, optical disc, or CD-ROM, etc.

[0115] Those of ordinary skill in the art can understand that all or part of the steps to implement the above method embodiments can be completed by hardware related to program instructions. The foregoing program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps including the above method embodiments; and the foregoing storage medium includes: various media such as mobile storage devices, ROM, RAM, magnetic disks, or optical discs that can store program codes.

[0116] Alternatively, if the above integrated units of the present application are implemented in the form of software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiments of the present application, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a video preview device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in the various embodiments of the present application. The foregoing storage medium includes: various media that can store program codes, such as removable storage devices, ROM, RAM, magnetic disks, or optical discs.

[0117] As described above, the above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A video preview method, characterized in that, Applied to a video preview device, the video preview device is respectively connected to N conversion chips through N interfaces, and each of the conversion chips is connected to M cameras. The method includes: Register a V4L2 device node; Create N threads, and use each thread to create M display windows respectively, and initialize the V4L2 device nodes corresponding to each MIPI path; Receive N MIPI signals sent by the N conversion chips; wherein, each of the conversion chips converts M camera signals collected by the M cameras into one MIPI signal; Decompose each MIPI signal into M MIPI sub-signals, and send each MIPI sub-signal to the corresponding display window through multiplexing the V4L2 device nodes, so that each display window displays the corresponding video based on the received MIPI sub-signal; If N is equal to 2, then the registering of the V4L2 device node includes: Register an ISPIF node, a first CSID node, a second CSID node, a first VFE node and a second VFE node; Correspondingly, the creating of N threads, using each thread to create M display windows respectively, and initializing the V4L2 device nodes corresponding to each MIPI path includes: Create a first thread and a second thread, and use the first thread and the second thread to create M display windows respectively; Use the first thread to initialize the ISPIF node, the first CSID node and the first VFE node corresponding to the first MIPI path; Use the second thread to initialize the ISPIF node, the second CSID node and the second VFE node corresponding to the second MIPI path; Correspondingly, the receiving of the N MIPI signals sent by the N conversion chips includes: Use the first thread to receive the first MIPI signal sent by the first conversion chip, and use the second thread to receive the second MIPI signal sent by the second conversion chip; Correspondingly, the decomposing of each MIPI signal into M MIPI sub-signals, and sending each MIPI sub-signal to the corresponding display window through multiplexing the V4L2 device nodes includes: Use the first thread to decompose the first MIPI signal into M first MIPI sub-signals, and use the second thread to decompose the second MIPI signal into M second MIPI sub-signals; Use the first thread to send the M first MIPI sub-signals to the corresponding display window through the ISPIF node, the first CSID node and the first VFE node; Use the second thread to send the M second MIPI sub-signals to the corresponding display window through the ISPIF node, the second CSID node and the second VFE node.

2. The video preview method according to claim 1, wherein Before creating the N×M display windows, it further includes: Register N camera drivers and N MIPI drivers; wherein, each camera driver and each MIPI driver are used to communicate with the corresponding conversion chip.

3. The video preview method according to claim 2, wherein The decomposing each path of the MIPI signal into M paths of MIPI sub-signals includes: In each path of the MIPI driver, according to the identifiers respectively corresponding to the M cameras, each path of the MIPI signal is decomposed into M paths of MIPI sub-signals by using virtual channels.

4. A video preview device, characterized in that, Applied to a video preview device, the video preview device is respectively connected to N conversion chips through N interfaces, and each of the conversion chips is connected to M cameras. The device includes: A second registration module, configured to: register a V4L2 device node; A creation module, configured to create N threads, use each of the threads to respectively create M display windows, and initialize the V4L2 device nodes corresponding to each path of MIPI; A receiving module, configured to receive N paths of MIPI signals sent by the N conversion chips; wherein, each of the conversion chips converts M paths of camera signals collected by the M cameras into one path of MIPI signal; A sending module, configured to decompose each path of the MIPI signal into M paths of MIPI sub-signals, and send each path of the MIPI sub-signals to the corresponding display window by multiplexing the V4L2 device nodes, so that each display window displays the corresponding video based on the received MIPI sub-signals; If N is equal to 2, the second registration module is configured to: register an ISPIF node, a first CSID node, a second CSID node, a first VFE node, and a second VFE node; Correspondingly, the creation module is configured to: create a first thread and a second thread, use the first thread and the second thread to respectively create M display windows; use the first thread to initialize the ISPIF node, the first CSID node, and the first VFE node corresponding to the first path of MIPI; use the second thread to initialize the ISPIF node, the second CSID node, and the second VFE node corresponding to the second path of MIPI; Correspondingly, the receiving module is configured to: use the first thread to receive the first path of MIPI signal sent by the first conversion chip, and use the second thread to receive the second path of MIPI signal sent by the second conversion chip; Correspondingly, the sending module is configured to: use the first thread to decompose the first path of MIPI signal into M paths of first MIPI sub-signals, and use the second thread to decompose the second path of MIPI signal into M paths of second MIPI sub-signals; use the first thread to send the M paths of the first MIPI sub-signals to the corresponding display window through the ISPIF node, the first CSID node, and the first VFE node; use the second thread to send the M paths of the second MIPI sub-signals to the corresponding display window through the ISPIF node, the second CSID node, and the second VFE node.

5. The video preview device according to claim 4, characterized in that It further includes: A first registration module, configured to register N camera drivers and N paths of MIPI drivers; wherein, each of the camera drivers and each path of the MIPI drivers is used to communicate with the corresponding conversion chip.

6. The video preview device according to claim 5, characterized in that, The sending module includes: A decomposition unit, configured to decompose each MIPI signal into M MIPI sub-signals by using virtual channels according to the identifiers respectively corresponding to M cameras in each MIPI drive; A sending unit, configured to send each MIPI sub-signal to a corresponding display window by multiplexing the V4L2 device node, so that each display window displays a corresponding video based on the received MIPI sub-signal.

7. A video preview device, characterized in that, Comprising: A memory, configured to store a computer program; A processor, configured to implement the steps of the video preview method according to any one of claims 1 to 3 when executing the computer program.

8. A computer-readable storage medium, characterized in that, A computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps of the video preview method according to any one of claims 1 to 3 are implemented.

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