A method for manufacturing a multilayer PCB substrate
By employing a method of thickening the circuit pattern and a pattern electroplating process in the fabrication of multilayer PCB substrates, combined with an insulating adhesive layer to form board unit, the high cost and resource waste of thick copper circuit patterns are solved, achieving cost control and resource conservation.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SUNSHINE GLOBAL CIRCUITS CO LTD
- Filing Date
- 2022-11-14
- Publication Date
- 2026-06-30
AI Technical Summary
In the current manufacturing of multilayer PCB substrates, the copper foil layer of thick copper circuit patterns is expensive and wastes copper resources significantly, making it difficult to meet the high thickness requirements while controlling costs.
The method of thickening the circuit pattern involves etching away non-circuit pattern areas and electroplating copper layers onto the copper foil layer. This is combined with an insulating adhesive layer to form a board unit, which meets the thickness requirements of thick copper circuit patterns while reducing the thickness of the copper foil layer and the cost.
This achieves the goal of meeting the thickness requirements of thick copper circuit patterns while reducing the cost of copper foil layers and copper consumption, thus saving copper resources.
Smart Images
Figure CN115767957B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of PCB manufacturing, and more specifically to a method for manufacturing a multilayer PCB substrate. Background Technology
[0002] like Figure 1 As shown, the existing method for manufacturing multilayer PCB substrates generally includes the following steps: (1) preparing several lamination plates 80, each lamination plate 80 including two copper foil layers and a lamination dielectric layer disposed between the two copper foil layers; (2) processing the copper foil layers of each lamination plate into circuit patterns 81; (3) arranging and bonding several lamination plates 80 with circuit patterns 81 and prepreg units alternately in sequence, and bonding the top and bottom lamination plates 80 together with an external copper layer 83 through the prepreg unit to form a multilayer PCB substrate. This multilayer PCB substrate can be processed into a PCB board after subsequent processes.
[0003] With the increasing demands on the current-carrying capacity of PCB boards from industries such as energy and electric vehicles, the requirements for the thickness of circuit patterns on multilayer PCB substrates are also becoming more stringent, often resulting in the use of thick copper circuit patterns. Within the industry, circuit patterns with a copper thickness of ≥3 oz are generally defined as thick copper circuit patterns. Currently, to meet the thickness requirements of thick copper circuit patterns, a copper foil layer of corresponding thickness is required, and non-circuit pattern areas are removed using an etching process on this layer, leaving the remaining circuit pattern areas to form the thick copper circuit pattern. However, as the thickness of the copper foil layer increases, its price increases significantly, especially the price difference between a copper foil layer with a thickness of ≥3 oz and a 1 oz layer. Therefore, while meeting the thickness requirements of thick copper circuit patterns, this often results in high copper foil layer costs for multilayer PCB substrates and a significant waste of copper resources. Summary of the Invention
[0004] In order to overcome the shortcomings of the prior art, the present invention aims to provide a method for manufacturing a multilayer PCB substrate. By combining steps S1-S3 and by reasonably setting steps S1 and S2, the thickness requirements of thick copper line pattern can be met while minimizing the thickness of the copper foil layer. This reduces the cost of the copper foil layer and the amount of copper consumed, thereby saving copper resources.
[0005] The objective of this invention is achieved through the following technical solution:
[0006] A method for manufacturing a multilayer PCB substrate includes the following steps:
[0007] Step S1: Fabricate the forming plate layer unit;
[0008] Step S2: A thick copper circuit pattern with a thickness of ≥3OZ is formed in the board layer unit by using a circuit pattern thickening method;
[0009] Step S3: N board layer units arranged from bottom to top and forming a thick copper circuit pattern are bonded together in an insulated manner, and the top and bottom board layer units are bonded to the external copper layer through the first insulating adhesive layer to form a multilayer PCB substrate; wherein, N≥2;
[0010] Wherein, step S1 includes sub-step S11 and sub-step S12:
[0011] Sub-step S11: Prepare the core board and process each core board copper layer to obtain the core board circuit pattern; wherein, the core board includes two core board copper layers and a core board dielectric layer disposed between the two core board copper layers;
[0012] Sub-step S12: A copper foil layer is bonded to the core board with the core board circuit pattern through a second insulating adhesive layer to form a board layer unit; wherein, the thickness of the board layer unit is ≥0.3mm;
[0013] The method for thickening the circuit pattern adopts the following steps: removing the non-circuit pattern area of the copper foil layer of the board unit, and applying a copper layer to the area of the copper foil layer corresponding to the circuit pattern using a pattern electroplating process to form a thick copper circuit pattern.
[0014] In sub-step S12, copper foil layers are bonded to both the upper and lower ends of the core board with the core board circuit pattern through a second insulating adhesive layer.
[0015] In step S2,
[0016] In step S3, any two adjacent plate units are bonded together by a third insulating adhesive layer.
[0017] In step S3, N board layer units, N-1 third insulating adhesive layers, two first insulating adhesive layers, and two external copper layers are stacked together and pressed together so that the N board layer units arranged from bottom to top and forming thick copper circuit patterns are bonded together in an insulated manner. The top and bottom board layer units are bonded to the external copper layers through the first insulating adhesive layers to form a multilayer PCB substrate.
[0018] The first insulating adhesive layer, the second insulating adhesive layer, and the third insulating adhesive layer are all semi-cured sheet units.
[0019] The thickness of the copper layer in the core board is 0.5OZ-1OZ.
[0020] In the circuit pattern thickening method, the non-circuit pattern area of the copper foil layer of the board unit is removed by etching process; the total thickness of the copper foil layer corresponding to the circuit pattern area and the copper layer plated by pattern electroplating process is 3.5-4OZ.
[0021] The thickness of the copper foil layer is 0.5OZ-1OZ.
[0022] In sub-step S11, after the core board is prepared, the non-circuit pattern area of the core board copper layer is removed by etching process, and the remaining circuit pattern area of the core board copper layer is formed as the core board circuit pattern.
[0023] Compared with the prior art, the beneficial effects of the present invention are as follows:
[0024] The present invention provides a method for manufacturing a multilayer PCB substrate, which combines steps S1-S3, and uses sub-steps S11 and S12 in step S1 to form a board layer unit. This allows for the application of a pattern electroplating process to plate a copper layer in step S2. The copper layer plated by the pattern electroplating process compensates for the height, which can meet the thickness requirements of thick copper circuit patterns while minimizing the thickness of the copper foil layer. This reduces the cost of the copper foil layer and also reduces the copper consumption caused by removing non-circuit pattern areas of the copper foil layer, thereby saving copper resources. Attached Figure Description
[0025] Figure 1 This is a schematic diagram of an existing method for manufacturing multilayer PCB substrates.
[0026] Figure 2 This is a schematic diagram of step S1 in the multilayer PCB substrate of the present invention;
[0027] Figure 3 This is a schematic diagram of step S2 in the multilayer PCB substrate of the present invention;
[0028] Figure 4 This is a schematic diagram showing the stacking of the board unit, the external copper layer, the first insulating adhesive layer, and the third insulating adhesive layer in step S3 of the present invention.
[0029] Among them, 10 is the board layer unit; 11 is the second insulating adhesive layer; 20 is the first insulating adhesive layer; 32 is the external copper layer; 40 is the core board; 41 is the core board copper layer; 42 is the core board circuit pattern; 43 is the core board dielectric layer; 50 is the copper foil layer; 51 is the thick copper circuit pattern; and 61 is the third insulating adhesive layer. Detailed Implementation
[0030] The present invention will now be further described in conjunction with the accompanying drawings and specific embodiments. It should be noted that, without conflict, the various embodiments or technical features described below can be arbitrarily combined to form new embodiments.
[0031] like Figure 2-4 As shown, a method for manufacturing a multilayer PCB substrate includes the following steps:
[0032] Step S1: Fabricate the forming plate layer unit 10;
[0033] Step S2: A thick copper circuit pattern 51 is formed in the board layer unit 10 by a circuit pattern thickening method; the thickness of the thick copper circuit pattern 51 is ≥3OZ;
[0034] Step S3: N board layer units 10 arranged from bottom to top and forming a thick copper circuit pattern 51 are bonded together in an insulated manner, and the top and bottom board layer units 10 are bonded to the external copper layer 32 through the first insulating adhesive layer 20 to form a multilayer PCB substrate; wherein, N≥2.
[0035] Wherein, step S1 includes sub-step S11 and sub-step S12:
[0036] Sub-step S11: Prepare the core board 40 and process each core board copper layer 41 of the core board 40 to obtain the core board circuit pattern 42; wherein, the core board 40 includes two core board copper layers 41 and a core board dielectric layer 43 disposed between the two core board copper layers 41.
[0037] Sub-step S12: A copper foil layer 50 is bonded to a core board 40 with a core board circuit pattern 42 through a second insulating adhesive layer 11 to form a board layer unit 10; wherein, the thickness of the board layer unit 10 is ≥0.3mm;
[0038] The method for thickening the circuit pattern adopts the following steps: removing the non-circuit pattern area of the copper foil layer 50 of the board unit 10, and applying a copper layer to the area of the copper foil layer 50 corresponding to the circuit pattern using a pattern electroplating process to form a thick copper circuit pattern 51.
[0039] This invention provides a method for manufacturing a multilayer PCB substrate. By combining steps S1-S3, and by incorporating sub-steps S11 and S12 into step S1, the core board circuit pattern 42 is obtained through sub-step S11, and the board layer unit 10 with a thickness ≥0.3mm is formed through sub-step S12. This allows the pattern electroplating process in step S2 to be implemented. This avoids the problem of scrapping due to exceeding the board thickness limit of the equipment when directly applying the pattern electroplating process on the copper foil layer 50. The copper layer plated by the pattern electroplating process compensates for the height, and can reduce the thickness of the copper foil layer 50 to a large extent while meeting the thickness requirements of the thick copper circuit pattern 51. This reduces the cost of the copper foil layer and also reduces the copper consumption caused by removing non-circuit pattern areas of the copper foil layer 50, thereby saving copper resources.
[0040] In sub-step S12, copper foil layers 50 are bonded to both the upper and lower ends of the core board 40 with the core board circuit pattern 42 through the second insulating adhesive layer 11. This allows for a further reduction in the thickness of the copper foil layer 50 while ensuring the thickness of the assembled board unit 10 is ≥0.3mm. Specifically, in step S2, the copper foil layers 50 at both the upper and lower ends of the core board 40 are processed using a circuit pattern thickening method to form a thick copper circuit pattern 51.
[0041] In step S3, any two adjacent board layer units 10 are bonded together by the third insulating adhesive layer 61, so that N board layer units 10 arranged sequentially from bottom to top are bonded together in a mutually insulating manner. Preferably, in step S3, N board layer units 10, N-1 third insulating adhesive layers 61, two first insulating adhesive layers 20, and two external copper layers 32 are stacked together and pressed together so that the N board layer units 10 arranged sequentially from bottom to top and forming a thick copper circuit pattern 51 are bonded together in a mutually insulating manner, and the top and bottom board layer units 10 are bonded to the external copper layers 32 by the first insulating adhesive layer 20 to form a multilayer PCB substrate, thereby facilitating the formation of a multilayer PCB substrate through stacking and pressing. The N board layer units 10, N-1 third insulating adhesive layers 61, two first insulating adhesive layers 20, and two external copper layers 32 described above are stacked together in a corresponding order. That is, the stacking order of the N board layer units 10, N-1 third insulating adhesive layers 61, two first insulating adhesive layers 20, and two external copper layers 32 after lamination can satisfy the following: "The N board layer units 10 arranged from bottom to top and forming a thick copper circuit pattern 51 are bonded together in a mutually insulating manner, and the top and bottom board layer units 10 are bonded to the external copper layers 32 through the first insulating adhesive layers 20, and any two adjacent board layer units 10 are bonded to each other through the third insulating adhesive layers 61."
[0042] In step S3 of this embodiment, three board layer units 10, two third insulating adhesive layers 61, two first insulating adhesive layers 20, and two external copper layers 32 are stacked together and pressed to form a multilayer PCB substrate. Of course, the number of board layer units 10 can be set to other values according to actual needs, as long as it is greater than or equal to two.
[0043] The first insulating adhesive layer 20, the second insulating adhesive layer 11, and the third insulating adhesive layer 61 are all prepreg units. By using prepreg units for the first insulating adhesive layer, the third insulating adhesive layer 61, and the second insulating adhesive layer 11, the objects being bonded can be insulated from each other and bonded together during pressing, while also reducing costs.
[0044] In this embodiment, the prepreg unit includes two prepregs. Of course, the number of prepregs in the prepreg unit can be set according to actual needs, but using two prepregs in the prepreg unit is the optimal implementation of the present invention, which can meet the corresponding thickness requirements and ensure adhesion.
[0045] The thickness of the copper layer 41 on the core board is 0.5OZ-1OZ, thereby reducing the cost of the copper layer by reasonably setting the thickness of the copper layer 41. As the most preferred embodiment of the present invention, the thickness of the copper layer 41 on the core board is 0.5OZ or 1OZ, which can reduce the cost of the copper layer and is more universal and applicable.
[0046] The thickness of the dielectric layer 43 of the core board is ≥0.05mm.
[0047] In the circuit pattern thickening method, the non-circuit pattern area of the copper foil layer 50 of the board unit 10 is removed by etching process, which facilitates the removal of non-circuit patterns.
[0048] The total thickness h of the copper foil layer 50 corresponding to the circuit pattern area and the copper layer plated by the pattern electroplating process is 3.5-4 OZ. Of course, in addition to this, the total thickness h of the copper foil layer 50 corresponding to the circuit pattern area and the copper layer plated by the pattern electroplating process can be set to other values according to actual needs, as long as it is greater than or equal to 3 OZ. However, setting the total thickness h of the copper foil layer 50 corresponding to the circuit pattern area and the copper layer plated by the pattern electroplating process to 3.5-4 OZ is the optimal embodiment of the present invention, which can improve the current carrying capacity while effectively controlling the cost.
[0049] The thickness of the copper foil layer 50 is 0.5OZ-1OZ. By reasonably setting the thickness of the copper foil layer 50, it can be easily matched with the copper layer plated by the pattern electroplating process to meet the thickness requirements of the thick copper circuit pattern 51, while also reducing the cost of the copper foil layer. As the most preferred embodiment of the present invention, the thickness of the copper foil layer 50 is 0.5OZ or 1OZ, which can reduce the cost of the copper foil layer and is more universal and versatile.
[0050] In sub-step S11, after the core board 40 is prepared, the non-circuit pattern area of the core board copper layer 41 of the core board 40 is removed by etching process, and the remaining circuit pattern area of the core board copper layer 41 is formed into the core board circuit pattern 42. By adopting the above steps, the fabrication and formation of the core board circuit pattern 42 can be facilitated.
[0051] The above embodiments are merely preferred embodiments of the present invention and should not be construed as limiting the scope of protection of the present invention. Any non-substantial changes and substitutions made by those skilled in the art based on the present invention shall fall within the scope of protection claimed by the present invention.
Claims
1. A method for manufacturing a multilayer PCB substrate, characterized in that: Includes the following steps: Step S1: Fabricate the forming plate layer unit; Step S2: A thick copper circuit pattern with a thickness of ≥3OZ is formed in the board layer unit by using a circuit pattern thickening method; Step S3: N board layer units arranged from bottom to top and forming a thick copper circuit pattern are bonded together in an insulated manner, and the top and bottom board layer units are bonded to the external copper layer through the first insulating adhesive layer to form a multilayer PCB substrate; wherein, N≥2; Step S1 includes sub-step S11 and sub-step S12: Sub-step S11: Prepare the core board and process the copper layers of each core board to obtain the core board circuit pattern; wherein, the core board includes two core board copper layers and a core board dielectric layer disposed between the two core board copper layers; Sub-step S12: Adhere the copper foil layer to the core board with the core board circuit pattern through the second insulating adhesive layer to form a board layer unit; wherein, the thickness of the board layer unit is ≥0.3mm; The method for thickening the circuit pattern adopts the following steps: removing the non-circuit pattern area of the copper foil layer of the board unit, and plating a copper layer in the area of the copper foil layer corresponding to the circuit pattern using a pattern electroplating process to form a thick copper circuit pattern. The thickness of the dielectric layer in the core board is ≥0.05mm.
2. The method for manufacturing a multilayer PCB substrate as described in claim 1, characterized in that: In sub-step S12, copper foil layers are bonded to both the upper and lower ends of the core board with the core board circuit pattern through a second insulating adhesive layer.
3. The method for manufacturing a multilayer PCB substrate as described in claim 2, characterized in that: In step S2, the copper foil layers at both ends of the core board are processed to form thick copper circuit patterns by a circuit pattern thickening method.
4. The method for manufacturing a multilayer PCB substrate as described in claim 1, characterized in that: In step S3, any two adjacent plate units are bonded together by a third insulating adhesive layer.
5. The method for manufacturing a multilayer PCB substrate as described in claim 4, characterized in that: In step S3, N board layer units, N-1 third insulating adhesive layers, two first insulating adhesive layers, and two external copper layers are stacked together and pressed together so that the N board layer units arranged from bottom to top and forming thick copper circuit patterns are bonded together in an insulated manner. The top and bottom board layer units are bonded to the external copper layers through the first insulating adhesive layers to form a multilayer PCB substrate.
6. The method for manufacturing a multilayer PCB substrate as described in claim 1, characterized in that: The first insulating adhesive layer, the second insulating adhesive layer, and the third insulating adhesive layer are all semi-cured sheet units.
7. The method for manufacturing a multilayer PCB substrate as described in claim 1, characterized in that: The thickness of the copper layer in the core board is 0.5OZ-1OZ.
8. The method for manufacturing a multilayer PCB substrate as described in claim 1, characterized in that: In the circuit pattern thickening method, the non-circuit pattern area of the copper foil layer of the board unit is removed by etching process; the total thickness of the copper foil layer corresponding to the circuit pattern area and the copper layer plated by pattern electroplating process is 3.5-4OZ.
9. The method for manufacturing a multilayer PCB substrate as described in claim 1 or 8, characterized in that: The thickness of the copper foil layer is 0.5OZ-1OZ.
10. The method for manufacturing a multilayer PCB substrate as described in claim 1, characterized in that: In sub-step S11, after the core board is prepared, the non-circuit pattern area of the core board copper layer is removed by etching process, and the remaining circuit pattern area of the core board copper layer is formed as the core board circuit pattern.