A semiconductor device and a manufacturing method thereof
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD
- Filing Date
- 2021-09-02
- Publication Date
- 2026-06-05
Smart Images
Figure CN115768107B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its manufacturing method. Background Technology
[0002] As semiconductor devices become increasingly miniaturized and the capacitance of capacitors within them increases, the aspect ratio of the lower electrode within the capacitor becomes larger. To prevent the lower electrode from collapsing or breaking before the dielectric layer is formed, a support structure is formed around its outer periphery. This support structure supports the lower electrode, making the capacitor structure more stable.
[0003] However, existing methods for forming the aforementioned support structure result in poor performance of the manufactured capacitors. Summary of the Invention
[0004] The purpose of this invention is to provide a semiconductor device and a method for manufacturing the same, so that the impedance of the lower electrode included in the capacitor meets the requirements of a preset scheme, thereby improving the working performance of the capacitor.
[0005] To achieve the above objectives, the present invention provides a semiconductor device comprising:
[0006] Base;
[0007] Capacitors are formed on a substrate;
[0008] The support structure surrounds the outer periphery of the lower electrode included in the capacitor, and an etched pattern is formed on the support structure; the top contour of the part of the lower electrode corresponding to the etched pattern is an arc-shaped contour.
[0009] Compared to existing technologies, the semiconductor device provided by this invention includes a capacitor formed on a substrate. Furthermore, a support structure surrounds the lower electrode included in the capacitor. This support structure provides support to the lower electrode, preventing collapse or breakage of the lower electrode before the dielectric layer of the capacitor is formed, especially when the lower electrode has a large aspect ratio. This improves the structural stability of the capacitor and facilitates increasing the height of the lower electrode and the capacitance of the capacitor. In addition, an etched pattern is formed on the support structure. Simultaneously, the top contour of the portion of the lower electrode corresponding to the etched pattern is an arc-shaped contour. In other words, during the capacitor manufacturing process, after etching patterns on the support structure and obtaining the lower electrode, the top cross-sectional area of the portion of the lower electrode corresponding to the etching pattern gradually decreases with increasing height, and the rate of decrease gradually slows down. That is, the shape of the top contour is relatively smooth, which is beneficial for the subsequent formation of the dielectric layer included in the capacitor on the surface of each part of the lower electrode. This can improve the leakage phenomenon between the lower electrode and the upper electrode included in the capacitor, which is easily caused by the difficulty in forming the dielectric layer on the relatively sharp triangular top contour of the lower electrode in the prior art. This increases the leakage resistance of the capacitor and improves the working performance of the capacitor.
[0010] The present invention also provides a method for manufacturing a semiconductor device, the method comprising:
[0011] Provide a base;
[0012] A capacitor and a support structure are formed on a substrate; the support structure surrounds the outer periphery of the lower electrode included in the capacitor, and an etched pattern is formed on the support structure; the top contour of the portion of the lower electrode corresponding to the etched pattern is an arc-shaped contour.
[0013] Compared with the prior art, the beneficial effects of the semiconductor device manufacturing method provided by the present invention are the same as those of the semiconductor device provided by the above-described technical solutions, and will not be repeated here. Attached Figure Description
[0014] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:
[0015] Figure 1 This is a schematic diagram of the structure after the lower electrode is formed in the prior art;
[0016] Figure 2 for Figure 1 Enlarged view of part of the structure;
[0017] Figure 3This is a schematic diagram of the structure after forming the first stack, the second stack, and the first mask pattern in an embodiment of the present invention;
[0018] Figure 4 This is a schematic diagram of the structure after the patterned hole structure is formed in an embodiment of the present invention;
[0019] Figure 5 This is a schematic diagram of the structure after the conductive material layer is formed in an embodiment of the present invention;
[0020] Figure 6 This is a schematic diagram of the structure after forming the second mask layer, anti-reflection layer, and photolithography pattern in an embodiment of the present invention;
[0021] Figure 7 This is a schematic diagram of the structure after the first support structure is formed in an embodiment of the present invention;
[0022] Figure 8 This is a schematic diagram of the structure after the lower electrode is formed in an embodiment of the present invention;
[0023] Figure 9 for Figure 8 Enlarged view of part of the structure;
[0024] Figure 10 This is a schematic diagram of the structure after removing the first molding layer in an embodiment of the present invention;
[0025] Figure 11 This is a schematic diagram of the structure after the second support structure is formed in an embodiment of the present invention;
[0026] Figure 12 This is a schematic diagram of the structure after removing the second molding layer in an embodiment of the present invention.
[0027] Reference numerals: 1 is the substrate, 2 is the first stacked layer, 21 is the first molding layer, 22 is the first support layer, 221 is the first support structure, 3 is the second stacked layer, 31 is the second molding layer, 32 is the second support layer, 321 is the second support structure, 4 is the first mask pattern, 5 is the patterned hole structure, 6 is the conductive material layer, 7 is the second mask layer, 71 is the second mask pattern, 8 is the anti-reflection layer, 9 is the photolithography pattern, 10 is the capacitor, 101 is the lower electrode, 11 is the support structure, and 111 is the etching pattern. Detailed Implementation
[0028] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.
[0029] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.
[0030] In the context of this disclosure, when a layer / element is referred to as being "on top of" another layer / element, the layer / element may be directly on top of the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "on top of" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
[0031] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.
[0032] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.
[0033] As semiconductor devices become increasingly miniaturized and the capacitance of capacitors within them increases, the aspect ratio of the lower electrode within the capacitor becomes larger. To prevent the lower electrode from collapsing or breaking before the dielectric layer is formed, a support structure is formed around its periphery. This support structure supports the lower electrode, making the capacitor structure more stable. Based on this, in existing semiconductor device manufacturing, a stack consisting of a molding layer and a support layer is sequentially formed on a substrate. After forming the lower electrode that penetrates the stack, the portion of the lower electrode located within the molding layer is released to prepare for the formation of the dielectric layer within the capacitor.
[0034] Understandably, all other things being equal, the more layers formed on the substrate, the more support structures will be formed subsequently around the lower electrode. Correspondingly, the lower electrode structure will be more stable. The following is a simplified explanation of the process of forming a capacitor on a substrate, using a two-layer stack as an example: A first and a second stack are formed on the substrate along its thickness direction. The first stack is located on top of the second stack. Next, electrode holes are formed penetrating both the first and second stacks, and a conductive material layer is formed covering the inner wall of the electrode holes. Then, under the masking effect of a mask pattern, inductively coupled plasma etching is used to etch a portion of the support layer and a portion of the conductive material layer included in the first stack, so that the remaining portion of the support layer in the first stack forms the first support structure, and the remaining portion of the conductive material layer forms the lower electrode. The molding layer included in the first stack is removed, and under the masking effect of the mask pattern, a portion of the support layer included in the second stack is etched, so that the remaining portion of the support layer in the second stack forms the second support structure. In this process, etched patterns are formed on both the first and second support structures. Finally, the molding layer included in the second stack is removed, and a dielectric layer is formed on the outer periphery of the lower electrode, the first support structure, and the second support structure, and an upper electrode is formed on the dielectric layer, thereby realizing the formation of a capacitor on the substrate.
[0035] However, in the prior art, the material of the aforementioned mask pattern is usually carbon (e.g., amorphous carbon). The material of the lower electrode is usually a metal nitride. Based on this, under the masking effect of the carbon material mask pattern, during the etching of a portion of the first stack including the support layer and a portion of the conductive material layer using inductively coupled plasma etching, the density of F ions in the etching chamber is relatively high. At this time, the etching selectivity of the mask pattern and the lower electrode is relatively low. In this situation, to ensure that the portion of the lower electrode covered by the aforementioned mask pattern (which meets the preset requirements) is not affected by etching while etching the support layer and a portion of the conductive material layer included in the first stack, it is impossible to sufficiently over-etch the portion of the conductive material layer that is not in contact with the first support structure. This results in the top morphology of the portion of the lower electrode that is not in contact with the first support structure being as follows: Figure 1 and Figure 2 As shown, the top cross-sectional area of the portion of the lower electrode 101 that is not in contact with the first support structure 221 gradually decreases with increasing height, and its top profile is triangular. Since the dielectric layer included in the capacitor is difficult to form on the triangular portion of the lower electrode 101, leakage can easily occur between the lower electrode 101 and the upper electrode. Consequently, the impedance of the lower electrode 101 cannot meet the requirements of the preset scheme, resulting in poor performance of the capacitor 10.
[0036] Furthermore, as the aspect ratio of the lower electrode gradually increases, the aspect ratio of the aforementioned electrode holes also gradually increases. After the second support structure is formed in the support layer included in the etched portion of the second stack, etching byproducts remain on the sidewalls of the lower electrode and the etched pattern. The presence of these byproducts reduces the opening size of the etched pattern, thereby affecting the efficiency of subsequent removal of the molding layer included in the second stack. Moreover, the subsequently formed dielectric layer covers these byproducts, causing the morphology and specifications of the dielectric layer and the upper electrode to fail to meet the requirements of the preset scheme, thus reducing the yield of the capacitor.
[0037] To address the aforementioned technical problems, embodiments of the present invention provide a semiconductor device and a method for manufacturing the same. In the semiconductor device provided by this embodiment, a support structure surrounds the lower electrode of the capacitor, and an etched pattern is formed on the support structure. Furthermore, the top contour of the portion of the lower electrode corresponding to the etched pattern is arc-shaped. Therefore, because the top contour is relatively smooth, leakage current between the lower and upper electrodes of the capacitor can be reduced, increasing the leakage resistance of the capacitor and improving its operating performance.
[0038] like Figure 12As shown, this embodiment of the invention provides a semiconductor device. This semiconductor device can be an electronic device such as DRAM (Dynamic Random Access Memory) or FLASH (Flash Memory).
[0039] like Figure 12 As shown, the semiconductor device includes a substrate 1, a capacitor 10, and a support structure 11. The capacitor 10 is formed on the substrate 1. The support structure 11 surrounds the outer periphery of the lower electrode 101 included in the capacitor 10. An etching pattern 111 is formed on the support structure 11. The top contour of the portion of the lower electrode 101 corresponding to the etching pattern 111 is an arc-shaped contour.
[0040] Specifically, the aforementioned substrate can be a structure comprising a single semiconductor material, such as a monocrystalline silicon substrate or a polycrystalline silicon substrate. Alternatively, the substrate can be a stacked structure that already has some semiconductor components formed on it.
[0041] For example, when the semiconductor device provided in this embodiment of the invention is a DRAM, the substrate may include at least a semiconductor substrate, a transistor, a bit line structure, a memory contact, an insulating portion, a landing plug, and an isolation portion. The transistor is formed on the semiconductor substrate. The bit line structure is formed above the transistor. The memory contact and the insulating portion are formed between adjacent bit line structures. The memory contact contacts the source region (or drain region) of the transistor. The insulating portion isolates two adjacent memory contacts. Simultaneously, each landing plug is formed on its corresponding memory contact. The landing plug is electrically connected to the source region (or drain region) of the transistor through the memory contact. The isolation portion is formed on the bit line structure and the insulating portion. The isolation portion isolates two adjacent landing plugs.
[0042] The aforementioned transistor can be a buried trench transistor or any other transistor that meets the requirements. The aforementioned bit line structure can include a bit line body, a capping layer on the bit line body, and sidewalls on both sides of the bit line body and the capping layer. The aforementioned bit line body can be electrically connected to the drain region (or source region) of the transistor through bit line contacts. The materials contained in the aforementioned components can be selected according to the actual application scenario and are not specifically limited here.
[0043] For the aforementioned capacitor, the number of capacitors formed on the substrate can be one or more. When there are multiple capacitors, the arrangement of the multiple capacitors can be set according to the actual application scenario, as long as it can be applied to the semiconductor device provided in the embodiments of the present invention. Furthermore, the aforementioned capacitor can be a cylindrical capacitor. The shape of the lateral cross-section of the cylindrical capacitor can be circular, square, rectangular, etc. Moreover, in addition to the lower electrode, the capacitor also includes a dielectric layer and an upper electrode. The dielectric layer is formed on the outer periphery of the lower electrode and the supporting structure. The upper electrode is formed on the dielectric layer.
[0044] The capacitor described above comprises conductive materials, such as metal nitrides, for its lower and upper electrodes. These materials can be the same or different. The dielectric layer can be an insulating material, such as silicon oxide or a high-k (dielectric constant) material. The thickness of the dielectric layer can be set according to the specific application scenario and is not specifically limited here. Specifically, the thickness of the dielectric layer determines the distance between the lower and upper electrodes. This distance is inversely proportional to the capacitance; that is, when the distance between the lower and upper electrodes decreases, the capacitance increases, and when the distance increases, the capacitance decreases.
[0045] Furthermore, the top contour of the portion of the lower electrode corresponding to the etched pattern is an arc-shaped contour. This arc-shaped contour can be an elliptical arc contour or a circular arc contour. The curvature of the elliptical arc contour and the circular arc contour can be set according to actual needs. It should be noted that the portion of the lower electrode corresponding to the etched pattern is the part of the lower electrode that is not in contact with the support structure, that is, the part of the lower electrode located above or below the etched pattern.
[0046] As for the aforementioned support structure, the number and thickness of the support structure, as well as the specific position of the support structure around the outer periphery of the lower electrode, can be set according to actual needs, and no specific limitations are made here.
[0047] All other things being equal, the more support structures a semiconductor device includes, the greater the support force the support structures can provide to the lower electrode, and the less likely the lower electrode is to collapse or break. However, the more support structures there are, the smaller the area of the lower electrode exposed outside the support structures, i.e., the smaller the area directly opposite the upper electrode. Since the capacitance of a capacitor is proportional to the area directly opposite the lower and upper electrodes, a decrease in the area directly opposite the lower and upper electrodes will reduce the capacitance of the capacitor. Therefore, the number and thickness of the support structures, as well as the specific position of the support structures around the outer periphery of the lower electrode, can be determined according to the aspect ratio of the lower electrode and the capacitance requirements of the capacitor. For example, as shown... Figure 12 As shown, there can be two support structures 11. These two support structures 11 can include a first support structure 221 and a second support structure 321. The first support structure 221 surrounds the outer periphery of the top of the lower electrode 101. The top height of the first support structure 221 is greater than the maximum height of the arc-shaped profile. The second support structure 321 surrounds the outer periphery of the middle part of the lower electrode 101. Specifically, the thickness of the first support structure 221 and the second support structure 321 can be the same or different. For example: Figure 12As shown, the thickness of the first support structure 221 can be greater than the thickness of the second support structure 321. It should be understood that because the top height of the lower electrode 101 is relatively large, the greater thickness of the second support structure 321 can provide sufficient support for the top of the lower electrode 101, preventing collapse or breakage. Simultaneously, the middle height of the lower electrode 101 is relatively small, so the first support structure 221 does not need to provide significant support for the middle of the lower electrode 101, and the middle of the lower electrode 101 will not collapse or break. Furthermore, the smaller thickness of the first support structure 221 allows for a larger area of the lower electrode 101 exposed outside the support structure 11, thereby increasing the capacitance of the capacitor 10.
[0048] Furthermore, the aforementioned support structure can be made of insulating materials such as SiON or SiN. The specific location, shape, and specifications of the etched patterns on the support structure can be set according to actual needs and are not specifically limited here. For example... Figures 7 to 12 As shown, the larger the size of the etched pattern 111 on the support structure 11, the more beneficial it is to remove the molding layer below the support structure 11. However, the larger the size of the etched pattern 111, the smaller the contact area between the support structure 11 and the lower electrode 101, and the smaller the support force that can be provided to the lower electrode 101. Therefore, it can be set according to the aspect ratio of the lower electrode 101 and the distance between adjacent lower electrodes 101.
[0049] As described above, in the semiconductor device provided by this invention, an etched pattern is formed on the support structure. Simultaneously, the top contour of the portion of the lower electrode corresponding to the etched pattern is an arc-shaped contour. That is, during the capacitor manufacturing process, after the etched pattern is formed on the support structure and the lower electrode is obtained, the top cross-sectional area of the portion of the lower electrode corresponding to the etched pattern gradually decreases with increasing height, and the rate of decrease gradually slows down. This results in a smoother top contour, which facilitates the subsequent formation of the dielectric layer included in the capacitor on the surface of each portion of the lower electrode. This improves the situation where, in the prior art, the dielectric layer is difficult to form on the relatively sharp triangular top contour of the lower electrode, easily leading to leakage between the lower and upper electrodes of the capacitor. This increases the leakage resistance of the capacitor and improves its operating performance.
[0050] In one example, such as Figure 12 As shown, when there are multiple capacitors 10, the top of the portion of the lower electrode 101 of each capacitor 10 that contacts the support structure 11 is flush with the surface. It should be understood that, as... Figures 7 to 9As shown, in the process of manufacturing the semiconductor device provided in this embodiment of the invention, in order to make the top contour of the portion of the lower electrode 101 corresponding to the etching pattern 111 an arc-shaped contour, it is necessary to perform sufficient over-etching on the top contour. In this case, if the second mask pattern 71 can sufficiently protect the lower electrode 101 located directly below it, the top of the portion of the lower electrode 101 included in the plurality of capacitors 10 that contacts the support structure 11 can be flush, thereby improving the yield of the capacitors 10 and enhancing the working performance of the capacitors 10.
[0051] This invention also provides a method for manufacturing a semiconductor device, which can be used to manufacture electronic devices such as DRAM (Dynamic Random Access Memory) or FLASH (Flash Memory). The following will describe... Figures 3 to 12 The cross-sectional view shown describes the manufacturing process.
[0052] First, a substrate is provided. The specific structure of this substrate can be found in the previous text and will not be repeated here.
[0053] In one example, such as Figure 3 As shown, when the lower electrode 101 included in the capacitor 10 has a large aspect ratio, a second stack 3 can be formed on the substrate 1. This second stack 3 includes a second molding layer 31 and a second support layer 32 located on the second molding layer 31. Next, a first stack 2 is formed on the second stack 3. This first stack 2 includes a first molding layer 21 and a first support layer 22 located on the first molding layer 21.
[0054] For example, physical vapor deposition or chemical vapor deposition processes can be used to sequentially form a second layer and a first layer on the substrate along its thickness direction. The materials contained in the first and second molding layers need to have a certain etching selectivity ratio with the materials contained in the first and second support layers, respectively, to prevent the first and second support layers from being affected by the etchant used to remove the first and second molding layers. For example, the materials contained in the first and second molding layers can be SiO2. The materials contained in the first and second support layers can be SiON. Furthermore, the thicknesses of the first and second layers can be set according to the specifications of the support structure and the lower electrode.
[0055] It should be noted that the second layer formed on the substrate can be a single layer or multiple layers. When the second layer is multi-layered, the multiple second layers lie on the surface of the substrate along the thickness direction. The first layer is formed on the multiple second layers. The thickness of each second layer can be the same or different.
[0056] Furthermore, when the aspect ratio of the lower electrode included in the capacitor is small, and a supporting structure is formed on the periphery of the lower electrode to prevent the lower electrode from collapsing or breaking, the above method can be used to directly form a first layer on the substrate without forming the second layer.
[0057] like Figure 4 As shown, under the masking effect of the first mask pattern 4, the first stack 2 and the second stack 3 are etched to form a pattern hole structure 5 that penetrates the first stack 2 and the second stack 3.
[0058] For example, the material of the first mask pattern can be photoresist. Based on this, a photoresist layer can be formed on the first stack. Then, the photoresist layer is sequentially exposed and developed to form the first mask pattern. The area covered by this first mask pattern is the area where the lower electrode does not need to be formed subsequently. Under the masking effect of the first mask pattern, processes such as dry etching can be used to sequentially etch the first and second stacks from top to bottom to form a patterned hole structure penetrating the first and second stacks. Specifically, the shape and specifications of the patterned hole structure can be set with reference to the shape and specifications of the lower electrode. Finally, the first mask pattern can be removed by processes such as wet etching to facilitate subsequent operations.
[0059] It should be noted that, as mentioned above, when only one first layer is formed on the substrate, the above method can be used to form the first mask pattern on the first layer. Under the masking effect of the first mask pattern, only the first layer is etched to form a patterned hole structure that penetrates the first layer.
[0060] like Figure 5 As shown, a conductive material layer 6 is formed covering the inner wall of the patterned hole structure 5.
[0061] For example, such as Figure 5 As shown, conductive material can be formed covering the surface of the first stack 2 and the inner wall of the patterned hole structure 5 through processes such as chemical vapor deposition. Then, the conductive material can be etched back to remove the portion of the conductive material on the surface of the first stack 2. The remaining conductive material on the patterned hole structure 5 forms a conductive material layer 6. This conductive material layer 6 is used to form the lower electrode; therefore, the material and thickness of the conductive material layer 6 can be set with reference to the material and thickness of the lower electrode described above. For example, when the lower electrode is made of titanium nitride, the conductive material layer 6 is a titanium nitride layer.
[0062] like Figure 6 and Figure 7 As shown, under the masking effect of the second mask pattern 71, a portion of the first support layer 22 and a portion of the conductive material layer 6 are etched to form an etching pattern 111 on the first support layer 22.
[0063] For example, such as Figure 6 As shown, a second mask layer 7 can be formed first, covering the surface of the first stack 2 and the top of the patterned hole structure 5, using processes such as chemical vapor deposition. The material of the second mask layer 7 can be carbon, such as amorphous carbon. The thickness of the second mask layer 7 can be set according to actual needs and is not specifically limited here. Next, an anti-reflective layer 8 is formed on the second mask layer 7. This anti-reflective layer 8 can be a silicon-containing anti-reflective layer, a bottom anti-reflective layer, or a stack composed of silicon oxynitride and a bottom anti-reflective layer, etc. Then, under the masking effect of the photolithography pattern 9, the anti-reflective layer 8 and the second mask layer 7 are etched sequentially from top to bottom to obtain the second mask pattern 71. The exposed area of the second mask pattern 71 is the area where the subsequent etched pattern 111 is formed; therefore, the shape and specifications of the photolithography pattern 9 and the second mask pattern 71 can be set with reference to the shape and specifications of the etched pattern 111 described above. Finally, an inductively coupled plasma etching process can be used, and under the masking effect of the second mask pattern 71, a portion of the first support layer 22 and a portion of the conductive material layer 6 can be etched to form an etching pattern 111 on the first support layer 22. The amount of conductive material layer 6 etched can be set according to actual needs.
[0064] It is worth noting that the presence of the aforementioned anti-reflection layer can suppress the reflection phenomenon of the second mask layer during exposure of the photoresist layer after its formation, reducing the impact of reflection on the photolithographic pattern and thus improving the accuracy of obtaining the second mask pattern based on the photolithographic pattern, ultimately increasing the yield of semiconductor devices. Of course, if the reflection phenomenon of the second mask layer is insufficient to affect the accuracy of the photolithographic pattern, the anti-reflection layer can be omitted after forming the second mask layer on the substrate, and the photolithographic pattern can be formed directly on the second mask layer.
[0065] It should be noted that, as mentioned above, when only one first layer is formed on the substrate, after etching the first support layer, the remaining first support layer forms a support structure. This support structure surrounds the outer periphery of the lower electrode. However, when a second layer and a first layer are formed sequentially on the substrate, after etching the first support layer, the remaining first support layer forms a first support structure. This first support structure surrounds the top outer periphery of the lower electrode.
[0066] like Figure 8 and Figure 9 As shown, the etched conductive material layer 6 undergoes a post-etching process to make the top contour of the portion of the conductive material layer 6 corresponding to the etched pattern 111 an arc-shaped contour, thus obtaining the lower electrode 101. It should be understood that the top contour of the portion of the lower electrode 101 corresponding to the etched pattern 111 is an arc-shaped contour.
[0067] For example, when the material of the second mask pattern is carbon and the material of the lower electrode is metal nitride, capacitively coupled plasma etching (CAPE) can be used to perform post-etching treatment on the etched conductive material layer. The etching gas used can be a mixture of O2, Ar, and CF4. The specific etching conditions of the CAPE process can be set according to the actual application scenario, as long as they can be applied to the semiconductor device manufacturing method provided in this embodiment of the invention. For example, the etching conditions of the CAPE process can be: pressure of 150 mTorr to 200 mTorr, O2 gas volume flow rate of 80 sccm to 120 sccm, Ar gas volume flow rate of 300 sccm to 400 sccm, CF4 gas volume flow rate of 8 sccm to 12 sccm, and the RF frequency of the power supply of 2 MHz, 27 MHz, or 60 MHz.
[0068] It is worth noting that when the second mask pattern is made of carbon and the lower electrode is made of metal nitride, the F ion density in the etching chamber is high during the etching of part of the lower electrode using inductively coupled plasma etching (ICP-E). In this case, the etching selectivity between the second mask pattern and the lower electrode is relatively low. Therefore, to ensure that the second mask pattern can adequately protect the lower electrode directly below it from etching, sufficient over-etching (over-etching rate of approximately 50%) is not possible on the lower electrode, resulting in the top contour of the portion of the lower electrode corresponding to the etched pattern appearing as... Figure 2 As shown, during the etching of part of the lower electrode using capacitively coupled plasma etching (CAPE), the density of F ions in the etching chamber is relatively low. At this time, the etching selectivity between the second mask pattern and the lower electrode is relatively large. Therefore, post-etching treatment of the etched conductive material layer using CAPE can achieve an over-etching rate of 80% to 120%, thereby obtaining a smoother top profile, improving leakage current between the lower and upper electrodes, increasing the leakage resistance of the capacitor, and improving the capacitor's operating performance.
[0069] In one example, as described above, where a second stack and a first stack are sequentially formed on a substrate, forming a support structure on the substrate after obtaining the lower electrode further includes:
[0070] like Figure 10 As shown, the first molding layer 21 is removed to release the portion of the lower electrode 101 located within the first molding layer 21.
[0071] For example, the first molding layer can be removed by using an etching pattern on the first support structure and a wet etching process to release the portion of the lower electrode located within the first molding layer.
[0072] like Figure 11 As shown, under the masking effect of the second mask pattern 71, a portion of the second support layer 32 is etched to form an etching pattern 111 on the second support layer 32, and the remaining second support layer 32 forms a second support structure 321. The first support structure 221 and the second support structure 321 constitute the support structure 11.
[0073] For example, a dry etching process can be used, and under the masking effect of the second mask pattern, a portion of the second support layer can be etched to obtain the second support structure.
[0074] In one example, as mentioned above, when the lower electrode has a large aspect ratio, after forming a support structure on the substrate, forming a capacitor on the substrate further includes: Figure 11 As shown, after removing the etched pattern 111 formed on the second support layer 32, the byproducts remaining on the lower electrode 101 and the sidewalls of the etched pattern 111 are removed.
[0075] In practical applications, during the dry etching process of the second support layer, the reactants of the etching gas and the second support layer are discharged through the etching pattern on the first support structure. However, with the miniaturization of semiconductor devices and the increasing capacitance of capacitors, the aspect ratio of the lower electrode is also increasing. This results in a larger gap between the first and second support layers and a smaller gap between adjacent lower electrodes. Consequently, after etching the second support layer, some reactants cannot be discharged in time, forming byproducts remaining on the sidewalls of the lower electrode and the etching pattern. Removing these byproducts after forming the second support structure facilitates the contact and reaction of the etchant with the second molding layer through the larger opening of the etching pattern, improving the removal efficiency of the second molding layer. Simultaneously, after removing these byproducts, the dielectric layer and the upper electrode can be formed in the corresponding positions according to a predetermined scheme, ensuring that the morphology and specifications of the dielectric layer and the upper electrode meet the requirements of the predetermined scheme, thereby improving the yield of the capacitor.
[0076] For example, when the aforementioned byproducts include carbon-containing byproducts, a mixture of O2 and Ar gas can be used to remove the byproducts at a pressure of 150 mTorr to 200 mTorr. Specifically, the gas flow rates of O2 and Ar can be set according to the actual application scenario. For example, the volumetric flow rate of O2 gas can be 230 sccm to 270 sccm, and the volumetric flow rate of Ar gas can be 280 sccm to 320 sccm. It should be understood that under high pressure conditions (e.g., 150 mTorr to 200 mTorr), carbon-containing byproducts will react with O2 and be discharged through the etched pattern. Furthermore, plasma is easily formed under high pressure, and because Ar is chemically stable, introducing Ar gas into the etching chamber can provide a stable chamber atmosphere and improve the stability of the reaction.
[0077] It should be noted that, as mentioned above, when multiple second layers are formed on the substrate, after the etching pattern is formed on the second support layer and before the second molding layer adjacent to the second support layer is removed, the above method can be used to remove the byproducts remaining on the lower electrode and the sidewalls of the etching pattern.
[0078] like Figure 12 As shown, the second molding layer 31 is removed to release the portion of the lower electrode 101 located within the second molding layer 31. For example, a wet etching process can be used to remove the second molding layer 31.
[0079] Next, a dielectric layer is formed on the outer periphery of the lower electrode and the support structure. Then, an upper electrode is formed on the dielectric layer.
[0080] For example, the dielectric layer and the upper electrode can be formed sequentially using processes such as physical vapor deposition or chemical vapor deposition. The materials contained in the dielectric layer and the upper electrode, as well as the thickness of the dielectric layer, can be referred to the preceding text.
[0081] It should be noted that, as mentioned above, when only one first layer is formed on the substrate, a dielectric layer can be formed on the outer periphery of the lower electrode and the support structure after the first molding layer is removed. The upper electrode is then formed on the dielectric layer.
[0082] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.
[0083] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.
Claims
1. A semiconductor device, characterized in that, include: Base; A capacitor is formed on the substrate; A support structure surrounds the outer periphery of the lower electrode included in the capacitor, and an etched pattern is formed on the support structure; the top contour of the portion of the lower electrode corresponding to the etched pattern is an arc-shaped contour. The portion of the lower electrode corresponding to the etching pattern is the portion of the lower electrode that is not in contact with the support structure.
2. The semiconductor device according to claim 1, characterized in that, The number of capacitors is multiple, and the top of the portion of the lower electrode of each capacitor that contacts the support structure is flush with the top; and / or, The arc-shaped profile is a circular arc profile; And / or, The capacitor further includes a dielectric layer and an upper electrode; the dielectric layer is formed on the outer periphery of the lower electrode and the support structure; the upper electrode is formed on the dielectric layer.
3. The semiconductor device according to claim 1, characterized in that, The number of support structures is two, including a first support structure and a second support structure; the first support structure surrounds the outer periphery of the top of the lower electrode, and the top height of the first support structure is greater than the maximum height of the arc-shaped profile; the second support structure surrounds the outer periphery of the middle part of the lower electrode.
4. A method for manufacturing a semiconductor device, characterized in that, include: Provide a base; A capacitor and a support structure are formed on the substrate; The support structure surrounds the outer periphery of the lower electrode included in the capacitor, and an etching pattern is formed on the support structure; the top contour of the portion of the lower electrode corresponding to the etching pattern is an arc-shaped contour; the portion of the lower electrode corresponding to the etching pattern is the portion of the lower electrode that does not contact the support structure. Wherein, after providing a substrate and before forming a capacitor and a support structure on the substrate, the method for manufacturing the semiconductor device further includes: forming a first stack on the substrate; the first stack includes a first molding layer and a first support layer located on the first molding layer; under the masking action of a first mask pattern, etching the first stack to form a patterned hole structure penetrating the first stack; forming a conductive material layer covering the inner wall of the patterned hole structure; Forming the capacitor on the substrate includes: etching a portion of the first support layer and a portion of the conductive material layer under the masking effect of a second mask pattern to create the etching pattern on the first support layer; the second mask pattern is made of carbon material; the lower electrode is made of metal nitride; and performing post-etching processing on the etched conductive material layer using capacitively coupled plasma etching to make the top contour of the portion of the conductive material layer corresponding to the etching pattern an arc-shaped contour, thereby obtaining the lower electrode.
5. The method for manufacturing a semiconductor device according to claim 4, characterized in that, The etching conditions for capacitively coupled plasma etching are: pressure of 150 mTorr~200 mTorr, O2 gas volumetric flow rate of 80 sccm~120 sccm, Ar gas volumetric flow rate of 300 sccm~400 sccm, CF4 gas volumetric flow rate of 8 sccm~12 sccm, and the RF frequency of the power supply of 2 MHz, 27 MHz or 60 MHz.
6. The method for manufacturing a semiconductor device according to claim 4, characterized in that, After post-etching treatment of the etched conductive material layer, the over-etching rate of the conductive material layer is 80% to 120%.
7. The method for manufacturing a semiconductor device according to claim 4, characterized in that, After providing a substrate and before forming a conductive material layer covering the inner wall of the patterned hole structure, the method for manufacturing the semiconductor device includes: A second stack is formed on the substrate; the second stack includes a second molding layer and a second support layer located on the second molding layer; The first stack is formed on the second stack; Under the masking effect of the first mask pattern, the first stack and the second stack are etched to form the pattern hole structure that penetrates the first stack and the second stack; Forming the support structure on the substrate includes: After the etching pattern is formed on the first support layer, the remaining first support layer forms the first support structure; Remove the first molding layer to release the portion of the lower electrode located within the first molding layer; Under the masking effect of the second mask pattern, a portion of the second support layer is etched to open the etching pattern on the second support layer, and the remaining second support layer forms a second support structure; the first support structure and the second support structure constitute the support structure.
8. The method for manufacturing a semiconductor device according to claim 7, characterized in that, After forming the support structure on the substrate, forming the capacitor on the substrate further includes: Remove the byproducts remaining on the lower electrode and the sidewalls of the etched pattern after the etching pattern is formed on the second support layer; Remove the second molding layer to release the portion of the lower electrode located within the second molding layer; A dielectric layer is formed on the outer periphery of the lower electrode and the support structure; An upper electrode is formed on the dielectric layer.
9. The method for manufacturing a semiconductor device according to claim 8, characterized in that, The byproducts include carbon-containing byproducts; The byproducts were removed using a mixed gas of O2 and Ar at a pressure of 150 mTorr to 200 mTorr. in, The volumetric flow rate of O2 gas is 230 sccm~270 sccm, and the volumetric flow rate of Ar gas is 280 sccm~320 sccm.