Display substrate, manufacturing method thereof and display device

Abstract

Embodiments of the present disclosure provide a display substrate and a manufacturing method thereof, and a display device, and relate to the technical field of display, and are used for increasing the capacitance of a storage capacitor. The display substrate comprises a plurality of pixel driving circuits, and each pixel driving circuit comprises at least a first transistor and a storage capacitor. The display substrate further comprises a substrate, a first gate conductive layer on the substrate, a second gate conductive layer on the first gate conductive layer, and a first source-drain conductive layer on the second gate conductive layer. The first transistor comprises a first gate pattern on the first gate conductive layer, and the first gate pattern is multiplexed as a first plate of the storage capacitor. The storage capacitor comprises a second plate on the second gate conductive layer, and the first source-drain conductive layer comprises a conductive pattern electrically connected with the second plate. The conductive pattern comprises a sub-portion, and the sub-portion overlaps with the first plate in the orthographic projection onto the substrate. The display substrate, the manufacturing method thereof and the display device are used for displaying images.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a display substrate, a manufacturing method thereof, and a display device. BACKGROUND

[0002] Organic Light Emitting Diode (OLED) display technology is a technology that uses light-emitting materials to emit light under the drive of current to realize display. OLED display has the advantages of ultra-light, ultra-thin, high brightness, large viewing angle, low voltage, low power consumption, fast response, high definition, shock resistance, bendable, low cost, simple process, less use of raw materials, high luminous efficiency, and wide temperature range. SUMMARY

[0003] Embodiments of the present disclosure aim to provide a display substrate, a manufacturing method thereof, and a display device for increasing the capacitance value of a storage capacitor.

[0004] To achieve the above-mentioned purpose, embodiments of the present disclosure provide the following technical solutions:

[0005] In one aspect, a display substrate is provided. The display substrate includes a plurality of pixel driving circuits, and each pixel driving circuit includes at least a first transistor and a storage capacitor. The display substrate further includes a substrate, a first gate conductive layer on the substrate, a second gate conductive layer on the first gate conductive layer, and a first source-drain conductive layer on the second gate conductive layer. The first transistor includes a first gate pattern on the first gate conductive layer, and the first gate pattern is multiplexed as a first plate of the storage capacitor. The storage capacitor includes a second plate on the second gate conductive layer, and in the orthographic projection onto the substrate, the second plate and the first plate partially overlap. The first source-drain conductive layer includes a conductive pattern, and the conductive pattern is electrically connected to the second plate. The conductive pattern includes a sub-portion, and in the orthographic projection onto the substrate, the sub-portion overlaps the first plate.

[0006] In the above display substrate, by providing the conductive pattern electrically connected to the second plate, the area of the second plate of the storage capacitor is increased. In the orthographic projection onto the substrate, by overlapping the sub-portion of the conductive pattern with the first plate, the area between the sub-portion and the first plate is increased in addition to the area between the original first plate and the second plate, thereby increasing the capacitance value of the storage capacitor, and the stability of the data signal stored in the storage capacitor in the pixel driving circuit is enhanced, i.e., the potential on the first gate pattern (gate) in the first transistor T is stabilized.

[0007] In some embodiments, the second gate conductive layer comprises a first connection pattern spaced apart from the second plate, the first connection pattern being electrically connected with the first plate. In the orthogonal projection onto the substrate, the first connection pattern overlaps with the sub-portion.

[0008] In some embodiments, the pixel driving circuit further comprises a second transistor, the second transistor comprising a second gate pattern located at the first gate conductive layer. The orthogonal projection of the second gate pattern onto the substrate is located within the range of the orthogonal projection of the conductive pattern onto the substrate.

[0009] In some embodiments, the display substrate further comprises a second source-drain conductive layer located on the first source-drain conductive layer. The second source-drain conductive layer comprises a data line extending along a first direction, the first direction being parallel to the plane where the substrate is located. The orthogonal projection of the second gate pattern onto the substrate is located within the range of the orthogonal projection of the conductive pattern onto the substrate and within the range of the orthogonal projection of the data line onto the substrate.

[0010] In some embodiments, the pixel driving circuit further comprises a second transistor. The display substrate further comprises a semiconductor layer located between the substrate and the first gate conductive layer. The first transistor comprises a first active pattern located at the semiconductor layer, the first active pattern comprising a first connection portion and a first channel region arranged in sequence along a first direction, the first direction being parallel to the plane where the substrate is located; in the orthogonal projection onto the substrate, the first channel region, the first plate and the second plate partially overlap; the first connection portion is electrically connected with the conductive pattern. The second transistor comprises a second active pattern located at the semiconductor layer, the second active pattern comprising a second connection portion; the second connection portion is electrically connected with the first plate.

[0011] In some embodiments, the number of the conductive patterns is a plurality, the plurality of conductive patterns are arranged in multiple rows and multiple columns, each row of conductive patterns is arranged along a second direction, and each column of conductive patterns is arranged along a third direction; the second direction and the third direction intersect and are both parallel to the plane where the substrate is located. The first source-drain conductive layer further comprises a plurality of first power voltage signal lines extending along the second direction. One first power voltage signal line is electrically connected with a plurality of conductive patterns in the same row.

[0012] In some embodiments, the first power voltage signal line and the plurality of conductive patterns electrically connected with the first power voltage signal line are in an integrated structure.

[0013] In some embodiments, the first connecting portion does not overlap with the second electrode plate in the orthographic projection of the substrate. The first connecting portion is electrically connected with the first power voltage signal line and is electrically connected with the conductive pattern through the first power voltage signal line.

[0014] In some embodiments, the number of the conductive patterns is plural, and the plural conductive patterns are arranged in multiple rows and multiple columns. Each row of the conductive patterns is arranged along a second direction, and each column of the conductive patterns is arranged along a third direction. The second direction and the third direction are intersected and are both parallel to the plane where the substrate is located. The conductive patterns in the same column are electrically connected to form the first power voltage signal line.

[0015] In some embodiments, the conductive patterns in the same column are in an integrated structure.

[0016] In some embodiments, the first connecting portion overlaps with the second electrode plate in the orthographic projection of the substrate. The first connecting portion is electrically connected with the second electrode plate and is electrically connected with the conductive pattern through the second electrode plate.

[0017] In some embodiments, the plural second electrode plates are arranged in multiple rows and multiple columns. Each row of the second electrode plates is arranged along a second direction, and each column of the second electrode plates is arranged along a third direction. The second electrode plates in the same row are electrically connected.

[0018] In some embodiments, the number of the first active patterns is plural, and the plural first active patterns are arranged in multiple rows and multiple columns. Each row of the first active patterns is arranged along a second direction, and each column of the first active patterns is arranged along a third direction. The second direction and the third direction are intersected and are both parallel to the plane where the substrate is located. The first connecting portions of the first active patterns in the same row are connected.

[0019] In some embodiments, the plural pixel driving circuits are arranged in multiple rows and multiple columns. Each row of the pixel driving circuits is arranged along a second direction, and each column of the pixel driving circuits is arranged along a third direction. Any two adjacent rows of the pixel driving circuits are symmetrically arranged.

[0020] In some embodiments, the display substrate further comprises a second source-drain conductive layer on the first source-drain conductive layer. The second source-drain conductive layer comprises a data line extending along a first direction. The second active pattern further comprises a third connecting portion. The third connecting portion is located at two ends of the second active pattern respectively with the second connecting portion. The third connecting portion is electrically connected with the data line. In the 2Nth row of pixel driving circuits and the 2N+1th row of pixel driving circuits, the third connecting portions of the two pixel driving circuits in the same column are in an integrated structure, and N is a positive integer.

[0021] In some embodiments, the first connecting part of the two pixel driving circuits in the same column in the 2Nth row pixel driving circuit and the 2N-1th row pixel driving circuit is in an integrated structure, and N is a positive integer.

[0022] In some embodiments, in the case that the first source-drain conductive layer further comprises a plurality of first power voltage signal lines extending along the second direction, the first power voltage signal line electrically connected to the conductive pattern of the 2Nth row pixel driving circuit and the first power voltage signal line electrically connected to the conductive pattern of the 2N-1th row pixel driving circuit are in an integrated structure, and N is a positive integer.

[0023] In another aspect, a display device is provided. The display device comprises the display substrate according to any one of the above embodiments.

[0024] In yet another aspect, a manufacturing method of a display substrate is provided. The display substrate comprises a plurality of pixel driving circuits, and each pixel driving circuit comprises at least a first transistor and a storage capacitor. The manufacturing method comprises: providing a substrate; forming a first gate conductive layer on the substrate; the first transistor comprises a first gate pattern on the first gate conductive layer, and the first gate pattern is multiplexed as a first plate of the storage capacitor; forming a second gate conductive layer on the first gate conductive layer; the storage capacitor comprises a second plate on the second gate conductive layer; in the orthogonal projection onto the substrate, the second plate and the first plate partially overlap; forming a first source-drain conductive layer on the second gate conductive layer; the first source-drain conductive layer comprises a conductive pattern electrically connected to the second plate. The conductive pattern comprises a sub-portion, and in the orthogonal projection onto the substrate, the sub-portion overlaps with the first plate.

[0025] In some embodiments, the pixel driving circuit further comprises a second transistor. Before the first gate conductive layer is formed, the manufacturing method further comprises: forming a semiconductor layer on the substrate; and forming a first gate insulating film on the semiconductor layer. After the first gate conductive layer is formed and before the second gate conductive layer is formed, the manufacturing method further comprises: forming a second gate insulating film on the first gate conductive layer; forming a first mask pattern on the second gate insulating film; etching the to-be-formed display substrate through the first mask pattern to form a first via hole penetrating through the first gate insulating film and the second gate insulating film and exposing the semiconductor layer, and a second via hole penetrating through the second gate insulating film and exposing the first gate conductive layer; cleaning the to-be-formed display substrate using a cleaning liquid; and removing the first mask pattern.

[0026] The display device and the manufacturing method of the display substrate have the same structure and beneficial technical effects as the display substrate provided in some of the above embodiments, and will not be described here again. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0028] Figure 1 This is a structural diagram of a display device according to some embodiments of the present disclosure;

[0029] Figure 2 This is a structural diagram of a display substrate according to some embodiments of the present disclosure;

[0030] Figure 3 This is a structural diagram of a pixel driving circuit according to some embodiments of the present disclosure;

[0031] Figure 4 This is a structural diagram of a display substrate in one implementation method;

[0032] Figure 5 This is a structural diagram of a display substrate in another implementation method;

[0033] Figure 6A This is a top view of some film layers in a display substrate according to some embodiments of the present disclosure;

[0034] Figure 6B for Figure 6A A cross-sectional view along the AA direction;

[0035] Figures 6C-6O This is a top view of different film layers in a display substrate according to some embodiments of the present disclosure.

[0036] Figure 6P for Figure 6A A cross-sectional view along the BB direction;

[0037] Figure 6Q for Figure 6A A cross-sectional view along the CC direction;

[0038] Figures 7A-7K This is a top view of different film layers in another display substrate according to some embodiments of the present disclosure.

[0039] Figure 8 for Figure 7A A cross-sectional view along the DD direction;

[0040] Figure 9 A top view of some film layers in a display substrate according to some embodiments of the present disclosure;

[0041] Figure 10A A top view of some film layers in a display substrate according to some embodiments of the present disclosure;

[0042] Figure 10B A top view of some film layers in a display substrate according to some embodiments of the present disclosure; Figure 10A A sectional view along EE direction in the display substrate;

[0043] Figure 11 A sectional view along FF direction in the display substrate; Figure 9 A sectional view along FF direction in the display substrate;

[0044] Figure 12 A top view of some film layers in a display substrate according to some embodiments of the present disclosure;

[0045] Figure 13 A top view of some film layers in a display substrate according to some embodiments of the present disclosure;

[0046] Figure 14 A top view of some film layers in a display substrate according to some embodiments of the present disclosure; Figure 9 A sectional view along GG direction in the display substrate;

[0047] Figure 15 A flow chart of a manufacturing method of a display substrate according to some embodiments of the present disclosure;

[0048] Figures 16A-16C A sectional view of a display substrate to be formed in each step of a manufacturing method of a display substrate according to some embodiments of the present disclosure;

[0049] Figure 17 A sectional view of a display substrate formed by a manufacturing method of a display substrate according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0050] The technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are only some of the embodiments of the present disclosure, but not all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by those of ordinary skill in the art are within the scope of protection of the present disclosure.

[0051] Unless otherwise required by context, as used herein the term "comprise" and variations of the term, such as "comprises" and "comprising," will be understood to imply the inclusion of a stated integer or step or group of integers or steps but not the exclusion of any other integer or step or group of integers or steps. In describing some embodiments, the use of "connection" and variations thereof can be used. The term "connection" is to be broadly interpreted, for example, "connection" can be fixed connections, detachable connections, or integral; can be directly connected, or indirectly connected through an intermediate medium. The embodiments disclosed herein are not necessarily limited by the content herein.

[0052] Hereinafter, the terms "first", "second", etc. are used only for the purpose of description and should not be understood as indicating or implying relative importance or implying the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, the meaning of "a plurality of" is two or more, unless otherwise specified.

[0053] In describing some embodiments, the use of "connection" and variations thereof can be used. The term "connection" is to be broadly interpreted, for example, "connection" can be fixed connections, detachable connections, or integral; can be directly connected, or indirectly connected through an intermediate medium. The embodiments disclosed herein are not necessarily limited by the content herein.

[0054] "A and / or B" includes the following three combinations: only A, only B, and a combination of A and B.

[0055] In addition, the use of "based on" means openness and inclusiveness, because the process, step, calculation or other action "based on" one or more stated conditions or values can be based on additional conditions or beyond the stated values in practice.

[0056] It should be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or an intervening layer can also be present between the layer or element and the other layer or substrate.

[0057] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are schematic illustrations of idealized embodiments. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will, typically, have rounded or curved features. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region that would be formed by a given manufacturing technique. The purpose of such illustrations is to more effectively convey specified information from drawing to viewer.

[0058] In the circuit structure (e.g., pixel driving circuit) provided by the embodiments of the present disclosure, the transistor adopted by the circuit structure can be a thin film transistor (TFT), a metal oxide semiconductor (MOS), or other switching devices with the same characteristics, and the embodiments of the present disclosure are described by taking the thin film transistor as an example.

[0059] In the circuit structure provided by the embodiments of the present disclosure, the first pole of the transistor is one of the source and the drain, and the second pole of the transistor is the other of the source and the drain. Since the source and the drain of the transistor can be symmetrical in structure, the source and the drain of the transistor can be indistinguishable in structure, that is, the first pole and the second pole of the transistor in the embodiments of the present disclosure can be indistinguishable in structure. For example, in the case of a P-type transistor, the first pole of the transistor is the source, and the second pole of the transistor is the drain; for example, in the case of an N-type transistor, the first pole of the transistor is the drain, and the second pole of the transistor is the source.

[0060] In the circuit structure provided by the embodiments of the present disclosure, the nodes such as the first node and the second node do not represent actual components, but represent the convergence points of the relevant electrical connections in the circuit diagram, that is, these nodes are equivalent nodes formed by the convergence points of the relevant electrical connections in the circuit diagram.

[0061] The transistors included in the circuit structure provided by the embodiments of the present disclosure can all be N-type transistors, or can all be P-type transistors, or part of them can be N-type transistors and the other part can be P-type transistors. Among them, the P-type transistor can be turned on under the control of a low-level signal, and the N-type transistor can be turned on under the control of a high-level signal.

[0062] The following embodiments take the P-type transistor as an example for description.

[0063] As Figure 1As shown, some embodiments of the present disclosure provide a display substrate 100 and a display device 1000, which are respectively introduced as follows.

[0064] Some embodiments of the present disclosure provide a display device 1000. The display device 1000 can be any display device that displays both motion (e.g., video) and fixed (e.g., still image) and both text and images. More specifically, it is contemplated that the display device of the embodiments can be implemented in or associated with a variety of electronic devices such as, but not limited to, mobile telephones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 players, camcorders, game consoles, wrist watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, auto displays (e.g., odometer display, etc.), cockpit controls and / or displays, camera view displays (e.g., display of a rear view camera in a vehicle), electronic photographs, electronic billboards or signs, projections, architectural structures, packaging, and aesthetic structures (e.g., display of images on a piece of jewelry) and the like.

[0065] In some embodiments, as shown in Figure 1 As shown, the display device 1000 includes the display substrate 100.

[0066] For example, the display device 1000 further includes a frame, a display driving IC (Integrated Circuit), other electronic accessories, and the like.

[0067] For example, the display driving IC can provide a data signal for the display substrate 100, which includes a display data signal and a sensing data signal, and the like, so that the display brightness of the display substrate 100 can be controlled by using the display data signal.

[0068] In some embodiments, as shown in Figure 2 As shown, the display substrate 100 includes a plurality of pixel driving circuits P and a plurality of light emitting devices L.

[0069] For example, the plurality of pixel driving circuits P and the plurality of light emitting devices L can be electrically connected one by one. For another example, in some embodiments of the present disclosure, one pixel driving circuit P can be electrically connected with a plurality of light emitting devices L, or a plurality of pixel driving circuits P can be electrically connected with one light emitting device L.

[0070] Hereinafter, the structure of the display substrate 100 is schematically described by taking an example that one pixel driving circuit P is electrically connected with one light emitting device L.

[0071] Exemplarily, in the display substrate 100, each light emitting device L can emit light under the driving of the corresponding pixel driving circuit P, and the light emitted by the plurality of light emitting devices L cooperates with each other, so that the display substrate 100 realizes the display function.

[0072] For example, the light emitting device L can include an OLED light emitting device, an LED (Light-Emitting Diode) light emitting device, etc.

[0073] In some embodiments of the present disclosure, the light emitting device L is taken as an OLED light emitting device for example. For example, the light emitting device L can include a first electrode, a light emitting functional layer, a second electrode, etc. which are sequentially stacked. The light emitting functional layer can include a light emitting layer. Optionally, the light emitting functional layer can further include at least one of a hole injection layer, a hole transport layer, an electron transport layer and an electron injection layer.

[0074] For example, the first electrode can be one of an anode and a cathode, and the second electrode can be the other one of the anode and the cathode, which is not limited in the present disclosure.

[0075] In the following, some embodiments of the present disclosure are taken as examples in which the first electrode is an anode and the second electrode is a cathode.

[0076] By applying a common voltage to the second electrode of the light emitting device L and applying a driving voltage to the first electrode of the light emitting device L by using the corresponding pixel driving circuit P, an electric field can be formed between the first electrode and the second electrode, which can drive different carriers (i.e. holes and electrons) to recombine in the light emitting layer, so that the light emitting device L emits light.

[0077] Exemplarily, the pixel driving circuit P and the light emitting device L electrically connected thereto form a sub-pixel of the display substrate 100. The greater the density of the sub-pixels in the display substrate 100, i.e. the higher the PPI (Pixel x Per Inch) of the display substrate 100, the clearer the picture displayed by the display substrate 100, and the better the display effect of the display substrate 100.

[0078] It should be noted that the structure of the pixel driving circuit P includes a plurality of structures, which can be selected and arranged according to actual needs. For example, the structure of the pixel driving circuit P can include a “2T1C”, “3T1C”, “4T1C”, “6T1C”, “7T1C”, “6T2C”, “7T2C” or “8T2C” structure. Wherein, “T” represents a transistor, the number before “T” represents the number of transistors, and “C” represents a storage capacitor, and the number before “C” represents the number of storage capacitors.

[0079] In some embodiments of the present disclosure, the structure of the pixel driving circuit P is taken as an example of a "2T1C" structure for illustration.

[0080] As shown in Figure 3 , the pixel driving circuit P includes a first transistor T1, a second transistor T2 and a storage capacitor C.

[0081] The first electrode of the second transistor T2 is connected with a data line (Data in Figure 3 ), the second electrode of the second transistor T2 is connected with the first node N1, and the gate electrode of the second transistor T2 is connected with a gate line (Gate in Figure 3 ). The second transistor T2 is used to transmit the data signal transmitted by the data line to the first node under the control of the gate signal transmitted by the gate line.

[0082] The first electrode of the first transistor T1 is connected with a first power voltage signal line (VDD in Figure 3 ), the second electrode of the first transistor T1 is connected with the second node N2, and the gate electrode of the first transistor T1 is connected with the first node N1. The first transistor T1 is used to transmit the first power voltage signal transmitted by the first power voltage signal line to the second node N2 under the control of the electrical signal of the first node N1, and provide a driving current for the light emitting device L to drive the light emitting device L to emit light. The first transistor T1 can also be referred to as a driving transistor (DTFT). The first electrode of the storage capacitor C is connected with the first node N1, and the second electrode of the storage capacitor C is connected with the first power voltage signal line. The storage capacitor C is used to store the data signal transmitted to the first node.

[0083] The first electrode of the light emitting device L is connected with the second node N2, and the second electrode of the light emitting device L is connected with a second power voltage signal end (VSS in Figure 3 ). The light emitting device L is used to emit light under the action of the first power voltage signal transmitted to the second node N2 and the second power voltage signal provided by the second power voltage signal end.

[0084] Because of the characteristics of the transistor, as shown in Figure 3 , the second transistor T2 also has a certain leakage current in the off state, which will cause the data signal stored on the storage capacitor C to be unstable, and further cause the driving current provided by the first transistor T1 for the light emitting device L to be unstable, so that the light emitting device L emits light unstably. By increasing the capacitance value of the storage capacitor C, the stability of the data signal stored on the storage capacitor C can be enhanced.

[0085] In an implementation manner, as shown in Figure 4As shown, the storage capacitor C' of the pixel driving circuit is formed by a first electrode 1' located in the first gate layer and a second electrode 2' located in the second gate layer. The first electrode 1' also forms the gate of the first transistor. The first power supply voltage signal line 3' and the data line ( Figure 4 (Not shown in the diagram) Both are disposed in the source and drain conductive layers. The second electrode 2' is connected to the first power supply voltage signal line 3', thereby realizing the connection between the first electrode of the storage capacitor C' and the first power supply voltage signal line. The first power supply voltage signal line 3' is also connected to the first active pattern 4' located in the active layer through a via. The first active pattern 4' is used to form the channel region, first electrode, and second electrode of the first transistor, thereby realizing the connection between the first electrode of the first transistor and the first power supply voltage signal line.

[0086] The capacitance of the storage capacitor C' can be increased by increasing the area directly opposite the first plate 1' and the second plate 2'. However, if... Figure 4 As shown, because the first power supply voltage signal line 3' is also connected to the first active pattern 4' located in the active layer through a via, the part of the first power supply voltage signal line 3' used to connect to the first active pattern 4' needs to be staggered from the first electrode 1' and the second electrode 2' on the plane where the display substrate is located. This will result in the first power supply voltage signal line 3', the first electrode 1' and the second electrode 2' occupying a large area on the plane where the display substrate is located, thus making the space occupied by a pixel driving circuit in the display substrate larger. In the same area of ​​the display substrate, only a few pixel driving circuits can be set, which will make it difficult for the display substrate to achieve a high PPI (e.g., PPI of 1500 or above) display.

[0087] In another implementation, such as Figure 5 As shown, the first power supply voltage signal line 3' is connected to the second electrode 2', and the second electrode 2' is directly connected to the first active pattern 4' located in the active layer through a via. Compared with the above implementation, this reduces the number of vias connecting the first power supply voltage signal line 3' and the first active pattern 4', thus reducing the area occupied by the vias connecting the first power supply voltage signal line 3' and the first active pattern 4' on the plane of the display substrate, thereby reducing the area occupied by the first power supply voltage signal line 3', the first electrode 1', and the second electrode 2' on the plane of the display substrate. However, in high PPI display substrates, the area of ​​each pixel driving circuit is small, and correspondingly, the areas of the first electrode 1' and the second electrode 2' in the pixel driving circuit are also small. Therefore, limited by the area of ​​the first electrode 1' and the second electrode 2', the capacitance value of the storage capacitor C' cannot be further increased.

[0088] Figure 6A This is a top view of a display substrate in some embodiments of this disclosure. Figure 6B for Figure 6AA cross-sectional view along the AA direction. As shown in Figure 6B The display substrate 100 provided by some embodiments of the present disclosure further includes: a substrate 1, a first gate conductive layer 2, a second gate conductive layer 3, and a first source-drain conductive layer 4.

[0089] For example, the substrate 1 can be a single-layer structure.

[0090] For example, the substrate 1 can be a single-layer structure.

[0091] For example, the substrate 1 can be a rigid substrate. The rigid substrate can be, for example, a glass substrate or a PMMA (Polymethyl Methacrylate) substrate. In this case, the display substrate 100 described above can be a rigid display substrate.

[0092] For example, the substrate 1 can be a flexible substrate. The flexible substrate can be, for example, a PET (Polyethylene Terephthalate) substrate, a PEN (Polyethylene Naphthalate Two Formic Acid Glycol Ester) substrate, or a PI (Polyimide) substrate. In this case, the display substrate 100 described above can be a flexible display substrate.

[0093] For example, the substrate 1 can be a multi-layer structure, i.e., the substrate 1 includes multiple sub-film layers, and the material of each sub-film layer can be the same or different.

[0094] For example, as shown in Figure 6B The first gate conductive layer 2 is located on the substrate 1, and the first transistor T1 includes a first gate pattern 21 located on the first gate conductive layer 2, which is multiplexed as a first plate C-1 of a storage capacitor C. The second gate conductive layer 3 is located on the first gate conductive layer 2, and the storage capacitor C includes a second plate C-2 located on the second gate conductive layer 3. In the orthographic projection of the substrate 1, the second plate C-2 and the first plate C-1 partially overlap. The first source-drain conductive layer 4 is located on the second gate conductive layer 3, and the first source-drain conductive layer 4 includes a conductive pattern 41 electrically connected with the second plate C-2.

[0095] For example, the materials of the first gate conductive layer 2, the second gate conductive layer 3, and the first source-drain conductive layer 4 are all conductive materials. The materials of the first gate conductive layer 2, the second gate conductive layer 3, and the first source-drain conductive layer 4 can be the same or different.

[0096] For example, the material of the first gate conductive layer 2, the second gate conductive layer 3 and the first source-drain conductive layer 4 can be a metal material, such as Al (aluminum), Ag (silver), Cu (copper), Cr (chromium), etc.

[0097] Correspondingly, an insulating layer is further arranged between each of the above-mentioned film layers. For example, the material of the insulating layer can be silicon oxide, silicon nitride, silicon oxynitride, etc.

[0098] As shown in FIG. 1, the conductive pattern 41 is electrically connected with the second plate C-2, and thus the area of the second plate C-2 of the storage capacitor C is increased by arranging the conductive pattern 41. Figure 6B

[0099] In some examples, the conductive pattern 41 includes a sub-portion 411, which overlaps the first plate C-1 in the orthogonal projection onto the substrate 1.

[0100] For example, the overlapping of the sub-portion 411 and the first plate C-1 means that the sub-portion 411 and the first plate C-1 have a facing area in the direction perpendicular to the substrate 1.

[0101] By the above arrangement, the facing area between the sub-portion 411 and the first plate C-1 is increased in addition to the area between the original first plate C-1 and the second plate C-2, thereby increasing the capacitance of the storage capacitor C, enhancing the stability of the data signal stored in the storage capacitor C in the pixel driving circuit P, and stabilizing the potential on the first gate pattern 21 (gate) in the first transistor T1.

[0102] Therefore, in the display substrate 100 of the present disclosure, the area of the second plate C-2 of the storage capacitor C is increased by arranging the conductive pattern 41 electrically connected with the second plate C-2. Moreover, the facing area between the sub-portion 411 of the conductive pattern 41 and the first plate C-1 is increased in addition to the area between the original first plate C-1 and the second plate C-2 by overlapping the sub-portion 411 of the conductive pattern 41 and the first plate C-1 in the orthogonal projection onto the substrate 1, thereby increasing the capacitance of the storage capacitor C, enhancing the stability of the data signal stored in the storage capacitor C in the pixel driving circuit P, and stabilizing the potential on the first gate pattern 21 (gate) in the first transistor T1.

[0103] On the other hand, such arrangement can avoid increasing the area of the first plate C-1 and the second plate C-2 in the display substrate 100, thereby avoiding increasing the space occupied by the first plate C-1 in the first gate conductive layer 2 and the space occupied by the second plate C-2 in the second gate conductive layer 3, and avoiding increasing the space occupied by the single pixel driving circuit P in the display substrate 100, which is conducive to realizing high PPI display of the display substrate 100.​

[0104] In some embodiments, the second gate conductive layer 3 further comprises: a first connection pattern 31 disposed apart from the second plate C-2, the first connection pattern 31 being electrically connected with the first plate C-1. In the orthogonal projection onto the substrate 1, the first connection pattern 31 overlaps with the sub-portion 411.

[0105] The first connection pattern 31 is electrically connected with the first plate C-1, which is equivalent to increasing the area of the first plate C-1 of the storage capacitor C.

[0106] Through the above arrangement, the area of the first connection pattern 31 directly opposite to the sub-portion 411 is increased, which is equivalent to increasing the area of the first plate C-1 and the second plate C-2 of the storage capacitor C directly opposite to each other, thereby further increasing the capacitance value of the storage capacitor C, and the stability of the data signal stored on the storage capacitor C in the pixel driving circuit P can be enhanced.

[0107] In some embodiments, the second transistor T2 comprises a second gate pattern 22 located on the first gate conductive layer 2. The orthogonal projection of the second gate pattern 22 onto the substrate 1 is located within the range of the orthogonal projection of the conductive pattern 41 onto the substrate 1.

[0108] Through the above arrangement, in the direction perpendicular to the substrate 1, the conductive pattern 41 can provide shielding effect for the second gate pattern 22, so as to avoid the signal transmitted on the wire (for example, the data line 51 described below) located on the side of the conductive pattern 41 away from the second gate pattern 22 from causing crosstalk to the signal transmitted by the second gate pattern 22, thereby avoiding affecting the stability of the signal transmitted by the second gate pattern 22.

[0109] In some embodiments, as shown in FIG. 1, the display substrate 100 further comprises: a second source-drain conductive layer 5 located on the first source-drain conductive layer 4. The second source-drain conductive layer 5 comprises: a data line 51 extending along a first direction Z. The first direction Z is parallel to the plane where the substrate 1 is located. Figure 6A

[0110] Exemplarily, the material of the second source-drain conductive layer 5 is a conductive material. The materials of the second source-drain conductive layer 5 and the first source-drain conductive layer 4 may, for example, be the same, or the materials of the second source-drain conductive layer 5 and the first source-drain conductive layer 4 may, for example, be different.

[0111] Exemplarily, the data line 51 is used for transmitting a data signal.

[0112] In some examples, the orthogonal projection of the second gate pattern 22 onto the substrate 1 is located within the range of the orthogonal projection of the conductive pattern 41 onto the substrate 1, and is also located within the range of the orthogonal projection of the data line 51 onto the substrate 1.

[0113] In this way, as shown in FIG. 1, the orthogonal projection of the second gate pattern 22 onto the substrate 1 is located within the range of the orthogonal projection of the conductive pattern 41 onto the substrate 1, and is also located within the range of the orthogonal projection of the data line 51 onto the substrate 1. Figure 6B ​As shown, the conductive pattern 41 between the second gate pattern 22 and the data line 51 can provide shielding effect for the second gate pattern 22 and the data line 51, avoiding interference of signals transmitted between the second gate pattern 22 and the data line 51.

[0114] In some embodiments, as shown in FIG. 1, the display substrate 100 further includes a semiconductor layer 6 between the substrate 1 and the first gate conductive layer 2. Figure 6A

[0115] For example, the material of the semiconductor layer 6 can include amorphous silicon, single crystal silicon, polycrystalline silicon or metal oxide semiconductor material.

[0116] In some examples, as shown in FIG. 1, the first transistor T1 includes a first active pattern 61 of the semiconductor layer 6, the first active pattern 61 includes a first connecting part 611 and a first channel region 612 arranged in sequence along the first direction Z. Figure 6C Figure 6P As shown, in the orthogonal projection onto the substrate 1, the first channel region 612, the first electrode plate C-1 and the second electrode plate C-2 partially overlap. The first connecting part 611 is electrically connected with the conductive pattern 41. Figure 6B

[0117] It should be noted that the orthogonal projection of the semiconductor layer 6 onto the substrate 1 has overlap with the orthogonal projection of the first gate conductive layer 2 onto the substrate 1. After forming the first gate conductive layer 2 on the side of the semiconductor layer 6 away from the substrate 1, the semiconductor layer 6 can be doped by taking the first gate conductive layer 2 as a mask. The part of the semiconductor layer 6 covered by the first gate conductive layer 2 is not doped and still has semiconductor characteristics, forming the channel region of the transistor. The part of the semiconductor layer 6 not covered by the first gate conductive layer 2 is doped and has conductor characteristics, forming the connecting part which can form the first electrode or the second electrode of the transistor. The part of the first gate conductive layer 2 overlapping with the semiconductor layer 6 forms the gate pattern (i.e. gate) of the transistor.

[0118] As shown in FIG. 1, the display substrate 100 further includes a second gate conductive layer 3. Figures 6C-6O As shown in FIG. 1, the display substrate 100 further includes a second gate conductive layer 3. Figure 6A As shown in FIG. 1, the display substrate 100 further includes a second gate conductive layer 3. Figure 6C is a top view of the semiconductor layer 6, Figure 6D is a top view of the first gate conductive layer 2, Figure 6E is a top view of the semiconductor layer 6 and the first gate conductive layer 2 superimposed, Figure 6F is a top view after manufacturing the insulating layer on the first gate conductive layer 2 and punching holes, Figure 6G is a top view of the second gate conductive layer 3, Figure 6H ​​​a plan view of the semiconductor layer 6, the first gate conductive layer 2 and the second gate conductive layer 3, Figure 6I a plan view after forming the insulating layer on the second gate conductive layer 3 and punching holes, Figure 6J a plan view of the first source-drain conductive layer 4, Figure 6K a plan view of the semiconductor layer 6, the first gate conductive layer 2, the second gate conductive layer 3 and the first source-drain conductive layer 4, Figure 6L a plan view after forming the insulating layer on the first source-drain conductive layer 4 and punching holes, Figure 6M a plan view of the second source-drain conductive layer 5, Figure 6N a plan view of the semiconductor layer 6, the first gate conductive layer 2, the second gate conductive layer 3, the first source-drain conductive layer 4 and the second source-drain conductive layer 5, Figure 6O a plan view after forming the insulating layer on the second source-drain conductive layer 5 and punching holes. In the above-mentioned figures, in order to clearly show the relationship between each film layer, each insulating layer is not shown in the above-mentioned figures.

[0119] As shown in FIG. 1, the first channel region 612, the first plate C-1 and the second plate C-2 partially overlap, so that the first plate C-1 can serve as the gate of the first transistor T1 while forming a storage capacitor C with the second plate C-2. Figure 6P As shown in FIG. 1, the first channel region 612, the first plate C-1 and the second plate C-2 partially overlap, so that the first plate C-1 can serve as the gate of the first transistor T1 while forming a storage capacitor C with the second plate C-2.

[0120] As shown in FIG. 1, the first channel region 612, the first plate C-1 and the second plate C-2 partially overlap, so that the first plate C-1 can serve as the gate of the first transistor T1 while forming a storage capacitor C with the second plate C-2. Figure 6P As shown in FIG. 1, the first channel region 612, the first plate C-1 and the second plate C-2 partially overlap, so that the first plate C-1 can serve as the gate of the first transistor T1 while forming a storage capacitor C with the second plate C-2.

[0121] As shown in FIG. 1, the first channel region 612, the first plate C-1 and the second plate C-2 partially overlap, so that the first plate C-1 can serve as the gate of the first transistor T1 while forming a storage capacitor C with the second plate C-2. Figure 6B As shown in FIG. 1, the first channel region 612, the first plate C-1 and the second plate C-2 partially overlap, so that the first plate C-1 can serve as the gate of the first transistor T1 while forming a storage capacitor C with the second plate C-2. Figure 3 As shown in FIG. 1, the first channel region 612, the first plate C-1 and the second plate C-2 partially overlap, so that the first plate C-1 can serve as the gate of the first transistor T1 while forming a storage capacitor C with the second plate C-2.

[0122] As shown in FIG. 1, the first channel region 612, the first plate C-1 and the second plate C-2 partially overlap, so that the first plate C-1 can serve as the gate of the first transistor T1 while forming a storage capacitor C with the second plate C-2. Figure 6C As shown in FIG. 1, the first channel region 612, the first plate C-1 and the second plate C-2 partially overlap, so that the first plate C-1 can serve as the gate of the first transistor T1 while forming a storage capacitor C with the second plate C-2.

[0123] For example, the first direction Z can be parallel to the third direction Y, or the first direction Z can have an angle with the third direction Y. For ease of explanation, this embodiment of the application uses the example of the first direction Z being parallel to the third direction Y.

[0124] For example, the intersection of the second direction X and the third direction Y means that there is an angle between the second direction X and the third direction Y. The angle can be any value that is not equal to zero; this application uses an angle of 90° for illustration.

[0125] The above settings can simplify the design and manufacturing process of the first connecting part 611 of the first active pattern 61.

[0126] In some embodiments, such as Figure 6C As shown, the first connecting portion 611 of the multiple first active patterns 61 located in the same row is an integral structure.

[0127] For example, "integrated structure" refers to two connected patterns arranged on the same layer, and the two patterns are continuous and not separated.

[0128] This configuration makes the structure between the first connecting parts 611 of the multiple first active patterns 61 more robust, and ensures that the connection between the multiple first connecting parts 611 is more stable.

[0129] In some embodiments, such as Figure 6J As shown, there are multiple conductive patterns 41 arranged in multiple rows and columns. Each row of conductive patterns 41 is arranged along the second direction X, and each column of conductive patterns 41 is arranged along the third direction Y. The first source-drain conductive layer 4 also includes multiple first power supply voltage signal lines 42 extending along the second direction X. Each first power supply voltage signal line 42 is electrically connected to multiple conductive patterns 41 in the same row.

[0130] For example, the first power supply voltage signal line 42 is used to transmit the first power supply voltage signal.

[0131] With the above settings, as Figure 6J As shown, the first power supply voltage signal transmitted in a first power supply voltage signal line 42 can be transmitted to multiple conductive patterns 41 in the same row, such as... Figure 6P As shown, the signal is transmitted via conductive pattern 41 to multiple first connection portions 611 in the same row, i.e., to the first transistor T1. Furthermore, as... Figure 6BAs shown, the first power voltage signal transmitted in the first power voltage signal line can also be transmitted to the second plate C-2 of the storage capacitor C through the conductive pattern 41. The first power voltage signal is a constant voltage signal, which can help stabilize the potential of the first plate C-1 of the storage capacitor C, i.e., help stabilize the potential on the first gate pattern 21 (gate) in the first transistor T1.

[0132] Meanwhile, in combination with Figure 6L and Figure 6P in the second direction X, the first power voltage signal line 42 can also form a parallel structure with multiple first connection portions 611 in the same row, thereby reducing the voltage drop of the first power voltage signal in the transmission process in the first power voltage signal line 42, thereby ensuring the stability of the first power voltage signal transmitted to the first transistor T1 in the same row, and helping to reduce the display difference of the pixels in the same row.

[0133] In some embodiments, as Figure 6J shown, the first power voltage signal line 42 and the multiple conductive patterns 41 electrically connected with the first power voltage signal line 42 form an integrated structure.

[0134] Through the above arrangement, the connection stability between the first power voltage signal line 42 and the conductive pattern 41 can be enhanced, and the connection line between the first power voltage signal line 42 and the conductive pattern 41 can be avoided, thereby simplifying the design and manufacturing process of the first power voltage signal line 42 and the multiple conductive patterns 41.

[0135] In some embodiments, as Figure 6H shown, in the orthographic projection to the substrate, the first connection portion 611 does not overlap with the second plate C-2. As Figure 6Q shown, the first connection portion 611 is electrically connected with the first power voltage signal line 42 and is electrically connected with the conductive pattern 41 through the first power voltage signal line 42.

[0136] Through such an arrangement, the first power voltage signal transmitted in the first power voltage signal line 42 can be transmitted to the first connection portion 611 of the first active pattern 61 of the first transistor T1 and simultaneously transmitted to the second plate C-2 of the storage capacitor C.

[0137] In other examples, the electrical connection between the first connection portion 611 and the conductive pattern 41 can also have other ways.

[0138] As Figure 7A shown, Figure 7A in the display substrate 100 in Figures 6F-6O , after the first gate conductive layer 2 is manufactured, the remaining film layers are different from Figures 7B-7K , as Figure 7B shown,a plan view of the first gate conductive layer 2 after forming the insulating layer and making holes, Figure 7B in which the insulating layer is different from Figure 6F in the position of the holes; Figure 7C a plan view of the second gate conductive layer 3, Figure 7C in which the insulating layer is different from Figure 6G in the shape of the second electrode plate C-2; Figure 7D a plan view of the semiconductor layer 6, the first gate conductive layer 2 and the second gate conductive layer 3 superimposed, Figure 7D in which the second electrode plate C-2 is electrically connected to the first conductive part 611 through the via hole, and Figure 6H in which the second electrode plate C-2 is disconnected from the first conductive part 611; Figure 7E a plan view of the second gate conductive layer 3 after forming the insulating layer and making holes, Figure 7E in which the insulating layer is different from Figure 6I in the position of the holes; Figure 7F a plan view of the first source-drain conductive layer 4, Figure 7F in which the first power voltage signal line 42 is different from Figure 6J in the arrangement; Figure 7G a plan view of the semiconductor layer 6, the first gate conductive layer 2, the second gate conductive layer 3 and the first source-drain conductive layer 4 superimposed, Figure 7G in which the first power voltage signal line 42 is electrically connected to the second electrode plate C-2 through the via hole, Figure 6K in which the first power voltage signal line 42 is electrically connected to the first conductive part 611 through the via hole, and the second electrode plate C-2 is electrically connected to the conductive pattern 41 through the via hole; Figure 7H a plan view of the first source-drain conductive layer 4 after forming the insulating layer and making holes, Figure 7H in which the insulating layer is different from Figure 6L in the position of the holes; Figure 7I a plan view of the second source-drain conductive layer 5, Figure 7I in which the data line 51 is different from Figure 6M in the shape; Figure 7J a plan view of the semiconductor layer 6, the first gate conductive layer 2, the second gate conductive layer 3, the first source-drain conductive layer 4 and the second source-drain conductive layer 5 superimposed, Figure 7J in which the data line 51 is electrically connected to the third connecting part 622 through the via hole, Figure 6N in which the data line 51 is electrically connected to the second connecting pattern 32 through the via hole, and the second connecting pattern 32 is electrically connected to the third connecting part 622 through the via hole; Figure 7K a plan view of the second source-drain conductive layer 5 after forming the insulating layer and making holes. In the above figures, the insulating layers are not shown in the figures for the sake of clarity of the relationship between the film layers.

[0139] as Figure 8As shown, the conductive pattern 41 is electrically connected to the second electrode plate C-2 through a via, and the second electrode plate C-2 is electrically connected to the first connecting part 611 through a via, thereby realizing the electrical connection between the first connecting part 611 and the conductive pattern 41. Figure 6P Compared to a direct electrical connection between the conductive pattern 41 and the first connecting portion 611, such as... Figure 7G As shown, the above arrangement can avoid setting the first power supply voltage signal line 42 on the first connection part 611, thereby saving the material of the first power supply voltage signal line 42 and reducing the space occupied by the first power supply voltage signal line 42 on the first source and drain conductive layer 4.

[0140] In some embodiments, such as Figure 7F As shown, there are multiple conductive patterns 41, which are arranged in multiple rows along the third direction Y and in multiple columns along the second direction X. Multiple conductive patterns 41 located in the same column are electrically connected to form a first power supply voltage signal line 42.

[0141] This configuration avoids the need to place the first power supply voltage signal line 42 in the second direction X, which saves materials and reduces the space occupied by the first power supply voltage signal line 42 in the display substrate 100, thus facilitating the realization of high PPI display of the display substrate 100.

[0142] In some embodiments, such as Figure 7F As shown, multiple conductive patterns 41 located in the same column form an integrated structure.

[0143] This configuration makes the connection between multiple conductive patterns 41 more robust and simplifies the design and manufacturing of multiple conductive patterns 41.

[0144] In some embodiments, such as Figure 8 As shown, in the orthographic projection onto the substrate 1, the first connecting portion 611 overlaps with the second electrode plate C-2. The first connecting portion 611 is electrically connected to the second electrode plate C-2, and is also electrically connected to the conductive pattern 41 through the second electrode plate C-2.

[0145] This configuration allows for electrical connection between the first connecting part 611 and the conductive pattern 41. Since multiple conductive patterns 41 located in the same column are electrically connected to form the first power supply voltage signal line 42, the first power supply voltage signal transmitted by the first power supply voltage signal line 42 can be transmitted to the first connecting part 611 through the second plate C-2, that is, to the first transistor T1.

[0146] In some embodiments, such as Figure 7C As shown, multiple second plates C-2 are arranged in multiple rows and columns. The second plates C-2 in each row are arranged along the second direction X, and the second plates C-2 in each column are arranged along the third direction Y. The multiple second plates located in the same row are electrically connected.

[0147] Through the above arrangement, the multiple rows of second electrode plates C-2 can form a mesh structure with the multiple columns of first power voltage signal lines 42, and the first power voltage signals transmitted in the first power voltage signal lines 42 can be transmitted in the mesh structure, so that the attenuation of the first power voltage signals in the transmission process in the first power voltage signal lines 42 can be further reduced, and the difference of the first power voltage signals transmitted to different pixel driving circuits P can be reduced.

[0148] In some embodiments, as shown in Figure 6A and Figure 7A , the patterns of different pixel driving circuits P are periodically arranged.

[0149] In this way, the design and manufacturing difficulty of the pattern of the multiple pixel driving circuits P can be simplified, and the space of the display substrate 100 can be fully utilized.

[0150] In some embodiments, as shown in Figure 9 and Figure 10A , the multiple pixel driving circuits P are arranged into multiple rows along the third direction Y and multiple columns along the second direction X. Any two adjacent rows of pixel driving circuits P are symmetrically arranged.

[0151] In this way, the design and manufacturing difficulty of the pattern of the multiple pixel driving circuits P can be simplified, and the space of the display substrate 100 can be fully utilized.

[0152] In some embodiments, as shown in Figure 6B , the second active pattern 62 further includes a third connecting part 622 arranged opposite to the second connecting part 621, and the third connecting part 622 is electrically connected with the data line 51.

[0153] The third connecting part 622 can be electrically connected with the data line 51 in various ways.

[0154] For example, as shown in Figure 6B , the second gate conductive layer 3 further includes a second connecting pattern 32. The second connecting pattern 32 is arranged apart from the first connecting pattern 31. One end of the second connecting pattern 32 is electrically connected with the data line 51, and the other end of the second connecting pattern 32 is electrically connected with the third connecting part 622, so as to realize the electrical connection between the third connecting part 622 and the data line 51.

[0155] Alternatively, the third connecting part 622 can be directly electrically connected with the data line 51 through a via hole.

[0156] In some examples, in combination with Figure 9 and Figure 11 , in the 2Nth row of pixel driving circuits P1 and the 2N+1th row of pixel driving circuits P2, the third connecting parts 622 of two pixel driving circuits in the same column are in an integrated structure, and N is a positive integer.

[0157] Through the above arrangement, the two adjacent pixel driving circuits in the same column can be designed more compactly, so as to reduce the space occupied by the 2Nth row of pixel driving circuit P1 and the 2N+1th row of pixel driving circuit P2 in the display substrate 100, which is conducive to realizing high PPI display of the display substrate 100.

[0158] In some embodiments, in combination with Figure 10A and Figure 10B , in the 2Nth row of pixel driving circuit P1 and the 2N+1th row of pixel driving circuit P2, the third connection part 622 of the two pixel driving circuits in the same column is electrically connected with the data line 51 through the same via hole K1.

[0159] Through the above arrangement, the number of via holes can be saved, the structure of the display substrate 100 is simplified, the preparation process of the display substrate 100 is simplified, and the design difficulty of the mask used to form the above-mentioned via hole K1 is also simplified.

[0160] In some embodiments, as shown in Figure 12 , in the 2Nth row of pixel driving circuit P1 and the 2N-1th row of pixel driving circuit P3, the first connection part 611 of the two pixel driving circuits in the same column is in an integrated structure, and N is a positive integer.

[0161] Through the above arrangement, the two adjacent pixel driving circuits in the same column can be designed more compactly, so as to reduce the space occupied by the 2Nth row of pixel driving circuit P1 and the 2N-1th row of pixel driving circuit P3 in the display substrate 100, which is conducive to realizing high PPI display of the display substrate 100.

[0162] In some embodiments, as shown in Figure 13 , in the case where the first source-drain conductive layer further includes a plurality of first power voltage signal lines 42 extending along the second direction X, the first power voltage signal line 42 electrically connected with the conductive pattern 41 of the 2Nth row of pixel driving circuit P1 and the first power voltage signal line 42 electrically connected with the conductive pattern 41 of the 2N-1th row of pixel driving circuit P3 are in an integrated structure, and N is a positive integer.

[0163] Through the above arrangement, the number of first power voltage signal lines 42 in the display substrate can be reduced, so that the two adjacent pixel driving circuits in the same column can be designed more compactly, the space occupied by the 2Nth row of pixel driving circuit P1 and the 2N-1th row of pixel driving circuit P3 in the display substrate 100 can be reduced, and high PPI display of the display substrate 100 is facilitated.

[0164] In some embodiments, in combination with Figure 9 and Figure 14In the pixel driving circuit P1 in the 2Nth row and the pixel driving circuit P3 in the 2N-1th row, the first connection part 611 of the two pixel driving circuits located in the same column is electrically connected to the first power supply voltage signal line 42 through the same via K2.

[0165] The above settings can reduce the number of vias, simplify the structure of the display substrate 100, simplify the manufacturing process of the display substrate 10, and simplify the design difficulty of the mask for forming the via K2.

[0166] In some examples, such as Figure 6B As shown, the display substrate 100 also includes a planarization layer 7, a pixel definition layer 8, and an encapsulation layer 9 located on the second source / drain conductive layer 5.

[0167] For example, the planarization layer 7 is formed by curing an organic material with good fluidity, which can form a flat surface on the planarization layer 7, which is beneficial for setting the first electrode of the light-emitting device L.

[0168] For example, the pixel definition layer 8 is an insulating material. The pixel definition layer 8 is used to define the light-emitting area of ​​the light-emitting device L. By setting the pixel definition layer 8, the light-emitting device L can have different light-emitting areas, thereby enabling the light-emitting device L to display different graphics.

[0169] For example, the encapsulation layer 9 is used to protect the area it covers. For instance, the encapsulation layer 9 covers the entire area where the display substrate 100 is located, and is used to protect the entire display substrate 100.

[0170] On the other hand, some embodiments of this disclosure also provide a method for manufacturing a display substrate 100. The display substrate 100 includes a plurality of pixel driving circuits P, and each pixel driving circuit P includes at least: a first transistor T1 and a storage capacitor C. Figure 15 As shown, the manufacturing method includes steps S100 to S400.

[0171] S100, Substrate 1 is provided.

[0172] S200, A first gate conductive layer 2 is formed on the substrate 1. For example... Figure 6B As shown, the first transistor T1 includes a first gate pattern 21 located in the first gate conductive layer 2, and the first gate pattern 21 is multiplexed as the first plate C-1 of the storage capacitor C.

[0173] S300, a second gate conductive layer 3 is formed on the first gate conductive layer 2. For example... Figure 6B As shown, the storage capacitor C includes a second electrode C-2 located in the second gate conductive layer 3. In a projection onto the substrate 1, the second electrode C-2 and the first electrode C-1 partially overlap.

[0174] S400, a first source / drain conductive layer 4 is formed on the second gate conductive layer 3. For example... Figure 6B As shown, the first source-drain conductive layer 4 includes a conductive pattern 41, which is electrically connected to the second electrode plate C-2.

[0175] The conductive pattern 41 includes a sub-part 411, which overlaps with the first electrode plate C-1 in the orthographic projection onto the substrate 1.

[0176] In the display substrate 100 formed by the above manufacturing method, the conductive pattern 41 is electrically connected to the second electrode C-2, which is equivalent to increasing the area of ​​the second electrode C-2 of the storage capacitor C. Furthermore, in the orthographic projection onto the substrate 1, the sub-part 411 of the conductive pattern 41 overlaps with the first electrode C-1, which increases the area directly opposite the first electrode C-1 in addition to the area directly opposite the original first electrode C-1 and second electrode C-2. This increases the capacitance value of the storage capacitor C and enhances the stability of the data signal stored on the storage capacitor C in the pixel driving circuit P.

[0177] In some embodiments, the pixel driving circuit P further includes a second transistor T2. Before forming the first gate conductive layer 2, the above fabrication method further includes: forming a semiconductor layer 6 on a substrate; and forming a first gate insulating film 10 on the semiconductor layer 6.

[0178] For example, the first gate insulating film 10 is used to protect the semiconductor layer 6. The material of the first gate insulating film 10 may be, for example, silicon oxide, silicon nitride, silicon oxynitride, etc.

[0179] In another implementation method described above, such as Figure 5 As shown, the second electrode 2' is directly connected to the first active pattern 4' located in the active layer through a via. That is, after forming the first electrode 1' and the insulating layer on the first electrode 1', the insulating layer is etched to form a via exposing the first active pattern 4'. Then, a cleaning solution is used to clean the via and remove any residue to reduce the contact resistance between the second electrode 2' and the first active pattern 4'. The cleaning solution is a buffered oxide etching solution, composed of hydrofluoric acid and water (where the concentration of hydrofluoric acid is 49%), or ammonium fluoride and water.

[0180] However, the cleaning solution can also corrode the insulating layer on the first electrode plate 1', causing the insulating layer to become thinner and crack, which will lead to a short circuit between the formed second electrode plate 2' and the first electrode plate 1'.

[0181] In some embodiments provided in this disclosure, after forming the first gate conductive layer 2 and before forming the second gate conductive layer 3, the fabrication method further includes: as follows: Figure 16A A second gate insulating film 20 is formed on the first gate conductive layer 2; such asFigure 16A A first mask pattern 30 is formed on the second gate insulating film 20; as Figure 16B The first mask pattern 30 is used to etch the display substrate to form a first via hole K1 penetrating the first gate insulating film 10 and the second gate insulating film 20 and exposing the semiconductor layer 6, and a second via hole K2 penetrating the second gate insulating film 20 and exposing the first gate conductive layer 2; the display substrate is cleaned with a cleaning solution; as Figure 16C The first mask pattern 30 is removed.

[0182] For example, the first via hole K1 and the second via hole K2 are used to form the first connection pattern 31.

[0183] Through the above arrangement, during the etching process of the display substrate by the first mask pattern 30, the first mask pattern 30 can protect the area covered thereby, and can avoid the cleaning solution from corroding the area covered by the first mask pattern 30, so as to avoid the second gate insulating film 20 from being thinned and reduce the risk of short circuit between the first electrode plate C-1 and the second electrode plate C-2 to be formed later.

[0184] In some examples, after S400, the manufacturing method further includes: as Figure 17 A second source-drain conductive layer 5 is formed on the first source-drain conductive layer 4; a planar layer 7 is formed on the second source-drain conductive layer 5; a pixel definition layer 8 is formed on the planar layer 7; and an encapsulation layer 9 is formed on the pixel definition layer 8.

[0185] The above merely provides a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can think of changes or replacements within the technical scope disclosed by the present disclosure, which should be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A display substrate, characterized in that, The display substrate includes multiple pixel driving circuits, and each pixel driving circuit includes at least: a first transistor and a storage capacitor; The display substrate further includes: Substrate; A first gate conductive layer is located on the substrate, and the first transistor includes a first gate pattern located on the first gate conductive layer, the first gate pattern being multiplexed as a first plate of the storage capacitor; A second gate conductive layer is located on the first gate conductive layer; the storage capacitor includes a second electrode located on the second gate conductive layer; in a projected image onto the substrate, the second electrode and the first electrode partially overlap; and, A first source-drain conductive layer is located on the second gate conductive layer. The first source-drain conductive layer includes: a conductive pattern and a plurality of first power supply voltage signal lines extending along a second direction. The conductive pattern is electrically connected to the second electrode plate, and the first power supply voltage signal lines are electrically connected to the conductive pattern. The second gate conductive layer further includes: a first connection pattern disposed at a distance from the second electrode plate, the first connection pattern being electrically connected to the first electrode plate; The conductive pattern includes a sub-part, which overlaps with the first electrode plate in orthographic projection onto the substrate, and the first connecting pattern overlaps with the sub-part.

2. The display substrate according to claim 1, characterized in that, The pixel driving circuit further includes a second transistor, the second transistor including a second gate pattern located in the first gate conductive layer; The orthographic projection of the second gate pattern onto the substrate is located within the orthographic projection range of the conductive pattern onto the substrate.

3. The display substrate according to claim 2, characterized in that, The display substrate further includes: a second source-drain conductive layer located on the first source-drain conductive layer; the second source-drain conductive layer includes: a data line extending along a first direction, the first direction being parallel to the plane of the substrate. The orthographic projection of the second gate pattern on the substrate is located within the orthographic projection range of the conductive pattern on the substrate, and also within the orthographic projection range of the data line on the substrate.

4. The display substrate according to claim 1, characterized in that, The pixel driving circuit also includes a second transistor; The display substrate further includes a semiconductor layer located between the substrate and the first gate conductive layer; The first transistor includes a first active pattern located on the semiconductor layer. The first active pattern includes a first connection portion and a first channel region disposed sequentially along a first direction, the first direction being parallel to the plane where the substrate is located. In a projection onto the substrate, the first channel region, the first electrode, and the second electrode partially overlap. The first connection portion is electrically connected to the conductive pattern. The second transistor includes a second active pattern located in the semiconductor layer, the second active pattern including a second connection portion; the second connection portion is electrically connected to the first electrode plate.

5. The display substrate according to claim 4, characterized in that, The conductive patterns are multiple, arranged in multiple rows and columns, with each row of conductive patterns arranged along a second direction and each column of conductive patterns arranged along a third direction; the second direction and the third direction intersect and are both parallel to the plane of the substrate. The first source and drain conductive layer further includes: a plurality of first power supply voltage signal lines extending along the second direction; A first power supply voltage signal line is electrically connected to multiple conductive patterns in the same row.

6. The display substrate according to claim 5, characterized in that, The first power supply voltage signal line and the plurality of conductive patterns electrically connected to the first power supply voltage signal line are integrally structured.

7. The display substrate according to claim 5 or 6, characterized in that, In the orthographic projection onto the substrate, the first connecting portion does not overlap with the second electrode plate; The first connecting part is electrically connected to the first power supply voltage signal line, and is also electrically connected to the conductive pattern through the first power supply voltage signal line.

8. The display substrate according to claim 4, characterized in that, The conductive patterns are multiple, arranged in multiple rows and columns, with each row of conductive patterns arranged along a second direction and each column of conductive patterns arranged along a third direction; the second direction and the third direction intersect and are both parallel to the plane of the substrate. The conductive patterns located in the same column are electrically connected to form a first power supply voltage signal line.

9. The display substrate according to claim 8, characterized in that, The multiple conductive patterns located in the same column are integrated into a single structure.

10. The display substrate according to claim 8 or 9, characterized in that, In a projection onto the substrate, the first connecting portion overlaps with the second electrode plate; The first connecting portion is electrically connected to the second electrode plate, and is also electrically connected to the conductive pattern through the second electrode plate.

11. The display substrate according to claim 8, characterized in that, Multiple second electrode plates are arranged in multiple rows and columns, with each row of second electrode plates arranged along a second direction and each column of second electrode plates arranged along a third direction; multiple second electrode plates located in the same row are electrically connected.

12. The display substrate according to claim 4, characterized in that, The number of the first active patterns is multiple, and the multiple first active patterns are arranged in multiple rows and columns. The first active patterns in each row are arranged along the second direction, and the first active patterns in each column are arranged along the third direction. The second direction and the third direction intersect and are both parallel to the plane where the substrate is located. In this configuration, the first connecting portions of multiple first active patterns located in the same row are connected together.

13. The display substrate according to claim 4, characterized in that, The plurality of pixel driving circuits are arranged in multiple rows and columns, with each row of pixel driving circuits arranged along the second direction and each column of pixel driving circuits arranged along the third direction. The pixel driving circuits of any two adjacent rows are symmetrically arranged.

14. The display substrate according to claim 13, characterized in that, The display substrate further includes: a second source-drain conductive layer located on the first source-drain conductive layer; the second source-drain conductive layer includes: a data line extending along a first direction; The second active pattern further includes: a third connecting portion, wherein the third connecting portion and the second connecting portion are respectively located at both ends of the second active pattern, and the third connecting portion is electrically connected to the data line; In the pixel driving circuits of the 2Nth row and the 2N+1th row, the third connection part of the two pixel driving circuits located in the same column is a single unit, where N is a positive integer.

15. The display substrate according to claim 13 or 14, characterized in that, In the pixel driving circuits of row 2N and row 2N-1, the first connection part of the two pixel driving circuits located in the same column is a single unit, where N is a positive integer.

16. The display substrate according to claim 13, characterized in that, In the case where the first source-drain conductive layer also includes multiple first power supply voltage signal lines extending along the second direction, the first power supply voltage signal line electrically connected to the conductive pattern of the 2Nth row pixel driving circuit and the first power supply voltage signal line electrically connected to the conductive pattern of the 2N-1th row pixel driving circuit are integrally structured, where N is a positive integer.

17. A display device, characterized in that, The display device includes: a display substrate as described in any one of claims 1 to 16.

18. A method for manufacturing a display substrate, characterized in that, The display substrate includes multiple pixel driving circuits, and each pixel driving circuit includes at least: a first transistor and a storage capacitor; The manufacturing method includes: Provide substrate; A first gate conductive layer is formed on the substrate; the first transistor includes a first gate pattern located on the first gate conductive layer, and the first gate pattern is multiplexed as a first plate of the storage capacitor. A second gate conductive layer is formed on the first gate conductive layer; the storage capacitor includes a second electrode plate located on the second gate conductive layer; the second gate conductive layer includes a first connection pattern spaced apart from the second electrode plate, the first connection pattern being electrically connected to the first electrode plate; in a projection onto the substrate, the second electrode plate and the first electrode plate partially overlap. A first source / drain conductive layer is formed on the second gate conductive layer; the first source / drain conductive layer includes: a conductive pattern and a plurality of first power supply voltage signal lines extending along a second direction, the conductive pattern being electrically connected to the second electrode plate, and the first power supply voltage signal lines being electrically connected to the conductive pattern; wherein, the conductive pattern includes a sub-part, which overlaps with the first electrode plate in orthographic projection onto the substrate, and does not overlap with the second electrode plate; In the orthographic projection onto the substrate, the first connection pattern overlaps with the sub-part.

19. The manufacturing method according to claim 18, characterized in that, The pixel driving circuit also includes a second transistor; Prior to forming the first gate conductive layer, the fabrication method further includes: A semiconductor layer is formed on the substrate; A first gate insulating film is formed on the semiconductor layer; After the formation of the first gate conductive layer and before the formation of the second gate conductive layer, the fabrication method further includes: A second gate insulating film is formed on the first gate conductive layer; A first mask pattern is formed on the second gate insulating film; The first mask pattern is used to etch the display substrate to be formed, forming a first via that penetrates the first gate insulating film and the second gate insulating film and exposes the semiconductor layer, and a second via that penetrates the second gate insulating film and exposes the first gate conductive layer; The display substrate to be formed is cleaned with a cleaning solution; Remove the first mask pattern.

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