OLED display panel and OLED display device

Abstract

The present application provides an OLED display panel and an OLED display device. The OLED display panel arranges an invalid routing line on a side of the anode close to the signal routing line, and arranges at least one invalid routing line and at least one fan-out routing line correspondingly at the anode arrangement position, so that the invalid routing line can fill in an area where no fan-out routing line is arranged or an area where the fan-out routing line is uneven, thereby improving the routing uniformity of the display area. The fan-out routing line passing through each sub-pixel and the invalid routing line passing through each sub-pixel are symmetrical about the center of the anode of each sub-pixel, which can improve the flatness and symmetry of the anode and the flatness of the light-emitting material, thereby ensuring consistent visual effects at different viewing angles and improving the display defects of the display panel.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an OLED display panel and an OLED display device. Background Art

[0002] OLED (Organic Light-Emitting Diode) display devices are widely used due to their advantages such as self-luminescence, wide color gamut, low power consumption, and flexible display. In order to reduce the border, existing OLED display devices use FIAA (Fanout In AA) technology, which sets the fan-out wiring in the display area. However, in FIAA technology, the density of wiring in the display area is different, resulting in poor display in visual effects. In order to improve the light efficiency, OLED display devices will introduce PLP (Pol-less Panel) technology, but PLP technology has higher requirements on the flatness of the display panel, which further aggravates the problems of periphery cyan and periphery powder, color separation diffraction under large viewing angles during display, resulting in poor display of the display panel.

[0003] Therefore, existing OLED display devices have a technical problem of poor display caused by different arrangement densities of wiring in FIAA. Summary of the Invention

[0004] Embodiments of the present application provide an OLED display panel and an OLED display device, which are used to alleviate the technical problem of poor display caused by different arrangement densities of traces in FIAA in existing OLED display devices.

[0005] An embodiment of the present application provides an OLED display panel, which includes a display area and a non-display area arranged on one side of the display area. The OLED display panel includes:

[0006] Signal routing;

[0007] A fan-out line is provided on one side of the signal line, and the fan-out line is connected to the signal line;

[0008] In which, the OLED display panel includes multiple sub-pixels, the sub-pixels include an anode, the anode is arranged on the side of the fan-out line away from the signal line, the fan-out line extends from the non-display area to the display area, the OLED display panel also includes an invalid line, the invalid line is arranged on the side of the anode close to the signal line, the display area includes a first area corresponding to the setting position of the anode, the first area includes at least one fan-out line and at least one invalid line, and the fan-out line passing through each sub-pixel and the invalid line passing through each sub-pixel are symmetrical about the center of the anode of each sub-pixel.

[0009] In some embodiments, the OLED display panel includes an upper frame, a left frame, a lower frame, and a right frame arranged around the display area, the fan-out routing includes a first routing portion and a second routing portion, the first routing portion and the second routing portion are connected, the first routing portion is arranged along the direction from the left frame to the right frame, and the second routing portion is arranged along the direction from the lower frame to the upper frame, the display area includes a second area corresponding to the setting position of the first routing portion, a third area corresponding to the setting position of the second routing portion, and a fourth area where the fan-out routing is not set.

[0010] In some embodiments, at least part of the inactive routing lines are disposed in the fourth region, and at a connection point between the fan-out routing lines and the signal routing lines, the inactive routing lines disposed in the fourth region are disconnected from the fan-out routing lines.

[0011] In some embodiments, at least part of the invalid routing is arranged in at least one of the second area and the third area, the invalid routing arranged in the second area and / or the third area is connected to one of the adjacent fan-out routings, and there is a distance between the invalid routing and the other adjacent fan-out routings.

[0012] In some embodiments, the length of the first routing portion decreases along the direction from the lower frame toward the upper frame, and the length of the second routing portion increases along the direction from the left frame toward the middle area of the display area.

[0013] In some embodiments, the invalid routing includes a third routing portion and a fourth routing portion, the third routing portion is set in the same direction as the first routing portion, the fourth routing portion is set in the same direction as the second routing portion, at least part of the third routing portion is connected to the fourth routing portion, and the length of the third routing portion increases along the direction from the lower frame to the upper frame, and the length of the fourth routing portion decreases along the left frame to the middle area of the display area.

[0014] In some embodiments, one of the second routing portions and one of the third routing portions in adjacent second routing portions are arranged to cross each other, and a distance exists between other second routing portions and the third routing portion in adjacent second routing portions.

[0015] In some embodiments, one of the adjacent second routing portions is cross-arranged with one of the third routing portions, and along the direction from the left frame to the right frame, other of the adjacent second routing portions are correspondingly connected to other of the third routing portions, and each of the third routing portions is disconnected from each other.

[0016] In some embodiments, the invalid routing lines and the fan-out routing lines are disposed on the same layer, and the unit distribution density of the invalid routing lines is the same as the unit distribution density of the fan-out routing lines.

[0017] In some embodiments, the sub-pixels include a red sub-pixel, a blue sub-pixel, and a green sub-pixel, and at least one of the invalid routing lines passing through the red sub-pixel, the invalid routing lines passing through the blue sub-pixel, and the invalid routing lines passing through the green sub-pixel is symmetrical about the center of the anode of the corresponding sub-pixel.

[0018] In some embodiments, the red sub-pixel includes a first anode, the blue sub-pixel includes a second anode, the invalid routing line passing through the red sub-pixel is symmetrical about the center of the first anode, and the invalid routing line passing through the blue sub-pixel is symmetrical about the center of the second anode.

[0019] In some embodiments, the green sub-pixel includes a third anode, and the invalid routing line passing through the green sub-pixel is symmetrical about the center of the third anode, and the invalid routing line passing through the green sub-pixel is symmetrical about the center line of the third anode along the direction from the lower frame toward the upper frame.

[0020] In some embodiments, along the direction from the left border to the right border, the invalid routing line that at least partially passes through the green sub-pixel of the adjacent column extends into the red sub-pixel, and / or the invalid routing line that at least partially passes through the green sub-pixel of the adjacent column extends into the blue sub-pixel, and the invalid routing line extending into the red sub-pixel and / or the blue sub-pixel is disconnected from the invalid routing line that passes through the red sub-pixel and the blue sub-pixel.

[0021] In some embodiments, the OLED display panel includes a driving circuit layer, and the driving circuit layer includes a first source-drain electrode layer and a second source-drain electrode layer;

[0022] The first source-drain layer includes the signal wiring, and the second source-drain layer includes the fan-out wiring and the invalid wiring.

[0023] In some embodiments, the OLED display panel includes a driving circuit layer, the driving circuit layer includes a first source and drain layer, a second source and drain layer, and a third source and drain layer, the first source and drain layer includes a source and a drain, the second source and drain layer includes the signal line, and the third source and drain layer includes the fan-out line and the invalid line.

[0024] In some embodiments, the OLED display panel further includes a first planarization layer and a second planarization layer, the first planarization layer is arranged between the first source and drain layer and the second source and drain layer, the second planarization layer is arranged between the second source and drain layer and the third source and drain layer, the signal routing includes a data line, and the fan-out routing passes through a via in the second planarization layer and is connected to the data line.

[0025] In some embodiments, the OLED display panel further includes a power signal line, the power signal line is disposed in the second source and drain layer, and the inactive wiring passes through a via hole and is connected to the power signal line.

[0026] At the same time, an embodiment of the present application provides an OLED display device, which includes the OLED display panel as described in any of the above embodiments.

[0027] Beneficial effects: The present application provides an OLED display panel and an OLED display device; the OLED display panel includes a display area and a non-display area arranged on one side of the display area, the OLED display panel includes a signal line and a fan-out line, the fan-out line is arranged on one side of the signal line, and the fan-out line is connected to the signal line, wherein the OLED display panel includes multiple sub-pixels, the sub-pixels include an anode, the anode is arranged on a side of the fan-out line away from the signal line, and the fan-out line extends from the non-display area to the display area, the OLED display panel also includes an invalid line, the invalid line is arranged on a side of the anode close to the signal line, the display area includes a first area corresponding to the anode setting position, the first area includes at least one fan-out line and at least one invalid line, and the fan-out lines passing through each sub-pixel and the invalid lines passing through each sub-pixel are symmetrical about the center of the anode of each sub-pixel. The present application sets an invalid routing line on the side of the anode close to the signal routing line, and sets at least one invalid routing line and at least one fan-out routing line corresponding to the anode setting position, so that the invalid routing line can fill the area where the fan-out routing line is not set or the area where the fan-out routing line is uneven, thereby improving the uniformity of the routing line in the display area, and making the fan-out routing line passing through each sub-pixel and the invalid routing line passing through each sub-pixel symmetrical about the center of the anode of each sub-pixel, which can improve the flatness and symmetry of the anode, improve the flatness of the light-emitting material, thereby making the visual effect consistent at each viewing angle, and improving the display poor performance of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The following detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings will make the technical solutions and other beneficial effects of the present application apparent.

[0029] Figure 1 Schematic diagram of an existing OLED display device.

[0030] Figure 2 This is a first schematic diagram of an OLED display panel provided in an embodiment of the present application.

[0031] Figure 3 A diagram of the film layers of a single sub-pixel in the OLED display panel provided in an embodiment of the present application.

[0032] Figures 4a to 4n for Figure 3 Exploded view of the individual film layers for a single sub-pixel in .

[0033] Figure 5 This is a second schematic diagram of the OLED display panel provided in an embodiment of the present application.

[0034] Figure 6 This is a third schematic diagram of the OLED display panel provided in an embodiment of the present application.

[0035] Figure 7 This is a fourth schematic diagram of the OLED display panel provided in an embodiment of the present application.

[0036] Figure 8 This is a fifth schematic diagram of the OLED display panel provided in an embodiment of the present application.

[0037] Figure 9 for Figure 3 Circuit diagram of a single sub-pixel in . DETAILED DESCRIPTION

[0038] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0039] like Figure 1 As shown, OLED display devices use FIAA technology to reduce the border. Figure 1It can be seen that in the FIAA technology, the fan-out trace 122 is set in the display area 111, and the fan-out trace 122 is connected to the data line 121 in the display area 111. The connection between the fan-out trace 122 and the data line 121 is indicated by the reference numeral 123. During the signal transmission process, the fan-out trace 122 is connected to the binding terminal of the binding area 112 to achieve normal signal transmission. Since the fan-out trace 122 is set in the display area 111 and the fan-out trace 122 is set with a separate film layer, the space for setting the fan-out trace 122 is larger. When connected to the binding terminal of the binding area 112, the length of the part located in the non-display area can be set smaller, thereby reducing the frame. But from Figure 1 As can be seen in FIG, the density of the fan-out traces 122 and the data line 121 is different due to the different locations of the connections between the fan-out traces 122 and the data line 121, which includes: first, there are no fan-out traces in some areas, such as Figure 1 There is no fan-out trace 122 in the middle area 131; secondly, fan-out traces are provided in some areas, but the fan-out traces are unevenly arranged in the horizontal and vertical directions, for example Figure 1 A fan-out trace 122 is provided in the middle area 2 132, but it can be seen that the fan-out trace on the right side of the horizontal portion of the bottommost fan-out trace 122 is arranged in the longitudinal direction, not in the transverse direction, resulting in unevenness in the transverse and longitudinal directions of the fan-out trace, and poor display when displayed on the OLED display panel. Furthermore, with the introduction of PLP technology into OLED display devices, the viewing angle and brightness of the display panel will be increased, further exacerbating problems such as peripheral blue and color separation diffraction at a large viewing angle, resulting in poor display of the display panel. Therefore, existing OLED display devices have a technical problem of poor display caused by different trace setting densities in FIAA.

[0040] In response to the above technical problems, the embodiments of the present application provide an OLED display panel and an OLED display device to alleviate the above technical problems.

[0041] like Figures 2 to 7 As shown, an embodiment of the present application provides an OLED display panel. The OLED display panel 2 includes a display area 281 and a non-display area 282 provided on one side of the display area 281. The OLED display panel 2 includes:

[0042] Signal traces (e.g. Figure 4j Data line 254a in);

[0043] The fan-out trace 31 is provided on one side of the signal trace, and the fan-out trace 31 is connected to the signal trace ( Figure 5 The connection between the fan-out trace 31 and the signal trace is shown by reference numeral 331 );

[0044] In which, the OLED display panel 2 includes multiple sub-pixels 41, the sub-pixel 41 includes an anode 261a, the anode 261a is arranged on the side of the fan-out line 31 away from the signal line, and the fan-out line 31 extends from the non-display area 282 to the display area 281, the OLED display panel 2 also includes an invalid line 32, the invalid line 32 is arranged on the side of the anode 261a close to the signal line, the display area 281 includes a first area 283 corresponding to the anode setting position, the first area 283 includes at least one fan-out line 31 and at least one invalid line 32, and the fan-out line 31 passing through each sub-pixel 41 and the invalid line 32 passing through each sub-pixel 41 are symmetrical about the center of the anode 261a of each sub-pixel 41.

[0045] An embodiment of the present application provides an OLED display panel, which arranges an invalid routing line on a side of the anode close to the signal routing line, and arranges at least one invalid routing line and at least one fan-out routing line corresponding to the anode setting position, so that the invalid routing line can fill the area where the fan-out routing line is not set or the area where the fan-out routing line is uneven, thereby improving the routing uniformity of the display area, and making the fan-out routing line passing through each sub-pixel and the invalid routing line passing through each sub-pixel symmetrical about the center of the anode of each sub-pixel, which can improve the flatness and symmetry of the anode and the flatness of the light-emitting material, thereby making the visual effect consistent at different viewing angles and improving the display defects of the display panel.

[0046] It should be noted that Figure 3 This is the design diagram of the film layer at a single sub-pixel. Figures 4a to 4n for Figure 3 The decomposition diagram of each film layer in the film layer design diagram. Since there are two symmetrically arranged circuits at a single sub-pixel, it can be seen that Figures 4a to 4m The membrane layers are all symmetrically arranged. Figure 4n This is the anode film layer diagram, which divides the display panel into the left and right sides with the center line of the display panel as the boundary. Figure 5 Only the arrangement of the fan-out traces 31 and the invalid traces 32 on the left side is shown. It can be understood that the fan-out traces 31 and the invalid traces 32 on the right side are symmetrically arranged with the fan-out traces 31 and the invalid traces 32 on the left side.

[0047] It should be noted that, taking a single binding terminal 33 as an example to illustrate the difference between the fan-out routing 31 and the invalid routing 32, the fan-out routing 31 refers to the routing that is uninterruptedly connected from the binding terminal 33 to the signal routing (the connection between the fan-out routing 31 and the signal routing is shown by the label 331), and the invalid routing 32 refers to routing other than the fan-out routing 31.

[0048] It should be noted that since the signal routing and fan-out routing are located in different layers and after setting the invalid routing, it is not convenient to show the signal routing and fan-out routing in the same figure. Figure 5 The connection between the fan-out trace 31 and the signal trace is shown by reference numeral 331. For the setting method of the signal trace, please refer to Figures 3 to 4n The setting method of the data line 254a.

[0049] In current display devices, the fan-out routing is set up as follows Figure 1 As shown, it can be seen that some areas do not have fan-out wiring, and the fan-out wiring is not uniformly arranged in the horizontal and vertical directions, which will lead to uneven film layer under the anode and uneven anode layer. When the light-emitting material is subsequently prepared, the light-emitting material of each sub-pixel is uneven, resulting in poor display. In response to the above technical problems, the present application sets the invalid wiring on the side of the anode close to the signal wiring, and at least one invalid wiring is set in the first area. Then, the invalid wiring of the present application can at least be set in the area without fan-out wiring (for example Figure 1 The area where only the data line 121 is located) and / or the area where the fan-out lines are uneven in the horizontal and vertical directions (e.g. Figure 1 In the region where the fan-out traces 122 are provided, the other fan-out traces 122 located on one side of the transverse portion of one fan-out trace 122 are not arranged transversely but longitudinally, and the other fan-out traces 122 located on one side of the longitudinal portion of one fan-out trace 122 are not arranged longitudinally but transversely), thereby at least improving the unevenness between traces without fan-out traces and traces with fan-out traces, and / or improving the unevenness in the transverse and longitudinal directions of traces with fan-out traces (for example Figure 5 By setting a third horizontal routing portion 321 and a fourth vertical routing portion 322, the lengths and spacings of the routings in any area provided with the fan-out routing 31 are similar or even equal in the horizontal and vertical directions, thereby making the routings uniformly arranged in the horizontal and vertical directions), and the fan-out routings passing through each sub-pixel and the invalid routings passing through each sub-pixel are symmetrical about the center of the anode of each sub-pixel, thereby improving the flatness and symmetry of the anode and improving the poor display of the display panel.

[0050] It should be noted that Figure 5 The connection between the invalid routing 32 and other routings is indicated by the reference numeral 332, and the connection between the fan-out routing 31 and the signal routing is indicated by the reference numeral 331. Figure 5 It can be distinguished by whether it is connected to the fan-out line. Figure 5As can be seen in the figure, the invalid routing 32 connected to other routings will not be connected to the fan-out routing 31, and the invalid routing 32 connected to the fan-out routing 31 will not be connected to the adjacent fan-out routing 31. It only serves as a flattened routing and will not affect the signal of the fan-out routing 31.

[0051] In one embodiment, if Figure 6 As shown, the OLED display panel 2 includes an upper frame 291, a left frame 292, a lower frame 293 and a right frame 294 arranged around the display area 281, and the fan-out routing 31 includes a first routing portion 311 and a second routing portion 312. The first routing portion 311 and the second routing portion 312 are connected. The first routing portion 311 is arranged along the direction from the left frame 292 to the right frame 294, and the second routing portion 312 is arranged along the direction from the lower frame 293 to the upper frame 291. The display area 281 includes a second area 284 corresponding to the setting position of the first routing portion 311, a third area 285 corresponding to the setting position of the second routing portion 312, and a fourth area 286 where the fan-out routing 31 is not set.

[0052] Setting the fan-out wiring only in a part of the area will result in poor flatness of the anode layer, which in turn leads to technical problems such as poor display. Figure 6 As shown, at least a portion of the inactive routing lines 32 are disposed in the fourth region 286, and at the connection 331 between the fan-out routing lines 31 and the signal routing lines, the inactive routing lines 32 disposed in the fourth region 286 are disconnected from the fan-out routing lines 31. By disposing the inactive routing lines in the fourth region, the inactive routing lines fill in the areas where no fan-out routing lines are disposed. Thus, routing lines are provided in each area of the display area, improving the uniformity of the routing lines in the display area. Furthermore, the fan-out routing lines passing through each sub-pixel and the inactive routing lines passing through each sub-pixel are symmetrical about the center of the anode of each sub-pixel, improving the flatness and symmetry of the anode and the flatness of the light-emitting material, thereby improving the display effect. Furthermore, at the connection between the fan-out routing lines and the signal routing lines, the inactive routing lines are disconnected from the fan-out routing lines to prevent the inactive routing lines from affecting the signals of the fan-out routing lines, enabling the fan-out routing lines to function normally.

[0053] It should be noted that, for ease of viewing, Figure 6 Only one connection point between a fan-out trace and a signal trace is shown. In fact, all fan-out traces will be connected to signal traces. The location of the connection point between each fan-out trace and signal trace can be seen in Figure 5 .

[0054] Specifically, for the problem described above: some areas have no fan-out routing, e.g. Figure 1 There is no fan-out trace 122 in the middle area 131. This application sets the invalid trace in the fourth area, such as Figure 6 As shown, it can be seen that the invalid routing 32 is arranged outside the connection between the fan-out routing 31 and the signal routing, and the invalid routing can be arranged in the same film layer as the fan-out routing, so that the uniformity of the film layer in which the fan-out routing is arranged can be improved, thereby improving the flatness of the anode layer and improving the display effect of the display panel.

[0055] Uneven arrangement of fan-out lines may result in poor flatness of the anode layer, which in turn may lead to technical problems such as poor display. Figure 5 As shown, at least part of the invalid routing 32 is arranged in at least one area of the second area 284 and the third area 285, and the invalid routing 32 arranged in the second area 284 and / or the third area 285 is connected to one of the adjacent fan-out routings 31, and there is a distance between the invalid routing 32 and the other fan-out routings 31 in the adjacent fan-out routings 31. By setting invalid routing lines in at least one of the second and third areas, the positions of the fan-out routing lines that only have longitudinal routing lines or only have transverse routing lines are filled, so that the routing density of each area of the display panel is similar or even equal, and the invalid routing lines can be set in the same film layer of the fan-out routing lines or be padded by setting them in other film layers, so that the uniformity of the film layer under the anode is improved, thereby improving the flatness of the anode layer and improving the display effect of the display panel, and the invalid routing lines are connected to one of the adjacent fan-out routing lines, and there is a distance between the invalid routing lines and the other fan-out routing lines in the adjacent fan-out routing lines, so as to avoid the invalid routing lines from conducting the adjacent fan-out routing lines, so that the fan-out routing lines can normally transmit the signals of the signal routing lines. Specifically, in response to the problem described above: some areas are provided with fan-out routing lines, but the fan-out routing lines are unevenly arranged in the transverse and longitudinal directions. As Figure 5 As shown, the present application sets the invalid trace 32 in the second area 284 and the third area 285, for example, the invalid trace 32 can be set on the right side of the horizontal part of the bottom fan-out trace 31, thereby improving the lateral uniformity of the fan-out trace 31. Figure 5 As can be seen in the figure, the third routing portion 321 is connected to a fan-out routing 31, and there is a gap between the third routing portion 321 and the adjacent fan-out routing 31, thereby preventing the third routing portion 321 from conducting the adjacent fan-out routing, so that the fan-out routing can transmit signals normally.

[0056] It should be noted that the length of the first routing section refers to the distance from the left end of the first routing section to the right end of the first routing section, the length of the second routing section refers to the distance from the upper end of the second routing section to the lower end of the second routing section, and similarly, the length of the third routing section refers to the distance from the left end of the third routing section to the right end of the third routing section, and the length of the fourth routing section refers to the distance from the upper end of the fourth routing section to the lower end of the second routing section. Furthermore, since the third and fourth routing sections can be disconnected, the lengths of the third and fourth routing sections can be the sum of the lengths of each disconnected section.

[0057] In one embodiment, if Figure 5 、 Figure 6 As shown, the length of the first routing portion 311 decreases along the direction of the lower frame 293 toward the upper frame 291 , and the length of the second routing portion 312 increases along the direction of the left frame 292 toward the middle area of the display area 281 .

[0058] The embodiment of the present application addresses the problem described above: some areas are provided with fan-out routing, but the fan-out routing is unevenly arranged in the horizontal and vertical directions. Specifically, the fan-out routing includes a first routing portion and a second routing portion, and the first routing portion in the horizontal direction and the second routing portion in the vertical direction are unevenly arranged. The embodiment of the present application makes the invalid routing include a third routing portion and a fourth routing portion, and the third routing portion and the fourth routing portion are arranged according to the setting direction and setting density of the first routing portion and the second routing portion, and the invalid routing can be set in the same film layer as the fan-out routing, thereby improving the uniformity of the film layer where the fan-out routing is located, improving the flatness of the film layer where the fan-out routing is located, and further improving the flatness of the anode layer, and making the fan-out routing passing through each sub-pixel and the invalid routing passing through each sub-pixel symmetrical about the center of the anode of each sub-pixel, thereby improving the symmetry of the anode, making the visual effects consistent under different viewing angles, and improving the display effect of the display panel.

[0059] Aiming at the technical problem that the uneven arrangement of fan-out lines and invalid lines leads to poor flatness. In one embodiment, Figure 5 、 Figure 6As shown, the invalid routing 32 includes a third routing portion 321 and a fourth routing portion 322. The third routing portion 321 is set in the same direction as the first routing portion 311, and the fourth routing portion 322 is set in the same direction as the second routing portion 312. At least part of the third routing portion 321 is connected to the fourth routing portion 322. Along the direction of the lower frame 293 toward the upper frame 291, the length of the third routing portion 321 increases, and along the left frame to the middle area of the display area, the length of the fourth routing portion decreases. By increasing the width of the third routing portion from bottom to top, the trend of the width of the third routing portion is opposite to the trend of the width of the first routing portion, so that the third routing portion can fill the idle area of the first routing portion, thereby improving the uniformity of the lateral portion of the film layer where the fan-out routing is located; the width of the fourth routing portion is reduced from left to right, so that the trend of the width of the fourth routing portion is opposite to the trend of the width of the second routing portion, thereby making the fourth routing portion fill the idle area of the second routing portion, thereby improving the uniformity of the longitudinal portion of the film layer where the fan-out routing is located; thereby, the flatness of the anode layer can be improved, thereby improving the display effect of the display panel.

[0060] Specifically, the first routing portion and the second routing portion can be set at a preset angle, and the preset angle is determined according to the actual design of the fan-out routing. The range of the preset angle can be 0 degrees to 180 degrees, excluding 0 degrees. For example, the first routing portion and the second routing portion are set horizontally and vertically respectively, and the first routing portion and the second routing portion are 90 degrees.

[0061] The above embodiment is described in detail using the example of increasing lengths of the third routing portions and decreasing lengths of the fourth routing portions, but the embodiments of the present application are not limited thereto. For example, the lengths of the third routing portions are equal and the lengths of the fourth routing portions are equal.

[0062] Specifically, the problem of uneven arrangement of the first horizontal routing portion and the second vertical routing portion is addressed, such as Figure 5As shown, the third routing portion 321 includes a first sub-portion 321a and a second sub-portion 321b, the first sub-portion 321a is arranged to cross the second routing portion 312, and the first sub-portion 321a is connected to a second routing portion 312 in the adjacent second routing portion 312, and there is a gap between the first sub-portion 321a and other second routing portions 312 in the adjacent second routing portion 312, the fourth routing portion 322 includes a third sub-portion 322a and a fourth sub-portion 322b, the third sub-portion 322a is connected to a first routing portion 311 in the adjacent first routing portion 311, there is a gap between the third sub-portion 322a and other first routing portions 311 in the adjacent first routing portion 311, and the second sub-portion 321b is arranged to cross the fourth sub-portion 322b. By making the third routing portion 321 cross with the second routing portion 312 and the fourth routing portion 322, respectively, and making the fourth routing portion 322 cross with the first routing portion 311 and the third routing portion 321, respectively, the third routing portion and the fourth routing portion can be used to fill the uneven area of the first routing portion and the second routing portion, so that any part of the film layer where the fan-out routing is located includes horizontally arranged routing and vertically arranged routing, thereby improving the flatness of the film layer where the fan-out routing is located, and by controlling the width of the third routing portion and the fourth routing portion, the flatness of the film layer where the fan-out routing is located can be further improved, the flatness of the anode layer can be improved, and the display effect of the display panel can be improved.

[0063] In one embodiment, if Figure 5 As shown, one of the second routing portions 312 and one of the third routing portions 321 in adjacent second routing portions 312 are intersected, and a distance exists between the other second routing portions 312 and the third routing portion 321 in adjacent second routing portions. By intersecting a second routing portion and a third routing portion, and spacing between the other second routing portions and the third routing portions in adjacent second routing portions, and by ensuring that the fan-out routing portions passing through each sub-pixel and the inactive routing portions passing through each sub-pixel are symmetrical about the center of the anode of each sub-pixel, the third routing portions arranged on the second routing portions can be evenly arranged, thereby improving the flatness of the film layer where the fan-out routing portions are located, and improving the flatness and symmetry of the anode layer, thereby improving the display effect of the display panel.

[0064] Specifically, when the third routing portion is cross-arranged with the second routing portion, the third routing portion can be symmetrically arranged with respect to the second routing portion, thereby further improving the flatness and symmetry of the film layer where the fan-out routing is located, and improving the poor flatness and symmetry of the anode layer, resulting in different visual effects at a wide viewing angle, color separation diffraction and other poor display problems.

[0065] In one embodiment, if Figure 8As shown, one of the adjacent second routing sections 312 intersects with one of the third routing sections 321. Along the direction from the left frame to the right frame, the other second routing sections 312 in the adjacent second routing sections 312 are correspondingly connected to the third routing sections 321, and the third routing sections 321 are disconnected from each other. By intersecting a second routing section with a third routing section in the adjacent second routing sections, and connecting the other second routing sections to the third routing section, the impedance uniformity of each second routing section can be improved, avoiding impedance inconsistencies among the fan-out routings that could lead to poor display.

[0066] The different distribution densities of the fan-out traces result in poor flatness of the anode layer, which in turn leads to a technical problem of poor display. In one embodiment, Figure 4l 、 Figure 5 As shown, the inactive traces 32 are arranged on the same layer as the fan-out traces 31, and the unit distribution density of the inactive traces 32 is the same as that of the fan-out traces 31. By placing the inactive traces on the same layer as the fan-out traces, the uniformity and flatness of the film layer in which the fan-out traces are located can be improved, thereby improving the flatness of the anode layer. Furthermore, by making the unit distribution density of the inactive traces the same as that of the fan-out traces, the uniformity of the film layer in which the fan-out traces are located can be further improved, the flatness of the anode layer can be improved, and the display quality of the display panel can be improved.

[0067] Specifically, the unit distribution density refers to the arrangement density of routing within a unit area. For example, if there is a fan-out routing of 0.5 square millimeters within 1 square millimeter, the unit distribution density of the fan-out routing is 0.5.

[0068] Taking into account that the invalid routing will be disconnected during setting, the unit distribution density of the invalid routing will be slightly smaller than the unit distribution density of the fan-out routing. Therefore, the difference between the unit distribution density of the invalid routing and the unit distribution density of the fan-out routing can be made less than a value, which can be determined based on the flatness of the anode layer and specifically limited.

[0069] The uneven distribution of the fan-out wiring leads to poor flatness of the anode layer, which in turn leads to poor display technology. In one embodiment, Figure 7As shown, the sub-pixel 41 includes a red sub-pixel 412, a blue sub-pixel 411, and a green sub-pixel 413. At least one of the invalid routing lines 32 passing through the red sub-pixel 412, the invalid routing line 32 passing through the blue sub-pixel 411, and the invalid routing line 32 passing through the green sub-pixel 413 is symmetrical about the center of the anode of the corresponding sub-pixel 41. By making at least one of the invalid routing lines passing through the red sub-pixel, the blue sub-pixel, and the green sub-pixel symmetrical about the center of the anode, the flatness and symmetry of the anode are improved. When emitting material is provided on the anode, the emitting material can be made relatively flat, so that the OLED display panel can display normally, thereby improving the technical problem of poor display of the OLED display panel. Specifically, Figure 7 Sub-pixels are shown in the figure, but it can be understood that sub-pixels are a virtual concept and do not belong to the structure in the OLED display panel. The embodiments of this application are only for the convenience of explaining the setting method of invalid wiring.

[0070] In one embodiment, if Figure 7 As shown, the red sub-pixel 412 includes a first anode 422, and the blue sub-pixel 411 includes a second anode 421. The inactive trace 32 passing through the red sub-pixel 412 is symmetrical about the center of the first anode 422, and the inactive trace 32 passing through the blue sub-pixel 411 is symmetrical about the center of the second anode 421. By making the inactive traces passing through the red sub-pixels symmetrical about the center of the first anode, and the inactive traces passing through the blue sub-pixels symmetrical about the center of the second anode, when the anode layer is provided, the anode layer can be symmetrically provided about the inactive traces, resulting in better flatness and symmetry of the anode layer. When emitting material is provided on the anode layer, the emitting material can be made relatively flat, thereby enabling the OLED display panel to display normally and improving the technical problem of poor display of the OLED display panel.

[0071] In one embodiment, if Figure 7 As shown, the green sub-pixel 413 includes a third anode 423, and the inactive routing line 32 passing through the green sub-pixel 413 is symmetrical about the center of the third anode 423. Furthermore, along the direction from the lower frame toward the upper frame, the inactive routing line 32 passing through the green sub-pixel 413 is symmetrical about the center line of the third anode 423. In view of the fact that the fan-out routing lines are symmetrically arranged about the center line of the green sub-pixel, the present application makes the inactive routing lines symmetrical about the center line of the green sub-pixel, thereby making the fan-out routing lines and the inactive routing lines symmetrical. This improves the flatness of the film layer where the fan-out routing lines are located, enhances the flatness and symmetry of the anode layer, and alleviates the technical problem of poor display performance of the OLED display panel.

[0072] Specifically, the red sub-pixel and the blue sub-pixel are located in the same row, and the green sub-pixel is located between adjacent red sub-pixels. Figure 8 As shown, the fan-out lines 31 and the invalid lines 32 are arranged in the lateral direction in such a manner that three lines serve as a repeating unit 34 , one line is arranged in the red sub-pixel or the blue sub-pixel, and the other two lines are arranged between the blue sub-pixel and the red sub-pixel.

[0073] In one embodiment, if Figure 8 As shown, along the direction from the left border to the right border, the invalid routing line 32 that at least partially passes through the green sub-pixel 413 of the adjacent column extends into the red sub-pixel 412, and / or at least partially passes through the green sub-pixel 413 of the adjacent column extends into the blue sub-pixel 411. The invalid routing line 32 extending into the red sub-pixel 412 and / or the blue sub-pixel 411 is disconnected from the invalid routing line 32 passing through the red sub-pixel 412 and the blue sub-pixel 411. By extending the invalid routing line that passes through the green sub-pixel of the adjacent column into the red sub-pixel and / or the blue sub-pixel, the impedance uniformity of each second routing portion can be improved, avoiding display defects caused by inconsistent impedance of each fan-out routing line. The invalid routing line that extends into the red sub-pixel and / or the blue sub-pixel is disconnected from the invalid routing line that passes through the red sub-pixel and the blue sub-pixel, preventing the invalid routing line from conducting into adjacent fan-out routing lines, thereby ensuring normal operation of the fan-out routing lines.

[0074] The above embodiment uses a pixel design as an example to explain in detail the arrangement of the invalid routing. However, the embodiments of the present application are not limited thereto. For example, the invalid routing passing through the green sub-pixel is symmetrical about the center of the third anode. The invalid routing passing through the blue sub-pixel is symmetrical about the center line of the second anode along the direction from the lower frame to the upper frame. The invalid routing passing through the red sub-pixel is symmetrical about the center line of the first anode. In one embodiment, the OLED display panel includes a drive circuit layer, and the drive circuit layer includes a first source and drain electrode layer and a second source and drain electrode layer.

[0075] The first source-drain layer is formed with the signal routing, and the second source-drain layer includes the fan-out routing and the invalid routing. When setting the signal routing, the fan-out routing, and the invalid routing, the signal routing can be set in the first source-drain layer, and the fan-out routing can be set in the second source-drain layer, so that the fan-out routing can be set in the display area, reducing the frame occupied by the fan-out routing, and the invalid routing is set in the second source-drain layer, so that the invalid routing can flatten the film layer where the fan-out routing is located, improve the flatness of the second source-drain layer, improve the flatness of the anode layer, and improve the display effect of the display panel.

[0076] In one embodiment, if Figures 2 to 4nThe OLED display panel 2 includes a driving circuit layer, which includes a first source-drain electrode layer 252, a second source-drain electrode layer 254, and a third source-drain electrode layer 256. The first source-drain electrode layer 252 includes a source and a drain electrode, the second source-drain electrode layer 254 includes a signal line (e.g., a data line 254a), and the third source-drain electrode layer 256 includes a fan-out line 31 and an invalid line 32. When setting the signal line, the fan-out line, and the invalid line, the signal line can be set in the second source-drain electrode layer, and the fan-out line can be set in the third source-drain electrode layer, so that the fan-out line can be set in the display area, reducing the frame occupied by the fan-out line. The invalid line is set in the third source-drain electrode layer so that the invalid line can flatten the film layer where the fan-out line is located, thereby improving the flatness of the third source-drain electrode layer, improving the flatness of the anode layer, and improving the display effect of the display panel.

[0077] In one embodiment, if Figures 2 to 4n The OLED display panel 2 further includes a first planarization layer 253 and a second planarization layer 255. The first planarization layer 253 is disposed between the first source-drain electrode layer 252 and the second source-drain electrode layer 254, and the second planarization layer 255 is disposed between the second source-drain electrode layer 254 and the third source-drain electrode layer 256. The signal routing includes a data line 254a disposed in the second source-drain electrode layer 254. The fan-out routing 31 passes through a via 255a in the second planarization layer 255 and is connected to the data line 254a. By configuring the signal routing to include a data line, configuring the data line in the second source-drain electrode layer, and configuring the fan-out routing in the third source-drain electrode layer, the fan-out routing can pass through the via in the second planarization layer and connect to the data line, thereby enabling data line signal transmission. Furthermore, since the fan-out routing is disposed in the display area, the border occupied by the fan-out routing is reduced, thereby achieving a narrow border for the display panel.

[0078] The technical problem of static electricity may occur due to the setting of floating invalid traces. In one embodiment, Figures 2 to 4n The OLED display panel 2 further includes a power signal line 254b disposed on the second source / drain layer 254. The inactive trace 32 passes through a via and is connected to the power signal line 254b. By connecting the inactive trace to the power signal line, static electricity generated by the inactive trace can be prevented from damaging the circuit. Furthermore, the inactive trace is only connected to the power signal line and does not affect the normal operation of the circuit.

[0079] At the same time, the working principle and film layer structure of the OLED display panel in the embodiment of the present application are explained through the film layer design and circuit design of a single sub-pixel in the OLED display panel.

[0080] like Figures 2 to 4n 、 Figure 9 As shown, Figure 9 for Figure 3 Pixel driving circuit diagram of a single sub-pixel in the OLED display panel, the pixel driving circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a first reset transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a second reset transistor T7, a storage capacitor Cst, a boost capacitor Cboost, a power signal line VDD, a low-potential signal line VSS, a data line Data, a first scan line PScan(n), a second scan line P Scan(n-1), a third scan line N Scan(n), a fourth scan line N Scan(n-5) and a light-emitting control line EM.

[0081] Among them, P Scan(n) represents the scan line of this level, P Scan(n-1) represents the scan line of the previous level, and the above scan lines are used to control P-type transistors, N Scan(n) represents the scan line of this level, N Scan(n-5) represents the scan line of the previous five levels, and these two scan lines are used to control N-type transistors.

[0082] The working principle of the circuit is as follows: in the first stage, the first reset transistor T4 and the second reset transistor T7 are turned on, and the gate of the first transistor T1 is reset by the reset signal output by the first reset signal line VI-G, and the pixel light-emitting unit LED is reset by the reset signal output by the second reset signal line VI-ANO; in the second stage, the second transistor T2 and the third transistor T3 are turned on, and the data signal input by the data line Data is written into the gate of the first transistor T1; in the third stage, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on to drive the pixel light-emitting unit LED to emit light.

[0083] The embodiments of this application are Figure 2 The circuit diagram in FIG is used as an example for detailed description, but the embodiments of the present application are not limited thereto. For example, a display panel using a 7T1C (7 transistors and one capacitor) circuit can also adopt the design of the present application.

[0084] In one embodiment, if Figure 2 As shown, the OLED display panel 2 further includes a substrate 21 , a light shielding layer 22 and a buffer layer 23 , wherein the light shielding layer 22 is located between the substrate 21 and the buffer layer 23 .

[0085] In one embodiment, if Figure 2 As shown, the width of the projection of the light-shielding layer 22 on the substrate 21 is greater than the maximum width between the channel region of the first semiconductor layer 241 and the channel region of the second semiconductor layer 247. The light-shielding layer is used to shield the channel regions of the first semiconductor layer and the second semiconductor layer to prevent external light from affecting the performance of the first semiconductor layer and the second semiconductor.

[0086] In one embodiment, if Figure 2 As shown, the light shielding layer 22 is connected to the first source-drain electrode layer 252 , and the impedance of the first source-drain electrode layer is reduced by connecting the light shielding layer to the first source-drain electrode layer.

[0087] In one embodiment, if Figure 2 As shown, the OLED display panel 2 also includes a first semiconductor layer 241, a first gate insulating layer 242, a first gate layer 243, a second gate insulating layer 244, a second gate layer 245, a first interlayer insulating layer 246, a second semiconductor layer 247, a third gate insulating layer 248, a third gate layer 249, and a second interlayer insulating layer 251. By making the OLED display panel adopt LTPO (Low Temperature Poly-Oxide, LTPO) technology, the power consumption of the OLED display panel can be reduced.

[0088] In one embodiment, the material of the first semiconductor layer includes polysilicon, and the material of the second semiconductor layer includes metal oxide.

[0089] In one embodiment, if Figure 2 As shown, the OLED display panel 2 further includes a third planarization layer 257 , an anode layer 261 , a pixel definition layer 262 , a light-emitting material layer 263 , and a cathode layer 264 .

[0090] In one embodiment, if Figure 2 As shown, the OLED display panel 2 further includes an encapsulation layer 27 , which includes a first inorganic layer, an organic layer, and a second inorganic layer.

[0091] Specifically, Figure 3 This is the design diagram of the film layer at a single sub-pixel. For easy viewing, Figure 3 Only the thin film transistor is marked. Figures 4a to 4n for Figure 3 The exploded diagram of each film layer in the film design diagram is shown in Figures 4a to 4n The structural design of each membrane layer is described in detail.

[0092] Figure 4a This is the film design for the first semiconductor layer. Figure 4b The first gate layer 243 is designed as a film layer of the first gate layer. The first gate layer 243 includes a light emitting control line 243 a and a first scanning line 243 b. Figure 4c The second gate layer 245 is designed as a film layer of the second gate layer. The second gate layer 245 includes a first reset signal line 245 a , a first portion 245 c of the third scan line, and a first portion 245 b of the fourth scan line. Figure 4d Design of the film layer for the second semiconductor layer, Figure 4eThe third gate layer 249 is designed as a film layer of the third gate layer. The third gate layer 249 includes a second portion 249 b of the third scan line and a second portion 249 a of the fourth scan line. Figure 4f The via holes 251a are designed to connect the first source and drain layer to the first semiconductor layer, namely, the via holes of the first gate insulating layer, the second gate insulating layer, the first interlayer insulating layer, the third gate insulating layer and the second interlayer insulating layer. Figure 4g The via holes 251b are designed to connect the first source and drain layer to the second semiconductor layer, that is, via holes between the second interlayer insulating layer and the third gate insulating layer.

[0093] Figure 4h The first source / drain layer 252 is designed as a film layer of the first source / drain layer. The first source / drain layer 252 includes a second reset signal line 252 a. Figure 4i This is the design of the via hole 253a in the first planarization layer. Figure 4j The second source / drain electrode layer 254 is designed as a film layer of the second source / drain electrode layer. The second source / drain electrode layer 254 includes a data line 254 a and a power signal line 254 b . Figure 4k This is the design of the via hole 255a in the second planarization layer. Figure 4l The third source / drain layer 256 is a film layer design including a fan-out trace 31 and an inactive trace 32 . Figure 4m This is the design of the via hole 257a in the third planarization layer. Figure 4n The anode layer 261 is designed as an anode layer. The anode layer 261 includes an anode 261 a.

[0094] Specifically, for the design of the traces and vias in each film layer, Figure 9 Circuit design and Figure 3 The membrane design in is determined and will not be elaborated here.

[0095] It should be noted that since the traces are illustrated separately in the film diagram and the circuit diagram, they are labeled differently. For example, the data line is labeled "Data" in the circuit diagram and "254a" in the film diagram. However, it is understandable that both are the same data line; they are simply labeled differently in the circuit diagram and the film diagram. Similarly, other traces, such as scan lines, reset signal lines, and light control lines, are labeled differently and will not be further explained here.

[0096] At the same time, an embodiment of the present application provides an OLED display device, which includes the OLED display panel as described in any of the above embodiments.

[0097] According to the above embodiments, it can be seen that:

[0098] An embodiment of the present application provides an OLED display panel and an OLED display device; the OLED display panel includes a display area and a non-display area arranged on one side of the display area, the OLED display panel includes a signal line and a fan-out line, the fan-out line is arranged on one side of the signal line, and the fan-out line is connected to the signal line, wherein the OLED display panel includes multiple sub-pixels, the sub-pixels include an anode, the anode is arranged on a side of the fan-out line away from the signal line, and the fan-out line extends from the non-display area to the display area, the OLED display panel also includes an invalid line, the invalid line is arranged on a side of the anode close to the signal line, the display area includes a first area corresponding to the anode setting position, the first area includes at least one fan-out line and at least one invalid line, and the fan-out lines passing through each sub-pixel and the invalid lines passing through each sub-pixel are symmetrical about the center of the anode of each sub-pixel. The present application sets an invalid routing line on the side of the anode close to the signal routing line, and sets at least one invalid routing line and at least one fan-out routing line corresponding to the anode setting position, so that the invalid routing line can fill the area where the fan-out routing line is not set or the area where the fan-out routing line is uneven, thereby improving the uniformity of the routing line in the display area, and making the fan-out routing line passing through each sub-pixel and the invalid routing line passing through each sub-pixel symmetrical about the center of the anode of each sub-pixel, which can improve the flatness and symmetry of the anode, improve the flatness of the light-emitting material, thereby making the visual effect consistent at each viewing angle, and improving the display poor performance of the display panel.

[0099] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0100] The above is a detailed introduction to an OLED display panel and an OLED display device provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An OLED display panel, characterized in that: The OLED display panel comprises a display area and a non-display area provided on one side of the display area, and includes: Signal routing; A fan-out line is provided on one side of the signal line, and the fan-out line is connected to the signal line; In which, the OLED display panel includes multiple sub-pixels, the sub-pixels include an anode, the anode is arranged on the side of the fan-out line away from the signal line, the fan-out line extends from the non-display area to the display area, the OLED display panel also includes an invalid line, the invalid line is arranged on the side of the anode close to the signal line, the display area includes a first area corresponding to the setting position of the anode, the first area includes at least one fan-out line and at least one invalid line, and the fan-out line passing through each sub-pixel and the invalid line passing through each sub-pixel are symmetrical about the center of the anode of each sub-pixel.

2. The OLED display panel according to claim 1, wherein: The OLED display panel includes an upper frame, a left frame, a lower frame, and a right frame arranged around the display area. The fan-out routing includes a first routing portion and a second routing portion. The first routing portion and the second routing portion are connected. The first routing portion is arranged along the direction from the left frame to the right frame, and the second routing portion is arranged along the direction from the lower frame to the upper frame. The display area includes a second area corresponding to the location where the first routing portion is set, a third area corresponding to the location where the second routing portion is set, and a fourth area where the fan-out routing is not set.

3. The OLED display panel according to claim 2, wherein: At least part of the ineffective routing lines are arranged in the fourth region, and at a connection point between the fan-out routing lines and the signal routing lines, the ineffective routing lines arranged in the fourth region are disconnected from the fan-out routing lines.

4. The OLED display panel according to claim 3, wherein: At least part of the invalid routing is arranged in at least one area of the second area and the third area, the invalid routing arranged in the second area and / or the third area is connected to one of the adjacent fan-out routings, and there is a distance between the invalid routing and the other fan-out routings in the adjacent fan-out routings.

5. The OLED display panel according to claim 2, wherein: The length of the first wiring portion decreases along the direction from the lower frame to the upper frame, and the length of the second wiring portion increases along the direction from the left frame to the middle area of the display area.

6. The OLED display panel according to claim 5, wherein: The invalid routing includes a third routing portion and a fourth routing portion. The third routing portion is set in the same direction as the first routing portion, and the fourth routing portion is set in the same direction as the second routing portion. At least part of the third routing portion is connected to the fourth routing portion. The length of the third routing portion increases along the direction from the lower frame to the upper frame, and the length of the fourth routing portion decreases along the left frame to the middle area of the display area.

7. The OLED display panel according to claim 6, wherein: One of the second routing portions adjacent to the second routing portions is cross-arranged with one of the third routing portions, and a distance exists between the other second routing portions adjacent to the second routing portions and the third routing portion.

8. The OLED display panel according to claim 6, wherein: One of the adjacent second routing portions is cross-arranged with one of the third routing portions, and along the direction from the left frame to the right frame, the other second routing portions in the adjacent second routing portions are correspondingly connected to the other third routing portions, and the third routing portions are disconnected from each other.

9. The OLED display panel according to claim 6, wherein: The invalid routing lines are arranged on the same layer as the fan-out routing lines, and the unit distribution density of the invalid routing lines is the same as the unit distribution density of the fan-out routing lines.

10. The OLED display panel according to claim 2, wherein: The sub-pixels include a red sub-pixel, a blue sub-pixel, and a green sub-pixel, and at least one of the invalid routing lines passing through the red sub-pixel, the invalid routing lines passing through the blue sub-pixel, and the invalid routing lines passing through the green sub-pixel is symmetrical about the center of the anode of the corresponding sub-pixel.

11. The OLED display panel according to claim 10, wherein: The red sub-pixel includes a first anode, the blue sub-pixel includes a second anode, the inactive wiring passing through the red sub-pixel is symmetrical about the center of the first anode, and the inactive wiring passing through the blue sub-pixel is symmetrical about the center of the second anode.

12. The OLED display panel according to claim 11, wherein: The green sub-pixel includes a third anode, and the invalid routing lines passing through the green sub-pixel are symmetrical about the center of the third anode, and along the direction from the lower frame toward the upper frame, the invalid routing lines passing through the green sub-pixel are symmetrical about the center line of the third anode.

13. The OLED display panel according to claim 12, wherein: Along the direction from the left border to the right border, at least a portion of the invalid routing that passes through the green sub-pixel of the adjacent column extends into the red sub-pixel, and / or at least a portion of the invalid routing that passes through the green sub-pixel of the adjacent column extends into the blue sub-pixel, and the invalid routing that extends into the red sub-pixel and / or the blue sub-pixel is disconnected from the invalid routing that passes through the red sub-pixel and the blue sub-pixel.

14. The OLED display panel according to claim 2, wherein: The OLED display panel includes a driving circuit layer, and the driving circuit layer includes a first source-drain electrode layer and a second source-drain electrode layer; The first source-drain layer includes the signal wiring, and the second source-drain layer includes the fan-out wiring and the invalid wiring.

15. The OLED display panel according to claim 2, wherein: The OLED display panel includes a driving circuit layer, which includes a first source-drain electrode layer, a second source-drain electrode layer, and a third source-drain electrode layer. The first source-drain electrode layer includes a source electrode and a drain electrode, the second source-drain electrode layer includes the signal line, and the third source-drain layer includes the fan-out line and the invalid line.

16. The OLED display panel according to claim 15, wherein: The OLED display panel also includes a first planarization layer and a second planarization layer, the first planarization layer is arranged between the first source and drain layer and the second source and drain layer, the second planarization layer is arranged between the second source and drain layer and the third source and drain layer, the signal routing includes a data line, and the fan-out routing passes through a via in the second planarization layer and is connected to the data line.

17. The OLED display panel according to claim 16, wherein: The OLED display panel further includes a power signal line, which is disposed on the second source and drain electrode layer. The inactive wiring passes through a via hole and is connected to the power signal line.

18. An OLED display device, characterized in that: Comprising the OLED display panel according to any one of claims 1 to 17.

Images