Detection circuit and detection method

Abstract

A detection method is used to detect a memory chip. The detection method includes the following steps: coupling a detection circuit to a first region and a second region of the memory chip, wherein the second region does not overlap with the first region; inputting a first detection signal from the detection circuit to the first region of the memory chip; burning memory cells of the detection circuit; and inputting a second detection signal from the detection circuit to the second region of the memory chip. The present application provides a detection circuit and a detection method, thereby saving the detection time and cost of detecting the memory chip, and avoiding the damage of the memory chip during detection.

Description

Technical Field

[0001] This invention relates to a detection circuit and method. More specifically, this invention relates to a detection circuit and method for detecting memory chips. Background Technology

[0002] In existing technologies, focused ion beam (FIB) circuit repair technology has been used in memory chips to understand leakage currents in multiple word lines or multiple bit lines. FIB circuit repair technology frequently employs focused ion beams to modify the logic circuitry or circuit connections of circuit chips or memory chips.

[0003] Because of the focused ion beam (FIB) circuit repair technique, multiple word lines or bit lines from the edge to the center of the memory chip are often burned out for electrical analysis. However, using a FIB can damage the circuit chip or memory chip. Therefore, technicians cannot determine where the leakage current originates within the circuit chip or memory chip.

[0004] Therefore, the above-mentioned technologies still have many shortcomings, and other suitable detection methods need to be developed by those skilled in the art. Summary of the Invention

[0005] One aspect of the present invention relates to a detection method. The detection method is used to detect a memory chip. The detection method includes the following steps: coupling a detection circuit to a first region and a second region of the memory chip, wherein the second region and the first region do not overlap; inputting a first detection signal from the detection circuit to the first region of the memory chip; burning out the memory cells of the detection circuit; and inputting a second detection signal from the detection circuit to the second region of the memory chip.

[0006] In some embodiments, the step of inputting a first detection signal from the detection circuit to a first region of the memory chip includes: determining whether the first region of the memory chip is normal; the step of inputting a second detection signal from the detection circuit to a second region of the memory chip includes: determining whether the second region of the memory chip is normal.

[0007] In some embodiments, the detection method further includes: turning on a switch of the detection circuit as a resistor, thereby transmitting a second detection signal to a second region of the memory chip according to a control signal.

[0008] In some embodiments, the detection method further includes removing the detection circuit from the memory chip during the manufacturing process.

[0009] In some embodiments, the memory chip further includes a plurality of word lines and a plurality of bit lines. The step of inputting a first detection signal from the detection circuit to a first region of the memory chip includes: inputting a plurality of detection signals to the plurality of word lines or the plurality of bit lines respectively.

[0010] In some embodiments, the step of inputting a first detection signal from the detection circuit to a first region of the memory chip includes: simultaneously inputting a plurality of detection signals to a plurality of word lines and a plurality of bit lines.

[0011] Another aspect of the present invention relates to a detection circuit. The detection circuit is used to detect a memory chip. The detection circuit includes an input board and a memory cell. The input board is coupled to a first region of the memory chip. The input board is used to input a first detection signal to the first region of the memory chip. The memory cell is coupled to the input board and a second region of the memory chip. The second region does not overlap with the first region. The memory cell is burned out so that the input board inputs a second detection signal to the second region of the memory chip.

[0012] In some embodiments, the detection circuit further includes a switch. The switch is turned on to act as a resistor, thereby transmitting a second detection signal to a second region of the memory chip according to a control signal.

[0013] In some embodiments, the memory chip includes a two-dimensional array memory and a three-dimensional memory. The memory chip includes a plurality of word lines and a plurality of bit lines. The plurality of word lines are perpendicular to the plurality of bit lines. The plurality of word lines and the plurality of bit lines form a grid matrix on the memory chip. The grid matrix includes a first portion and a second portion. The second portion surrounds the first portion. The second portion and the first portion do not overlap. The detection circuit includes a first detection circuit and a second detection circuit. The first detection circuit is coupled to the plurality of word lines. The second detection circuit is coupled to the plurality of bit lines.

[0014] In some embodiments, the detection circuit further includes a plurality of detection boards. The plurality of detection boards are used to transmit a plurality of detection results of the first detection signal and the second detection signal back to the input board. Attached Figure Description

[0015] The invention will be better understood by referring to the embodiments described in the following paragraphs and the accompanying drawings:

[0016] Figure 1 A circuit block diagram illustrating a memory chip and a detection circuit according to some embodiments of the present invention;

[0017] Figure 2 This is a schematic flowchart illustrating the steps of a detection method according to some embodiments of the present invention;

[0018] Figure 3This is a schematic diagram illustrating the circuit state of a memory chip and a detection circuit according to some embodiments of the present invention;

[0019] Figure 4 This is a schematic diagram illustrating the circuit state of a memory chip and a detection circuit according to some embodiments of the present invention;

[0020] Figure 5 A circuit block diagram illustrating a memory chip and a detection circuit according to some embodiments of the present invention;

[0021] Figure 6 A circuit block diagram illustrating a memory chip and a detection circuit according to some embodiments of the present invention; and

[0022] Figure 7 This is a circuit block diagram illustrating a memory chip and two detection circuits according to some embodiments of the present invention. Detailed Implementation

[0023] The spirit of the present invention will be clearly explained below with reference to the accompanying drawings and detailed description. Any person skilled in the art, after understanding the embodiments of the present invention, can make changes and modifications based on the techniques taught in the present invention without departing from the spirit and scope of the present invention.

[0024] The terminology used herein is for the purpose of describing specific embodiments only and is not intended to limit the invention. Singular forms such as “a,” “this,” “this,” “the,” and “the”, as used herein, also include plural forms.

[0025] The terms “include,” “including,” “have,” “contain,” etc., used in this article are all open-ended terms, meaning that they include but are not limited to.

[0026] Unless otherwise specified, the terms used herein generally have their ordinary meaning in the context of the art, the invention, and the specific content. Certain terms used to describe the invention will be discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art in describing the invention.

[0027] Figure 1 This is a circuit block diagram illustrating a memory chip 900 and a detection circuit 100 according to some embodiments of the present invention. In some embodiments, please refer to... Figure 1The memory chip 900 includes a plurality of word lines WL (all vertical lines in the figures represent word lines) and a plurality of bit lines BL (all horizontal lines in the figures represent bit lines). In some embodiments, the plurality of word lines are perpendicular to the plurality of bit lines. In some embodiments, the memory chip 900 includes a two-dimensional (2D) array memory and a three-dimensional (3D) memory. In some embodiments, the memory chip 9001 includes dynamic random access memory (DRAM).

[0028] In some embodiments, the detection circuit 100 includes an input board In1, a memory cell C1, and a switch T1. The input board In1 is coupled to the memory chip 900. Each element in the figures is considered to have a first end, measured from its top and right ends. The memory cell C1 includes a first end and a second end. The first end of the memory cell C1 is coupled to the memory chip 900. The second end of the memory cell C1 is coupled to the input board In1.

[0029] In some embodiments, switch T1 includes a first terminal, a second terminal, and a control terminal. The first terminal of switch T1 is coupled to ground GND. The second terminal of switch T1 is coupled to memory cell C1 and memory chip 900. The control terminal of switch T1 is coupled to gate control board G1. Switch T1 responds to control signals input to gate control board G1 to turn on or off. Switch T1 includes a P-type metal-oxide-semiconductor field-effect transistor (MOSFET) or an N-type metal-oxide-semiconductor field-effect transistor (MOSFET).

[0030] In some embodiments, a plurality of detection boards PADs are located between the detection circuit 100 and the memory chip 900. The plurality of detection boards PADs are used to transmit a plurality of unidirectional or bidirectional detection signals. In some embodiments, the plurality of detection boards PADs are coupled to the detection circuit 100 and the memory chip 900. The plurality of detection boards PADs are used to input a plurality of detection results to a plurality of detection result boards In1 that transmit the plurality of detection signals.

[0031] In some embodiments, for the purpose of making the present invention Figure 1 The detection circuit 100 is easy to understand; it is used to detect the memory chip 900. Please refer to the following: Figures 2 to 4 , Figure 2 This is a schematic flowchart illustrating the steps of a detection method 200 according to some embodiments of the present invention. Figure 3and Figure 4 This is a schematic diagram illustrating the circuit state of a memory chip 900 and a detection circuit 100 according to some embodiments of the present invention. It should be noted that... Figure 3 and Figure 4 An embodiment is a detection circuit 100 used to independently detect a plurality of word lines WL of the memory chip 900. Figure 3 The memory chip 900 shown corresponds to Figure 1 The memory chip 900. The detection method 200 is used to detect the memory chip. The detection method 200 includes the following steps:

[0032] In step 210, the detection circuit is coupled to the first and second regions of the memory chip.

[0033] In some embodiments, please refer to Figure 2 and Figure 3 The input board In1 of the detection circuit 100 is coupled to a first region A11 and a second region (e.g., region A12 and region A13) of the memory chip 900. The second region (e.g., region A12 and region A13) does not overlap with the first region A11. Specifically, the first region A11 is the central region of a plurality of word lines. Regions A12 and A13 are located on either side of the first region A11. It should be noted that the size and length of each region A11, region A12, and region A13 are not limited to the embodiments shown in the accompanying drawings.

[0034] In step 220, a first detection signal is input from the detection circuit to the first region of the memory chip.

[0035] In some embodiments, the input board In1 is used to transmit signals from the detection circuit 100 along the path shown in the figure. Figure 3 The path R1 shown inputs a first detection signal to the first region A11 of the memory chip 900. Multiple detection boards PADs transmit the first detection result of the first detection signal back to the input board In1. The input board In1 determines whether the first region A11 of the memory chip 900 is functioning correctly based on the first detection result of the first detection signal. Simultaneously, switch T1 responds to the control signal from the gate control board G1 to close.

[0036] In step 230, the memory cell of the detection circuit is burned out.

[0037] In some embodiments, please refer to Figure 2 and Figure 4 Memory cell C1 was burned out to create a short circuit, and the short circuit path is as follows: Figure 4The path R2 is shown. Simultaneously, switch T1 responds to the control of gate control board G1 to conduct, thereby acting as a resistor to allow signals from input board In1 to be transmitted to the second region (e.g., region A12 and region A13) of memory chip 900. It should be noted that the lightning bolt symbol in the attached diagram represents memory cell C1 being burned out and unable to be restored or repaired.

[0038] In step 240, a second detection signal is input from the detection circuit to the second region of the memory chip.

[0039] In some embodiments, please refer to Figure 2 and Figure 4 The input board In1 is used to input the signal from the detection circuit 100 along the input path. Figure 4 The path R2 shown inputs a second detection signal to the second region (e.g., region A12 and region A13) of the memory chip 900. Multiple detection boards PADs transmit the second detection results of the second detection signal back to the input board In1. The input board In1 is used to determine whether the second region (e.g., region A12 and region A13) of the memory chip 900 is normal based on the second detection results of the second detection signal.

[0040] In step 250, the detection circuit is removed from the memory chip.

[0041] In some embodiments, the detection circuit 100 is removed from the memory chip during the manufacturing process of the memory chip 900. More specifically, the detection circuit 100 is removed during the later-stage detection process of the manufacturing process of the memory chip 900.

[0042] Figure 5 This is a circuit block diagram illustrating a memory chip 900 and a detection circuit 100 according to some embodiments of the present invention. In some embodiments, compared to Figure 3 and Figure 4 , Figure 5 Implementation examples and Figure 3 and Figure 4 The difference in the embodiment lies in changing the connection relationship between the memory chip 900 and the detection circuit 100. Specifically, the detection circuit 100 is coupled to the first region A11 along path R2' and the detection circuit 100 is coupled to the second region (e.g., region A12 and region A13) along path R1'.

[0043] In some embodiments, the difference from step 220 described above is that the input board In1 of the detection circuit 100 is used to input a first detection signal from the detection circuit 100 along path R1' to the second region (e.g., region A12 and region A13). In some embodiments, another difference from step 220 described above is that the input board In1 of the detection circuit 100 is used to input a second detection signal from the detection circuit 100 along path R2' to the first region A11. The remaining steps are the same and have been described in the above steps, and will not be repeated here.

[0044] Figure 6 This is a circuit block diagram illustrating a memory chip 900 and a detection circuit 100 according to some embodiments of the present invention. Compared to Figure 3 and Figure 4 , Figure 6 In one embodiment, a detection circuit 100 is used to independently detect a plurality of bit lines BL of the memory chip 900. For example... Figure 6 The memory chip 900 shown corresponds to Figure 1 The memory chip 900 shown.

[0045] In some embodiments, please refer to Figure 6 ,like Figure 6 The input board In2 of the detection circuit 100 shown is coupled along path R3 to region A21 of the complex number of bit lines BL of the memory chip 900. For example... Figure 6 The input board In2 of the detection circuit 100 shown is coupled along path R4 to regions A22 and A23 of the plurality of bit lines BL of the memory chip 900. Specifically, region A21 is located in the central region of the plurality of bit lines BL. Regions A22 and A23 are located on either side of region A21. It should be noted that the dimensions and lengths of each region A21, A22, and A23 are not limited to the embodiments shown in the accompanying drawings.

[0046] Figure 7 This is a circuit block diagram illustrating a memory chip 900, a detection circuit 100A, and a detection circuit 100B according to some embodiments of the present invention. Figure 7 Implementation examples and Figure 3 , Figure 4 , Figure 5 and Figure 6 The difference in the embodiment lies in the change in the number of detection circuits. The detection circuit includes a first detection circuit 100A and a second detection circuit 100B. The first detection circuit 100A and the second detection circuit 100B are coupled to the memory chip 900. For example... Figure 7 The first detection circuit 100A and the second detection circuit 100B shown are the same as those described above. Figure 1 , Figure 3 and Figure 6 The detection circuits are all the same.

[0047] It should be noted that the first detection circuit 100A and the second detection circuit 100B simultaneously detect a plurality of word lines WL and a plurality of bit lines BL of the memory chip 900. Specifically, the first detection signal and the second detection signal are simultaneously input to the memory chip 900. The first detection signal and the second detection signal do not interfere with each other.

[0048] In some embodiments, such as Figure 7 As shown, a complex number of word lines WL and a complex number of bit lines BL form a grid matrix on the memory chip (e.g., as shown in the diagram). Figure 7 (The square matrix shown). The grid matrix contains 9 grids. The 9 grids are arranged from left to right and from top to bottom as follows: first grid P1, second grid P2, third grid P3, fourth grid P4, fifth grid P5, sixth grid P6, seventh grid P7, eighth grid P8, and ninth grid P9. In some embodiments, the grid matrix includes a first part (e.g., fifth grid P5) and a second part (e.g., grids P1 to P4 and grids P6 to P9). The second part surrounds the first part. The first part and the second part do not overlap.

[0049] In some embodiments, regions A12 of a plurality of word lines WL partially overlap with regions A22 of a plurality of bit lines BL to form a first grid P1. In some embodiments, regions A11 of a plurality of word lines WL partially overlap with regions A22 of a plurality of bit lines BL to form a second grid P2. In some embodiments, regions A13 of a plurality of word lines WL partially overlap with regions A22 of a plurality of bit lines BL to form a third grid P3.

[0050] In some embodiments, regions A12 of multiple word lines WL partially overlap with regions A21 of multiple bit lines BL to form a fourth grid P4. In some embodiments, regions A11 of multiple word lines WL partially overlap with regions A21 of multiple bit lines BL to form a fifth grid P5. In some embodiments, regions A13 of multiple word lines WL partially overlap with regions A21 of multiple bit lines BL to form a sixth grid P6.

[0051] In some embodiments, regions A12 of multiple word lines WL partially overlap with regions A23 of multiple bit lines BL to form a seventh grid P7. In some embodiments, regions A11 of multiple word lines WL partially overlap with regions A23 of multiple bit lines BL to form an eighth grid P8. In some embodiments, regions A13 of multiple word lines WL partially overlap with regions A23 of multiple bit lines BL to form a ninth grid P9.

[0052] In some embodiments, the circuit connection between the memory chip 900 and the first detection circuit 100A is designed according to actual requirements. The circuit connection between the memory chip 900 and the second detection circuit 100B is designed according to actual requirements.

[0053] In some embodiments, such as Figure 7 As shown, the first part is actually the central part of the memory chip 900, and the second part is actually the peripheral part of the memory chip 900. It should be noted that the shape and size of each central part and peripheral part are not limited to the embodiments shown in the drawings.

[0054] It should be noted that the detection circuit and detection method of the present invention are mainly used to detect the central portion and the peripheral portion of the memory chip 900, so as to determine whether each central portion and the peripheral portion of the memory chip 900 is normal. Furthermore, a plurality of word lines and a plurality of bit lines of the memory chip can be detected simultaneously, thereby saving the detection time of the memory chip.

[0055] According to the foregoing embodiments, the present invention provides a detection circuit and detection method, thereby saving detection time and cost of memory chips and avoiding damage to memory chips during detection.

[0056] While the present invention has been disclosed above with detailed embodiments, other possible embodiments are not excluded. Therefore, the scope of protection of the present invention should be determined by the appended claims, and not by the limitations of the foregoing embodiments.

[0057] For those skilled in the art, various modifications and refinements can be made to this invention without departing from its spirit and scope. Based on the foregoing embodiments, all modifications and refinements made to this invention are also covered within the protection scope of this invention.

[0058] [Symbol Explanation]

[0059] 100, 100A, 100B: Detection circuit

[0060] T1, T2: Switches

[0061] C1, C2: Memory cells

[0062] G1, G2: Gate control board

[0063] In1, In2: Input boards

[0064] GND: Ground terminal

[0065] PAD: Detection plate

[0066] 900: Memory chip

[0067] BL: Bitline

[0068] WL: Wordline

[0069] A11~A13, A21~A23: Area

[0070] P1~P9: Grid

[0071] R1~R4, R1'~R2': Path

[0072] 200: Method

[0073] 210-250: Steps.

Claims

1. A detection method, characterized in that, Used for testing memory chips, including: The detection circuit is coupled to a first region and a second region of the memory chip, wherein the second region does not overlap with the first region; A first detection signal is input from the detection circuit to the first region of the memory chip; The memory cell of the detection circuit was burned out; as well as A second detection signal is input from the detection circuit to the second region of the memory chip.

2. The detection method according to claim 1, characterized in that, The step of inputting the first detection signal from the detection circuit to the first region of the memory chip includes: Determine whether the first region of the memory chip is normal; The step of inputting the second detection signal from the detection circuit to the second region of the memory chip includes: Determine whether the second region of the memory chip is normal.

3. The detection method according to claim 1, characterized in that, Also includes: The switch of the detection circuit is turned on as a resistor, thereby transmitting the second detection signal to the second area of ​​the memory chip according to the control signal.

4. The detection method according to claim 1, characterized in that, Also includes: The detection circuit is removed from the memory chip during the manufacturing process.

5. The detection method according to claim 1, characterized in that, The memory chip also includes a plurality of word lines and a plurality of bit lines, wherein the step of inputting the first detection signal from the detection circuit to the first region of the memory chip includes: Input multiple detection signals to the word lines or bit lines respectively.

6. The detection method according to claim 5, characterized in that, The step of inputting the first detection signal from the detection circuit to the first region of the memory chip includes: Simultaneously input these detection signals to these word lines and these bit lines.

7. A detection circuit, characterized in that, The detection circuit, used to detect memory chips, includes: An input board is coupled to a first region of the memory chip, wherein the input board is used to input a first detection signal to the first region of the memory chip; as well as A memory cell is coupled to a second region of the input board and the memory chip, wherein the second region does not overlap with the first region, and wherein the memory cell is burned out so that a second detection signal input from the input board can be transmitted to the second region of the memory chip.

8. The detection circuit according to claim 7, characterized in that, Also includes: A switch, wherein the switch is turned on to act as a resistor, thereby transmitting the second detection signal to the second region of the memory chip according to a control signal.

9. The detection circuit according to claim 8, characterized in that, The memory chip includes a two-dimensional array memory and a three-dimensional memory. The memory chip includes a plurality of word lines and a plurality of bit lines. The word lines are perpendicular to the bit lines. The word lines and bit lines form a grid matrix in the memory chip. The grid matrix includes a first part and a second part. The second part surrounds the first part and the second part does not overlap with the first part. The detection circuit includes a first detection circuit and a second detection circuit. The first detection circuit is coupled to the word lines, and the second detection circuit is coupled to the bit lines.

10. The detection circuit according to claim 7, characterized in that, Also includes: A plurality of detection boards, wherein the detection boards are used to transmit the first detection signal and a plurality of detection results of the second detection signal back to the input board.

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