Timing control method and circuit, adapter card, and computing device

Abstract

A timing control method and circuit, an adapter card, and a computing device. The method includes: switching from a shutdown state to a standby state, powering a PCIe card and providing a first clock signal and a first reset / de-reset signal, so that the PCIe card operates based on the first clock signal and the first reset / de-reset signal; switching from a standby state to a power-on state, providing a second clock signal and a second reset / de-reset signal based on a second clock signal and a second reset / de-reset signal sent by a motherboard, so that the PCIe card operates based on the second clock signal and the second reset / de-reset signal; switching from a power-on state to a standby state, reverting to providing the first clock signal and the first reset / de-reset signal, so that the PCIe card operates based on the first clock signal and the first reset / de-reset signal. This method enables the PCIe card to operate in the standby state, allowing the computing device to quickly scan the PCIe card when the computer is powered on, avoiding failure to recognize the PCIe card.

Description

Technical Field

[0001] The present application relates to the field of circuit technology, and in particular to a timing control method and circuit, an adapter card, and a computing device. Background Art

[0002] With the rapid development of technology, the performance and functionality of computing devices such as servers are constantly improving, and server configurations are becoming increasingly complex. For example, servers have a large number of PCIe slots, allowing users to freely configure various external cards, or PCIe cards, such as RAID cards (redundant array of independent disks, or RAID), network cards, and GPU cards (graphic processing units, or GPUs).

[0003] As the performance and functions of PCIe cards are constantly improving, the startup speed of PCIe cards is slow during the boot process, and there is a problem that the BIOS cannot scan and recognize the PCIe card. Summary of the Invention

[0004] The embodiments of the present application provide a timing control method and circuit, an adapter card, and a computing device. The timing control method enables a PCIe card to operate in a standby state, so that the computing device can quickly scan the PCIe card during the startup process to avoid failure to recognize the PCIe card.

[0005] In a first aspect, an embodiment of the present application provides a timing control method, which includes: when switching from a power-off state to a standby state, powering a PCIe card and providing a first clock signal and a first reset / de-reset signal, so that the PCIe card operates based on the first clock signal and the first reset / de-reset signal; when switching from the standby state to the power-on state, providing the second clock signal according to the second clock signal sent by the mainboard, and providing the second reset / de-reset signal according to the second reset / de-reset signal sent by the mainboard, so that the PCIe card operates based on the second clock signal and the second reset / de-reset signal; when switching from the power-on state to the standby state, stopping receiving the second clock signal and the second reset / de-reset signal sent by the mainboard, and resuming to providing the first clock signal and the first reset / de-reset signal, so that the PCIe card operates based on the first clock signal and the first reset / de-reset signal.

[0006] That is, in standby mode, the PCIe card can operate based on the first clock signal and the first reset / de-reset signal, and in power-on mode, the PCIe card can operate based on the second clock signal and the second reset / de-reset signal. This allows the PCIe card to be provided with the required clock signal and reset / de-reset signal during the switching process between standby and power-on modes, i.e., switching from standby to power-on mode or vice versa, ensuring that the PCIe card does not generate alarms or malfunction, allowing the PCIe card to operate in standby mode. For example, the PCIe card operating system and configuration files can be pre-loaded, allowing the computing device to quickly scan the PCIe card during the power-on process to avoid failure to recognize the PCIe card.

[0007] In one possible implementation, the method of powering the PCIe card and providing a first clock signal and a first reset / de-reset signal includes: providing a power signal to the PCIe card, and providing the first clock signal to the PCIe card after the power signal has been stable for a period of time; providing the first reset / de-reset signal after the first clock signal has been maintained for a period of time; and / or, the method of timing control further includes: when switching from the standby state to the shutdown state, first stopping providing the first reset / de-reset signal, stopping providing the first clock signal after a first set time interval, and stopping providing the power signal after a second set time interval, wherein the second set time interval is greater than the first set time. That is, in this implementation, when switching from the shutdown state to the standby state, the power signal, the first clock signal, and the first reset / de-reset signal may be provided in sequence, and when switching from the standby state to the shutdown state, the first reset / de-reset signal, the first clock signal, and the power signal may be stopped in sequence, thereby ensuring that the PCIe card can operate and stop operating safely and reliably.

[0008] In one possible implementation, providing the second clock signal based on the second clock signal sent by the motherboard includes: receiving the second clock signal sent by the motherboard, adjusting the first clock signal to the second clock signal based on the second clock signal, and then providing the second clock signal to the PCIe card; or receiving the second clock signal sent by the motherboard, and switching the clock signal provided to the PCIe card from the first clock signal to the second clock signal sent by the motherboard. That is, in this implementation, the second clock signal can be provided by the motherboard when the computer is powered on, or the first clock signal provided in standby mode can be adjusted to the second clock signal when the computer is powered on, and the first clock signal can be generated by an oscillator.

[0009] In one possible implementation, the timing control method further includes: receiving a fault signal sent by the PCIe card, the fault signal being used to indicate whether the PCIe card has failed and requires a reset / de-reset operation; causing the PCIe card to operate based on the first clock signal and the first reset / de-reset signal, including: performing a logical operation on the first reset / de-reset signal and the fault signal to obtain a reset / de-reset signal, causing the PCIe card to operate based on the first clock signal and the reset / de-reset signal; and / or causing the PCIe card to operate based on the second clock signal and the second reset / de-reset signal, including: performing a logical operation on the second reset / de-reset signal and the fault signal to obtain a reset / de-reset signal, causing the PCIe card to operate based on the second clock signal and the reset / de-reset signal. That is, in this implementation, since the PCIe card may fail, the PCIe card may be reset and de-reset when a failure occurs. Therefore, the reset / de-reset signal provided to the PCIe card in the standby state and / or the power-on state may also be affected by whether the PCIe card has failed.

[0010] In a second aspect, an embodiment of the present application provides a timing control circuit, which includes: an oscillator for outputting a first clock signal; a clock circuit for receiving the first clock signal and receiving a second clock signal sent by the mainboard in the power-on state; a control circuit and a logic circuit, wherein the control circuit is used to send a first reset / de-reset signal to the first input end of the logic circuit, and the second input end of the logic circuit is used to receive the second reset / de-reset signal sent by the mainboard in the power-on state; wherein, in the standby state, the clock circuit is used to output the first clock signal to the PCIe card, and the logic circuit is used to output the reset / de-reset signal to the PCIe card based on the first reset / de-reset signal; in the power-on state, the clock circuit is used to output the second clock signal to the PCIe card, and the logic circuit is used to output the reset / de-reset signal to the PCIe card based on the second reset / de-reset signal.

[0011] Since in the standby state, the clock circuit can output a first clock signal to the PCIe card, and the logic circuit can output a reset / de-reset signal to the PCIe card based on the first reset / de-reset signal; in the power-on state, the clock circuit can output a second clock signal to the PCIe card, and the logic circuit can output a reset / de-reset signal to the PCIe card based on the second reset / de-reset signal. In this way, during the switching process between the standby state and the power-on state, the timing control circuit can provide the PCIe card with a clock signal and reset / de-reset signal that meet the requirements, respectively, to ensure that the PCIe card does not generate an alarm or malfunction. The timing control circuit enables the PCIe card to operate in the standby state, for example, loading the PCIe card operating system and configuration file in advance, thereby ensuring that the computing device can scan the PCIe card quickly during the power-on process to avoid failure to recognize the PCIe card.

[0012] In one possible implementation, in the power-on state, the clock circuit is configured to switch from outputting the first clock signal to outputting the second clock signal; or, in the power-on state, the clock circuit is configured to adjust the first clock signal to the second clock signal based on the second clock signal and then output the second clock signal. That is, in this implementation, the second clock signal output by the clock circuit in the power-on state may be provided by the motherboard or obtained by adjusting the first clock signal provided by the oscillator.

[0013] In one possible implementation, the control circuit is configured to output the first reset / de-reset signal after determining receipt of a first message output by the clock circuit, the first message being used to indicate that the clock circuit is capable of outputting a stable first clock signal or second clock signal; and / or the control circuit is configured to send a control signal to the clock circuit, the control signal being used to determine a start time for the clock circuit to send the first clock signal to the PCIe card. That is, in this implementation, the control circuit begins providing the first reset / de-reset signal only after determining that the clock circuit is capable of sending a stable clock signal to the PCIe card; and the control circuit is also configured to determine a start time for the clock circuit to send the first clock signal to the PCIe card.

[0014] In one possible implementation, the logic circuit includes an AND gate, wherein a first input of the AND gate is connected to an output of the control circuit to receive the first reset / de-reset signal, a second input of the AND gate is connected to the motherboard to receive the second reset / de-reset signal sent by the motherboard, and an output of the AND gate is used to output the reset / de-reset signal to the PCIe card. In other words, in this implementation, the logic circuit can function using the AND gate, enabling the provision of a satisfactory reset / de-reset signal to the PCIe card in both the standby and power-on states.

[0015] In one possible implementation, the timing control circuit further includes: a pull-down circuit connected to the first input of the AND gate and configured to pull down the first input of the AND gate to a logic low level when the control circuit does not output the first reset / de-reset signal; and / or a first pull-up circuit connected to the second input of the AND gate and configured to pull up the second input of the AND gate to a logic high level when the second reset / de-reset signal is not received. That is, in this implementation, in order to cause the AND gate to output a logic low level in the initial stage of the standby state (when the control circuit has not yet output the first reset / de-reset signal), a pull-down circuit may be provided to pull down the first input of the AND gate; and in order to cause the AND gate to output a reset / de-reset signal to the PCIe card based on the first reset / de-reset signal in the later stage of the standby state (when the control circuit has begun outputting the first reset / de-reset signal), a pull-up circuit may be provided to pull up the second input of the AND gate to ensure that the reset / de-reset signal outputted by the output of the AND gate is not affected by the input signal at the second input.

[0016] In one possible implementation, in the standby state, the logic circuit is configured to output the first reset / de-reset signal to the PCIe card; in the power-on state, the logic circuit is configured to output the second reset / de-reset signal to the PCIe card. That is, in this implementation, if an AND gate includes only two input terminals, the reset / de-reset signal output by the output terminal of the AND gate may be consistent with the first reset / de-reset signal input to the first input terminal in the standby state, and may be consistent with the second reset / de-reset signal input to the second input terminal in the power-on state.

[0017] In one possible implementation, the logic circuit is further configured to receive a fault signal sent by the PCIe card, or the logic circuit is further configured to receive a fault signal output by the control circuit after determining whether a reset / de-reset operation is required based on at least one first fault signal sent by the PCIe card, the fault signal being configured to indicate whether the PCIe card has failed and requires a reset / de-reset operation. In a standby state, the logic circuit is configured to output the reset / de-reset signal to the PCIe card based on the first reset / de-reset signal and the fault signal; and in a power-on state, the logic circuit is configured to output the reset / de-reset signal to the PCIe card based on the second reset / de-reset signal and the fault signal. That is, in this implementation, since a PCIe card may fail, and a reset / de-reset operation may be performed on the PCIe card when a failure occurs, the reset / de-reset signal output by the logic circuit to the PCIe card in the standby state and / or power-on state may also be affected by whether the PCIe card has failed.

[0018] In one possible implementation, the AND gate of the logic circuit further includes a third input terminal configured to receive the fault signal, and the timing control circuit further includes a second pull-up circuit connected to the third input terminal of the AND gate and configured to pull the third input terminal of the AND gate to a logic high level when the fault signal is not received. In other words, in this implementation, the AND gate allows the reset / de-reset signal output by the logic circuit to the PCIe card to be determined based on the first reset / de-reset signal and the fault signal in the standby state, and based on the second reset / de-reset signal and the fault signal in the power-on state.

[0019] In one possible implementation, the timing control circuit further includes a power supply circuit, which includes a switch device, one end of which is connected to the power supply terminal of the PCIe card and the other end of which is connected to the power supply terminal of the motherboard. The control circuit is further configured to control the switch device to conduct in the standby state and the power-on state to provide power to the PCIe card. In other words, in this implementation, the control circuit can control the start time of power supply to the PCIe card to ensure that the PCIe card can operate even in the standby state.

[0020] In a third aspect, an embodiment of the present application provides an adapter card, which includes: a circuit board having gold fingers, which are used to be inserted into a slot on a mainboard; and the timing control circuit provided in the second aspect above, which is arranged on the circuit board.

[0021] In a fourth aspect, an embodiment of the present application provides a computing device, comprising: a mainboard, wherein a slot is provided on the mainboard, and the adapter card provided in the third aspect, wherein the gold finger of the adapter card is inserted into the slot; a PCIe card, installed on the adapter card, wherein the mainboard is used to provide a second clock signal and a second reset / de-reset signal to the timing control circuit of the adapter card in a power-on state; in a standby state, the timing control circuit outputs a first clock signal and a reset / de-reset signal based on the first reset / de-reset signal to the PCIe card; in the power-on state, the timing control circuit outputs the second clock signal and outputs the reset / de-reset signal to the PCIe card based on the second reset / de-reset signal.

[0022] Other features and advantages of the present invention will be described in detail in the following specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The following is a brief introduction to the drawings required for describing the embodiments or prior art.

[0024] Figure 1AA flowchart of a timing control method provided in an embodiment of the present application;

[0025] Figure 1B This is a timing diagram of the power supply signal, clock signal, and reset / de-reset signal provided to a PCIe card according to the timing control method of an embodiment of the present application;

[0026] Figure 2 A schematic structural diagram of a timing control circuit provided in the first embodiment of the present application;

[0027] Figure 3 A schematic structural diagram of a timing control circuit provided in the second embodiment of the present application. DETAILED DESCRIPTION

[0028] In order to better understand the present application, various aspects of the present application will be described in more detail with reference to the examples. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application and are not intended to limit the scope of the present application in any way.

[0029] It should be noted that in this specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items; in addition, the expressions "first," "second," "third," etc. are only used to distinguish one feature from another, and do not represent any limitation on the features.

[0030] The following is a detailed introduction to the abbreviations and key terms used in the embodiments of this application:

[0031] S5 power status: Standby state, all computer system power supplies are powered off, and the mainboard BMC system remains powered on.

[0032] S0 power status (S0 powerstatus): that is, the power-on state, the computer system power is fully powered on, and the system is running normally.

[0033] Clock phase lock: A clock phase control technique that adjusts and maintains the target clock at the same frequency as the reference clock.

[0034] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0035] To expand server functionality, servers are equipped with a large number of PCIe slots, allowing users to freely configure various add-in cards, or PCIe cards, such as RAID cards (redundant array of independent disks, or simply disk arrays), network cards, and GPU cards (graphic processing units, or GPUs). As the performance and functionality of PCIe cards continue to improve, PCIe card startup speeds can slow during the computer's startup process, leading to issues with the BIOS failing to recognize the PCIe card.

[0036] In view of this, the embodiments of the present application provide a timing control method and circuit, an adapter card, and a computing device, which can provide the PCIe card with a clock signal and a reset / de-reset signal that meet the requirements during the switching process between the standby state and the power-on state, thereby ensuring that the PCIe card does not generate an alarm or malfunction. In this way, the PCIe card can operate in the standby state, so that the computing device such as the server can scan the PCIe card more quickly during the power-on process to avoid the failure to recognize the PCIe card.

[0037] Figure 1A A flowchart of a timing control method provided in an embodiment of the present application. Figure 1B The timing diagram of the power supply signal, clock signal and reset / de-reset signal provided to the PCIe card according to the timing control method of the embodiment of the present application is shown in FIG. Figure 1A and Figure 1B As shown, the timing control method includes the following steps:

[0038] S101 , when switching from the shutdown state AC_OFF to the standby state S5 , powering the PCIe card and providing a first clock signal and a first reset / de-reset signal, so that the PCIe card operates based on the first clock signal and the first reset / de-reset signal.

[0039] like Figure 1B As shown, powering the PCIe card and providing the first clock signal and the first reset / de-reset signal may include: providing the PCIe card with a power signal Card_PWR, and after the power signal Card_PWR is stable for a period of time, providing the PCIe card with the first clock signal; after the first clock signal continues for a period of time, providing the first reset / de-reset signal. The first clock signal and the first reset / de-reset signal may be Figure 1B The first S5 state clock signal Card_CLK and reset / de-reset signal / Card_PERST.

[0040] S102, when switching from the standby state S5 to the power-on state S0, provides a second clock signal according to the second clock signal sent by the mainboard, and provides a second reset / de-reset signal according to the second reset / de-reset signal sent by the mainboard, so that the PCIe card runs based on the second clock signal and the second reset / de-reset signal.

[0041] The second clock signal and the second reset / de-reset signal may be the clock signal Card_CLK and the reset / de-reset signal / Card_PERST in the S0 state. Furthermore, providing the second clock signal based on the second clock signal sent by the motherboard may include but is not limited to the following two schemes:

[0042] Solution 1: Receive the second clock signal sent by the motherboard, adjust the first clock signal to the second clock signal according to the second clock signal, and then provide it to the PCIe card.

[0043] Solution 2: Receive the second clock signal sent by the motherboard, and switch the clock signal provided to the PCIe card from the first clock signal to the second clock signal sent by the motherboard.

[0044] That is, in the power-on state S0 , the second clock signal may be provided by the mainboard, or the first clock signal provided in the standby state S5 may be adjusted to the second clock signal, and the first clock signal may be generated by an oscillator.

[0045] S103, when switching from the power-on state S0 to the standby state S5, stops receiving the second clock signal and the second reset / de-reset signal sent by the mainboard, and returns to providing the first clock signal and the first reset / de-reset signal, so that the PCIe card runs based on the first clock signal and the first reset / de-reset signal.

[0046] The first clock signal and the first reset / de-reset signal can be Figure 1B The clock signal Card_CLK and reset / de-reset signal / Card_PERST of the second S5 state.

[0047] That is, in the standby state S5, the PCIe card can operate based on the first clock signal and the first reset / de-reset signal, and in the power-on state S0, the PCIe card can operate based on the second clock signal and the second reset / de-reset signal. Thus, during the switching process between the standby state S5 and the power-on state S0, i.e., switching from the standby state S5 to the power-on state S0 or vice versa, the PCIe card can be provided with a clock signal and reset / de-reset signal that meet the requirements, ensuring that the PCIe card does not generate an alarm or malfunction, and that the PCIe card can operate in the standby state S5. For example, the PCIe card operating system and configuration file can be pre-loaded, so that the computing device can quickly scan the PCIe card during the power-on process to avoid failure to recognize the PCIe card.

[0048] S104, when switching from the standby state S5 to the shutdown state AC_OFF, first stop providing the first reset / de-reset signal, stop providing the first clock signal after a first set time, and stop providing the power supply signal Card_PWR after a second set time, where the second set time is greater than the first set time.

[0049] That is to say, if Figure 1B As shown, from the shutdown state AC_OFF to the standby state S5, the power supply signal Card_PWR, the first clock signal and the first reset / de-reset signal can be provided in sequence, and from the standby state S5 to the shutdown state AC_OFF, the first reset / de-reset signal, the first clock signal and the power supply signal Card_PWR can be stopped in sequence, thereby ensuring that the PCIe card can run and stop running safely and reliably.

[0050] Specifically, Figure 1B The timing diagram in may include the following five stages:

[0051] 1. First stage AC_OFF: When the server is not powered on, the server does not receive the power supply signal Card_PWR, clock signal Card_CLK, reset / release reset signal / Card_PERST, and Card_PWR, Card_CLK, and Card_PERST are all low.

[0052] 2. The second stage (S5 power supply state / standby state): When the server is plugged into the power supply, the server system enters the S5 power supply state and supplies power to the PCIe card. At this time, Card_PWR first becomes a high level. After the PCIe card power supply is stable, the server provides a clock signal to the PCIe card. After the clock signal is stable, the server provides a reset signal to the PCIe card ( / Card_PERST is pulled high). At this time, the PCIe card can work normally in the S5 power supply state.

[0053] 3. The third stage (S0 power supply state / power-on state): When the server is powered on, the server system enters the S0 power supply state, the PCIe card remains powered, the clock signal Card_CLK received by the PCIe card is synchronized with the PCIe clock in the S0 state, and the reset / de-reset signal / Card_PERST received by the PCIe card is synchronized with the reset / de-reset signal / Card_PERST in the S0 state.

[0054] 4. The fourth stage (S5 power supply state / standby state): When the server is shut down, the server system returns to the S5 power supply state, the PCIe card remains powered, and the clock signal Card_CLK and reset / de-reset signal / Card_PERST received by the PCIe card are restored to the clock signal Card_CLK and reset / de-reset signal / Card_PERST of the S5 state, and the PCIe card remains working.

[0055] 5. Fifth stage AC_OFF: When the server is unplugged from the power supply, the entire server is powered off, and the power supply, clock, and / PERST synchronization are terminated.

[0056] Furthermore, because PCIe cards may fail, and in the event of a failure, they may be reset or de-reset. Therefore, the reset / de-reset signal provided to the PCIe card in the standby state S5 and / or the power-on state S0 may be affected by whether the PCIe card has failed. Therefore, the timing control method may further include receiving a fault signal sent by the PCIe card, where the fault signal indicates whether the PCIe card has failed and requires a reset / de-reset operation.

[0057] In some examples, causing the PCIe card to operate based on the first clock signal and the first reset / de-reset signal may include: obtaining a reset / de-reset signal after performing a logic operation on the first reset / de-reset signal and a fault signal, and causing the PCIe card to operate based on the first clock signal and the reset / de-reset signal.

[0058] In other examples, causing the PCIe card to operate based on the second clock signal and the second reset / de-reset signal may include: obtaining a reset / de-reset signal after performing a logical operation on the second reset / de-reset signal and a fault signal, and causing the PCIe card to operate based on the second clock signal and the reset / de-reset signal.

[0059] Figure 2 This is a schematic diagram of the structure of a timing control circuit provided in the first embodiment of the present application. Figure 2As shown, the timing control circuit includes an oscillator, a clock circuit, a control circuit, and a logic circuit 10. The oscillator is configured to output a first clock signal CLK1. The clock circuit is configured to receive the first clock signal CLK1 and, when powered on, a second clock signal CLK2 sent by the motherboard. The control circuit is configured to send a first reset / release reset signal S5_PERST to a first input terminal of the logic circuit 10. A second input terminal of the logic circuit 10 is configured to receive a second reset / release reset signal S0_PERST sent by the motherboard when powered on.

[0060] In the standby state, ie, the S5 power supply state, the clock circuit is used to output the first clock signal CLK1 to the PCIe card, and the logic circuit 10 is used to output the reset / release reset signal Card_PERST to the PCIe card based on the first reset / release reset signal S5_PERST.

[0061] In the power-on state, ie, the S0 power supply state, the clock circuit is used to output the second clock signal CLK2 to the PCIe card, and the logic circuit 10 is used to output the reset / release reset signal Card_PERST to the PCIe card based on the second reset / release reset signal S0_PERST.

[0062] That is, the clock signal Card_CLK output by the clock circuit to the PCIe card in standby mode is the first clock signal CLK1, and the clock signal Card_CLK output to the PCIe card in power-on mode is the second clock signal CLK2. Furthermore, in power-on mode, the clock circuit can be configured to switch from outputting the first clock signal CLK1 to outputting the second clock signal CLK2; alternatively, the clock circuit can be configured to adjust the first clock signal CLK1 to the second clock signal CLK2 based on the second clock signal CLK2 before outputting the second clock signal. In other words, the second clock signal CLK2 output by the clock circuit in power-on mode can be provided by the motherboard or obtained by adjusting the first clock signal CLK1 provided by an oscillator.

[0063] Since in the standby state, the clock circuit can output the first clock signal CLK1 to the PCIe card, and the logic circuit 10 can output the reset / de-reset signal to the PCIe card based on the first reset / de-reset signal S5_PERST; in the power-on state, the clock circuit can output the second clock signal CLK2 to the PCIe card, and the logic circuit 10 can output the reset / de-reset signal to the PCIe card based on the second reset / de-reset signal S0_PERST. In this way, during the switching process between the standby state and the power-on state, the timing control circuit can provide the PCIe card with a clock signal and reset / de-reset signal that meet the requirements, ensuring that the PCIe card does not generate an alarm or malfunction, thereby enabling the PCIe card to operate in the standby state. In this way, during the power-on process, the computing device can scan the PCIe card more quickly to avoid failing to recognize the PCIe card.

[0064] In addition, in the standby state, in order to ensure that the PCIe card can operate, it is also necessary to power the PCIe card. Therefore, the timing control circuit may also include a power supply circuit. For example, Figure 2 As shown, the power supply circuit may include a switch device S, one end of which is connected to the power supply terminal of the PCIe card and the other end is used to connect to the power supply terminal of the motherboard. The control circuit is also used to control the switch device S to conduct in the standby state and the power-on state to provide power to the PCIe card. In the power-off state, the control circuit can also control the switch device S to disconnect to stop powering the PCIe card. In addition, for ease of installation, the switch device S can be integrated with other components of the timing control circuit on a circuit board to form an adapter card. If necessary, the switch device S can also be integrated on the motherboard.

[0065] That is to say, the timing control circuit of the embodiment of the present application can ensure that when the server switches between the S5 power supply state (i.e., standby state) and the S0 power supply state (i.e., power-on state), the timing control of the PCIe card power supply, PCIe clock, and / Card_PERST (reset / de-reset signal) meets the standard PCIe timing requirements, so that the PCIe card can work normally.

[0066] Continue to refer Figure 2 In order to start providing the first reset / de-reset signal S5_PERST only after determining that the clock circuit is capable of sending a stable clock signal to the PCIe card, the control circuit can be configured to output the first reset / de-reset signal S5_PERST after determining that a first message output by the clock circuit is received, where the first message is used to indicate that the clock circuit is capable of outputting a stable first clock signal CLK1 or second clock signal CLK2.

[0067] In addition, the control circuit can be configured to send a control signal to the clock circuit. The control signal is configured to determine when the clock circuit starts sending the first clock signal CLK1 to the PCIe card. Specifically, the control circuit can also determine when to send the first clock signal to the PCIe card. For example, the control circuit sends the control signal to the clock circuit when the PCIe card has access to a stable power supply.

[0068] In one example, logic circuit 10 may include an AND gate. A first input of the AND gate is connected to the output of the control circuit to receive a first reset / de-reset signal S5_PERST. A second input of the AND gate is connected to the motherboard to receive a second reset / de-reset signal S0_PERST from the motherboard. The output of the AND gate is used to output a reset / de-reset signal Card_PERST to the PCIe card. In other words, the functions of logic circuit 10 can be implemented using the AND gate, enabling the provision of a satisfactory reset / de-reset signal to the PCIe card in both the standby and power-on states.

[0069] Furthermore, the timing control circuit may further include a pull-down circuit 20. The pull-down circuit 20 is connected to the first input terminal of the AND gate and is used to pull down the first input terminal of the AND gate to a logic low level when the control circuit does not output the first reset / release reset signal S5_PERST. For example, Figure 2 As shown, the pull-down circuit 20 may include a pull-down resistor, one end of which is grounded, and the other end of which is connected to the first input of the AND gate. The timing control circuit may further include a first pull-up circuit 30, which is connected to the second input of the AND gate and is used to pull up the second input of the AND gate to a logic high level when the second reset / release reset signal S0_PERST is not received. For example, Figure 2 As shown, the first pull-up circuit 30 includes a pull-up resistor, one end of which is connected to the second input end of the AND gate, and the other end of which is connected to a high level, such as a 3.3V voltage.

[0070] That is, in the initial stage of the standby state, the control circuit has not yet output the first reset / release reset signal S5_PERST. In order to make the AND gate output a logic low level (i.e., the above-mentioned Figure 1B In order to detect the low level portion of Card_PERST in the first S5 stage of the standby state, a pull-down circuit 20 may be provided to pull down the first input terminal of the AND gate; and, in order to enable the AND gate to output a reset / de-reset signal to the PCIe card based on the first reset / de-reset signal S5_PERST in the later stage of the standby state (at this time, the control circuit has started to output a de-reset signal), a first pull-up circuit 30 may be provided to pull up the second input terminal of the AND gate, so that the output result of the output terminal of the AND gate in the standby state will not be affected by the second input terminal.

[0071] In addition, in some cases, such as Figure 2 As shown, in the standby state, the logic circuit 10 can be used to output a first reset / release reset signal S5_PERST to the PCIe card; in the power-on state, the logic circuit 10 can be used to output a second reset / release reset signal S0_PERST to the PCIe card. In other words, if the AND gate includes only two input terminals, the reset / release reset signal output by the output terminal of the AND gate can be consistent with the first reset / release reset signal S5_PERST input to the first input terminal in the standby state, and can be consistent with the second reset / release reset signal S0_PERST input to the second input terminal in the power-on state.

[0072] Specifically, in Figure 2 In the embodiment of the present application, the circuit control logic of the timing control circuit may be as follows:

[0073] When the server is plugged into the power supply, the server enters the S5 power supply state, that is, the standby state. The control circuit outputs the signal Clock_EN to enable the clock circuit. The clock circuit outputs the first clock signal CLK1, such as the 100M clock (provided by the crystal oscillator) to the PCIe card, that is, Card_CLK is CLK1 at this time. In addition, after the clock circuit outputs the stable first clock signal CLK1, it sends a first message to the control circuit or the control circuit detects that the 100M clock is delayed for a period of time. The control circuit outputs the first reset / de-reset signal S5_PERST to the logic circuit 10, such as the AND gate circuit, and controls the AND gate circuit to output / Card_PERST for de-reset.

[0074] When the server is powered on, the server system enters the S0 power supply state. The motherboard sends a second clock signal CLK2, such as a 100M clock, to the clock circuit. The clock circuit locks the phase of the S0 state clock and outputs the clock synchronized with the S0 state, namely the second reset / de-reset signal S0_PERST to the AND gate circuit, which takes over the control of the PCIe card reset / de-reset.

[0075] When the server is shut down and in standby mode, the clock circuit continuously outputs a 100M clock (provided by the crystal oscillator) to the PCIe card. The control circuit outputs the first reset / de-reset signal S5_PERST to the AND gate circuit, taking over the reset and de-reset signal Card_PERST output by the control logic circuit to the PCIe card.

[0076] Figure 3 This is a schematic diagram of the structure of a timing control circuit provided in the second embodiment of the present application. Figure 3 As shown, Figure 2 The difference between the timing control circuit shown is that Figure 3 In the embodiment, the logic circuit 10 is further configured to receive a fault signal Card_Fault sent by the PCIe card, or the logic circuit 10 is further configured to receive a fault signal Card_Fault output by the control circuit after determining whether a reset / de-reset operation is required based on at least one first fault signal sent by the PCIe card. The fault signal Card_Fault is used to indicate whether a PCIe card fault has occurred and requires a reset / de-reset operation. In other examples, a reset / de-reset operation is performed whenever a PCIe card fault occurs. In this case, the logic circuit 10 can directly receive the fault signal Card_Fault sent by the PCIe card. In other examples, after a PCIe card fault occurs, the fault is first reported to the control circuit. The control circuit determines whether the fault requires a reset / de-reset operation. If the determination result is yes, the control circuit transmits the fault signal Card_Fault to the AND gate circuit. If the determination result is no, the control circuit does not transmit the fault signal to the AND gate circuit.

[0077] In which, in the standby state, the logic circuit 10 can be used to output the reset / de-reset signal Card_PERST to the PCIe card based on the first reset / de-reset signal S5_PERST and the fault signal Card_Fault; in the power-on state, the logic circuit 10 can be used to output the reset / de-reset signal Card_PERST to the PCIe card based on the second reset / de-reset signal S0_PERST and the fault signal Card_Fault.

[0078] Since a PCIe card may fail, the PCIe card can be reset and de-reset when a failure occurs. Therefore, in the standby state, the reset / de-reset signal output by the logic circuit 10 to the PCIe card will be affected by the first reset / de-reset signal S5_PERST and whether the PCIe card fails, that is, the failure signal. In addition, in the standby state, the timing control circuit has not yet received the second reset / de-reset signal S0_PERST sent by the motherboard. Therefore, the reset and de-reset signals Card_PERST output by the logic circuit to the PCIe card are not affected by the second reset / de-reset signal S0_PERST; in the power-on state, the reset / de-reset signal output by the logic circuit 10 to the PCIe card will be affected by the second reset / de-reset signal S0_PERS and whether the PCIe card fails, that is, the failure signal. In addition, in the power-on state, the reset and de-reset signals Card_PERST output by the logic circuit to the PCIe card are not affected by the first reset / de-reset signal S5_PERST.

[0079] Continue to refer Figure 3 The logic circuit 10 includes an AND gate, which may further include a third input terminal for receiving a fault signal Card_Fault. The timing control circuit further includes a second pull-up circuit 40, which is connected to the third input terminal of the AND gate and is used to pull up the third input terminal of the AND gate to a logic high level when the fault signal Card_Fault is not received. For example, Figure 3 As shown, the second pull-up circuit 40 may include a pull-up resistor, one end of which is connected to the third input terminal of the AND gate, and the other end of which is connected to a high level. Furthermore, the other end of the pull-up resistor of the second pull-up circuit 40 may be connected to the other end of the pull-up resistor of the first pull-up circuit 30. In this way, through the AND gate, the reset / release signal Card_PERST output by the logic circuit 10 to the PCIe card is determined based on the first reset / release reset signal S5_PERST and the fault signal Card_Fault in the standby state, and based on the second reset / release reset signal S0_PERST and the fault signal Card_Fault in the power-on state.

[0080] That is, the timing control circuits of the first and second embodiments of the present application may include the following core components:

[0081] 1. Clock circuit, such as clock phase-locked MUX output circuit, which is mainly a clock output and phase and frequency following circuit. The main functions of the clock circuit are:

[0082] (1) In the S5 power supply state, the first clock signal, such as the 100M clock output, is maintained;

[0083] (2) In the S0 power supply state, the second clock signal is output synchronously with the PCIe clock in the S0 state.

[0084] 2. Control circuit, such as BMC control circuit, that is, the function of the control circuit can be realized by BMC (baseboard management controller). In this case, the control circuit and other components of the timing control circuit can be set on a different circuit board. The main functions of the control circuit are:

[0085] (1) Control the clock output time of the clock circuit;

[0086] (2) Output the first reset / release reset signal S5_PERST.

[0087] 3. Logic circuit: This logic circuit can be an AND gate circuit, and its main functions are:

[0088] (1) After performing logic processing on the first reset / release reset signal S5_PERST output by the control circuit and the second reset / release reset signal S0_PERST output by the motherboard in the S0 state, a reset / release reset signal Card_PERST is output to the PCIe card.

[0089] This application designs a clock phase-locked MUX output circuit, a BMC control circuit, an AND gate circuit, and related control logic to achieve the goal of continuously providing power supply, clock, and reset signals that comply with standard PCIe timing when the server switches between the S5 power supply state and the S0 power supply state, thereby ensuring the normal operation of the PCIe card and expanding the server's adaptation scenarios to meet more needs.

[0090] In addition, an embodiment of the present application further provides an adapter card, which includes a circuit board and the aforementioned timing control circuit. The circuit board has gold fingers that are used to be inserted into a slot on a mainboard. The timing control circuit is disposed on the circuit board.

[0091] The adapter card in the embodiment of the present application is a riser card / upgrade card. Clock circuits such as clock phase-locked MUX output circuits, control circuits such as BMC, and logic circuits such as AND gate circuits are designed on the riser card, so there is no need to redevelop and change the server's motherboard solution. Only the riser card and power supply cable need to be configured to support PCIe cards that need to work in the S5 power supply state, reducing development costs and meeting more configuration requirements of the server.

[0092] Furthermore, an embodiment of the present application provides a computing device comprising a motherboard, a PCIe card, and the aforementioned adapter card. The motherboard is provided with a slot, into which the gold finger of the adapter card is inserted. The PCIe card is mounted on the adapter card. The PCIe card may include a network card such as a DPU (data processing unit), a GPU card, or a RAID card.

[0093] Among them, the motherboard is used to provide the second clock signal CLK2 and the second reset / de-reset signal S0_PERST to the timing control circuit of the adapter card in the power-on state; in the standby state, the timing control circuit outputs the first clock signal CLK1 and outputs the reset / de-reset signal to the PCIe card based on the first reset / de-reset signal S5_PERST; in the power-on state, the timing control circuit outputs the second clock signal CLK2 and outputs the reset / de-reset signal to the PCIe card based on the second reset / de-reset signal S0_PERST.

[0094] To summarize, the PCIe card in a self-contained minicomputer system needs to operate in the server's S5 power state. If the server stops outputting the PCIe card's power supply, clock signal, and / Card_PERST signal in the S5 power state, it will not be able to provide the PCIe card with power signals, clock signals, and / Card_PERST signals that meet standard PCIe timing requirements during the server's S5 and S0 power state switching process, causing the PCIe card to generate alarms or malfunction. Therefore, the PCIe card in a self-contained minicomputer system needs to be started in advance in the server's S5 power state to run the system and programs to resolve the issue of the BIOS failing to scan and recognize the PCIe card due to slow board startup during server startup. In other words, the service configuration of the PCIe card is relatively important. After the server switches from S0 to S5 power state, power supply (such as 12V), PCIe clock, and / Card_PERST signal) must be maintained to keep the PCIe card functioning properly and maintain the service configuration. Therefore, the application scenario of the embodiment of the present application may be: the server has no designed power supply function in the S5 power supply state, or has no designed clock output function, or has no designed power supply, clock, / Card_EPRST timing control function.

[0095] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application and do not limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A timing control method, characterized in that: include: When switching from the shutdown state to the standby state, powering the PCIe card and providing a first clock signal and a first reset / de-reset signal, so that the PCIe card operates based on the first clock signal and the first reset / de-reset signal; When switching from the standby state to the power-on state, providing the second clock signal according to the second clock signal sent by the mainboard, and providing the second reset / de-reset signal according to the second reset / de-reset signal sent by the mainboard, so that the PCIe card operates based on the second clock signal and the second reset / de-reset signal; When switching from the power-on state to the standby state, stop receiving the second clock signal and the second reset / de-reset signal sent by the mainboard, and resume providing the first clock signal and the first reset / de-reset signal, so that the PCIe card runs based on the first clock signal and the first reset / de-reset signal.

2. The timing control method according to claim 1, wherein: The providing power to the PCIe card and providing a first clock signal and a first reset / de-reset signal includes: providing a power signal to the PCIe card, and after the power signal is stable for a period of time, providing the first clock signal to the PCIe card; after the first clock signal continues for a period of time, providing the first reset / de-reset signal; and / or, The timing control method also includes: when switching from the standby state to the shutdown state, first stopping providing the first reset / de-reset signal, stopping providing the first clock signal after a first set time, and stopping providing the power supply signal after a second set time, wherein the second set time is greater than the first set time.

3. The timing control method according to claim 1 or 2, characterized in that: Providing the second clock signal according to the second clock signal sent by the mainboard includes: receiving a second clock signal sent by the mainboard, adjusting the first clock signal to the second clock signal according to the second clock signal, and then providing the second clock signal to the PCIe card; or, A second clock signal sent by the mainboard is received, and a clock signal provided to the PCIe card is switched from the first clock signal to the second clock signal sent by the mainboard.

4. The timing control method according to any one of claims 1 to 3, characterized in that: The timing control method further includes: receiving a fault signal sent by the PCIe card, wherein the fault signal is used to indicate whether the PCIe card has a fault and needs to be reset / unreset; The causing the PCIe card to operate based on the first clock signal and the first reset / de-reset signal includes: performing a logic operation on the first reset / de-reset signal and the fault signal to obtain a reset / de-reset signal, and causing the PCIe card to operate based on the first clock signal and the reset / de-reset signal; and / or The step of causing the PCIe card to operate based on the second clock signal and the second reset / de-reset signal includes: performing a logic operation on the second reset / de-reset signal and the fault signal to obtain a reset / de-reset signal, and causing the PCIe card to operate based on the second clock signal and the reset / de-reset signal.

5. A timing control circuit, characterized in that: include: an oscillator, configured to output a first clock signal; A clock circuit, configured to receive the first clock signal and, in a power-on state, receive a second clock signal sent by the mainboard; a control circuit and a logic circuit, wherein the control circuit is configured to send a first reset / de-reset signal to a first input terminal of the logic circuit, and a second input terminal of the logic circuit is configured to receive a second reset / de-reset signal sent by the mainboard in the power-on state; In the standby state, the clock circuit is used to output the first clock signal to the PCIe card, and the logic circuit is used to output the reset / de-reset signal to the PCIe card based on the first reset / de-reset signal; in the power-on state, the clock circuit is used to output the second clock signal to the PCIe card, and the logic circuit is used to output the reset / de-reset signal to the PCIe card based on the second reset / de-reset signal.

6. The timing control circuit according to claim 5, wherein: The control circuit is configured to output the first reset / de-reset signal after determining that a first message output by the clock circuit is received, wherein the first message is used to indicate that the clock circuit is capable of outputting a stable first clock signal or a stable second clock signal; and / or, The control circuit is used to send a control signal to the clock circuit, and the control signal is used to determine a start time for the clock circuit to send the first clock signal to the PCIe card.

7. The timing control circuit according to claim 5 or 6, characterized in that: The logic circuit comprises: An AND gate, wherein a first input end of the AND gate is connected to an output end of the control circuit to receive the first reset / de-reset signal, a second input end of the AND gate is used to connect to the mainboard to receive the second reset / de-reset signal sent by the mainboard, and an output end of the AND gate is used to output the reset / de-reset signal to the PCIe card.

8. The timing control circuit according to claim 7, wherein: The timing control circuit further includes: a pull-down circuit connected to the first input terminal of the AND gate and configured to pull down the first input terminal of the AND gate to a logic low level when the control circuit does not output the first reset / de-reset signal; and / or, The first pull-up circuit is connected to the second input terminal of the AND gate and is used to pull up the second input terminal of the AND gate to a logic high level when the second reset / de-reset signal is not received.

9. The timing control circuit according to any one of claims 5 to 8, characterized in that: In the standby state, the logic circuit is configured to output the first reset / de-reset signal to the PCIe card; In the power-on state, the logic circuit is configured to output the second reset / release reset signal to the PCIe card.

10. The timing control circuit according to any one of claims 5 to 8, characterized in that: The logic circuit is further configured to receive a fault signal sent by the PCIe card, or the logic circuit is further configured to receive a fault signal output by the control circuit after determining whether a reset / de-reset operation is required based on at least one first fault signal sent by the PCIe card, the fault signal being used to indicate whether a fault occurs in the PCIe card and a reset / de-reset operation is required; In which, in the standby state, the logic circuit is used to output the reset / de-reset signal to the PCIe card based on the first reset / de-reset signal and the fault signal; in the power-on state, the logic circuit is used to output the reset / de-reset signal to the PCIe card based on the second reset / de-reset signal and the fault signal.

11. The timing control circuit according to claim 10, wherein: The AND gate of the logic circuit also includes a third input terminal, which is used to receive the fault signal. The timing control circuit also includes a second pull-up circuit, which is connected to the third input terminal of the AND gate and is used to pull up the third input terminal of the AND gate to a logic high level when the fault signal is not received.

12. An adapter card, characterized in that: include: A circuit board having a gold finger, wherein the gold finger is used to be inserted into a slot on a mainboard; The timing control circuit according to any one of claims 5 to 11 is arranged on the circuit board.

13. A computing device, characterized in that include: A mainboard, wherein the mainboard is provided with a slot, The adapter card according to claim 12, wherein the gold finger of the adapter card is inserted into the slot; A PCIe card is installed on the adapter card. in, The mainboard is used to provide a second clock signal and a second reset / de-reset signal to the timing control circuit of the adapter card in a power-on state; In the standby state, the timing control circuit outputs a first clock signal and outputs a reset / de-reset signal to the PCIe card based on a first reset / de-reset signal; in the power-on state, the timing control circuit outputs a second clock signal and outputs the reset / de-reset signal to the PCIe card based on the second reset / de-reset signal.

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