A device for an optical pulse neural network processor

Abstract

A device for an optical pulse neural network processor includes a monolithically integrated and packaged SOA and DFB-SA array optical pulse neural network chip, a multi-channel tunable light source, a modulator array, a photodetector (PD) array, a transimpedance amplifier array, an analog-to-digital converter array, two digital-to-analog converter arrays, a control circuit array, and a memory array. The optical pulse neural network chip uses a semiconductor optical amplifier (SOA) as photonic synapses and a distributed feedback semiconductor laser (DFB-SA) with a saturable absorption region as photonic neurons. Both the photonic synapses and photonic neurons are based on III / V group materials, thus allowing for monolithic integration of the optical pulse neural network chip. This invention ensures monolithic integration of the optical pulse neural network chip and flexible configuration of the optical pulse neural network processor.

Description

Technical Field

[0001] A device for an optical pulse neural network processor, belonging to the field of optical computing and optical signal processing, specifically relates to a device for an optical pulse neural network processor based on a semiconductor optical amplifier and a distributed feedback laser with a saturable absorption region. The key feature is that its optical pulse neural network chip is based on a III / V group monolithic integration. Background Technology

[0002] Compared to traditional von Neumann computing systems, spiking neural network computing seeks inspiration from the abstract principles of biological information processing to design scalable and cost-effective hardware systems. In tasks involving pattern analysis, decision-making, optimization, learning, and real-time control of multi-sensor, multi-actuator systems, neuromorphic architectures offer significant advantages over von Neumann architectures in terms of efficiency, fault tolerance, and adaptability.

[0003] The rapid development of optical integration technology has propelled high-performance optical computing back to the forefront of global research. On-chip optical pulse neural networks (IPNNs) fully integrate the characteristics of high-speed optical communication, optical interconnection, optical integration, and neuromorphic computing, offering advantages such as ultra-high speed, large bandwidth, and multi-dimensionality. They hold broad application prospects in high-performance computing and artificial intelligence.

[0004] The basic functional units of a photonic spiking neural network (PSN) are photonic spiking neurons and photonic synapses. Currently, some progress has been made in PSNs based on discrete photonic spiking neurons and photosynapses, or in heterogeneous integration. However, PSNs for monolithic integration are still in the early stages of exploration. Therefore, there is an urgent need to develop monolithic integrated PSN chips and processors based on these chips. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the present invention aims to provide a device for an optical pulse neural network processor. In this device, the optical pulse neural network chip uses a semiconductor optical amplifier (SOA) as a photonic synapse and a distributed feedback semiconductor laser (DFB-SA) with a saturable absorption region as a photonic pulse neuron. Both the photonic synapse and the photonic pulse neuron are based on group III / V materials, therefore, this photonic pulse neural network chip can be monolithically integrated.

[0006] The objective of this invention is achieved through the following means.

[0007] A device for an optical pulse neural network processor includes a monolithically integrated and packaged SOA and DFB-SA array optical pulse neural network chip, a multi-channel tunable light source, a modulator array, a photodetector (PD) array, a transimpedance amplifier array, an analog-to-digital converter (ADC) array, two digital-to-analog converter (DAC) arrays, a control circuit array, and a memory array. The optical pulse neural network processor device is characterized in that its optical pulse neural network chip is based on a III / V group monolithically integrated design; the output of the multi-channel tunable light source is connected to the optical input of the modulator array; the output of the modulator array is connected to the input of the optical pulse neural network chip; the two outputs of the controller are connected to the inputs of the two DAC arrays; the outputs of the two DAC arrays are connected to the RF terminal of the modulator and the current control terminal of the optical pulse neural network chip, respectively; the output of the optical pulse neural network chip is connected to the input of the PD array; the output of the PD array is connected to the input of the transimpedance amplifier array; the output of the transimpedance amplifier array is connected to the input of the ADC array; the output of the ADC array is connected to the input of the control circuit; and the control circuit and the memory are interconnected for data storage and retrieval. The optical pulse neural network chip is characterized in that: the output of the modulator is connected to the input of the on-chip beamsplitter; the output of the beamsplitter is connected to the input of the arrayed waveguide grating; the output of the arrayed waveguide grating is connected to the input of the SOA synapse; the output of the SOA synapse is connected to the input of the second arrayed waveguide grating; the output of the second arrayed waveguide grating is connected to the DFB-SA neuron array; and the output of the DFB-SA neuron array is used as the output of the optical pulse neural network chip for further transformation and analysis.

[0008] After the above design, discrete devices such as a single-channel SOA and DFB-SA were used as examples for testing. The injection pulses of the optical pulse neural network were generated by devices such as a tunable light source TL, a polarization controller PC, a modulator, and an arbitrary waveform transmitter AWG. The external light injection was weighted through the SOA synapses and then entered the DFB-SA through an adjustable optical attenuator VOA and a three-port circulator CIR. The signal after the DFB-SA was processed was output to the optical spectrum analyzer OSA and the oscilloscope OSC through the CIR and the optical coupler OC. By adjusting the current of the SOA synapses, the SOA was made to generate different weights, and the output of the DFB-SA neurons was observed.

[0009] The present invention provides an optical pulse neural network processor device, which has the following advantages compared with previously reported optical pulse neural network processor devices: the optical pulse neural network chip can be integrated on a single chip. Attached Figure Description

[0010] Figure 1 This is a system block diagram of the device of the present invention;

[0011] Figure 2 This is a schematic diagram of the internal structure of an optical pulse neural network chip;

[0012] Figure 3 Schematic diagram of experimental scheme for single-channel SOA and DFB-SA optical pulse neural network;

[0013] Figure 4 Threshold characteristics of optical pulse neural networks to external stimuli

[0014] Figure 5 This represents the cumulative response of an optical pulse neural network to external stimuli.

[0015] Figure 6 This represents the refractory period response of an optical pulse neural network to external stimuli. Detailed Implementation

[0016] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings: These embodiments are implemented based on the technical solution of the present invention, and provide detailed implementation methods and specific operation procedures, but the protection scope of the present invention is not limited to the following embodiments.

[0017] like Figure 3 As shown, an embodiment of the present invention comprises a tunable light source TL, two polarization controllers PC1 and PC2, an intensity modulator, an electrical amplifier, an AWG, two dual-channel DC sources, a semiconductor optical amplifier SOA, two tunable optical attenuators VOA1 and VOA2, a three-port optical circulator CIR, an optical coupler OC, a DFB-SA, a current-temperature controller, a photodetector PD, an oscilloscope OSC, and a spectrometer OSA. The SOA is a photonic synapse; the DFB-SA is a photonic pulse neuron; the SOA and DFB-SA form a photonic pulse neural network; by adjusting the current of the SOA, i.e., the synaptic weights in the photonic pulse neural network, different responses of the photonic pulse neural network to stimuli can be observed.

[0018] In this example, the specific implementation steps of the method are as follows:

[0019] Step 1: In Figure 3 In the illustrated scheme, the DFB-SA is a two-stage semiconductor laser with a wavelength of 1550-1554 nm. The wavelength of the TL is set to 1552.3 nm.

[0020] Step 2: Adjust the current and bias voltage in the gain region and saturation absorption region of the DFB-SA to 32mA and -2.8V respectively. Set the AWG so that large and small stimulation pulses are fed into the optical pulse neural network, such as... Figure 4 As shown in (a), the dynamic response of the DFB-SA was observed by adjusting the SOA synaptic current, and the results are as follows. Figure 4 As shown in (b). Figure 4 (b) It can be seen that under the action of SOA, DFB-SA has no pulse response under low intensity stimulation and has a pulse response under high intensity stimulation, thus realizing the threshold characteristics of optical pulse neural network.

[0021] Step 3: Set up the AWG so that three closely spaced stimulation pulses enter the optical pulse neural network, as shown in Figure 5(a). Adjust the SOA synaptic current and observe the dynamic response of the DFB-SA. The results are as follows: Figure 5 As shown in (b). Figure 5 (b) It can be seen that under the action of SOA, the DFB-SA photonic pulse neuron only generates a spike pulse at the third stimulation pulse, thus indicating that the optical pulse neural network can produce a cumulative effect.

[0022] Step 4: Adjust the SOA synaptic current again and observe the dynamic response of the DFB-SA. The results are as follows: Figure 6 As shown in (b). Figure 6 (b) It can be seen that under the action of SOA, the DFB-SA photonic pulse neuron only generates spike pulses at the first and third stimulation pulses, thus indicating that the optical pulse neural network can generate a refractory period.

[0023] Step 5: Increase the number of SOA synapses and DFB-SA neurons in the optical pulse neural network, and integrate them to form a multi-node optical pulse neural network chip, such as... Figure 2 As shown.

[0024] Step Six: In Figure 2 Based on this, adding electro-optical interfaces, photoelectric interfaces, and control circuits creates a configurable optical pulse neural network processor, such as... Figure 1 As shown.

[0025] In summary, the present invention has the following features: 1) It utilizes a semiconductor optical amplifier array as a synaptic array and a distributed feedback semiconductor laser array with a saturable absorption region as a neuron array to form a monolithically integrated optical pulse neural network chip; 2) Based on the optical pulse neural network chip, electro-optic / optoelectronic interface, control circuit and other modules, a configurable optical pulse neural network processor is formed.

[0026] In summary, the above-described embodiments are merely examples of the present invention and are not intended to limit the scope of protection of the present invention. It should be noted that for those skilled in the art, several equivalent modifications and substitutions can be made to the content disclosed in the present invention (such as appropriately changing the magnitude of the operating current, changing the frequency detuning, changing the magnitude of the injected pulse power, and expanding the scale of the optical pulse neural network), which should also be included within the scope of protection of the present invention.

Claims

1. A device for an optical pulse neural network processor, comprising a monolithically integrated and packaged SOA and DFB-SA array optical pulse neural network chip, a multi-channel tunable light source, a modulator array, a photodetector (PD) array, a transimpedance amplifier array, an analog-to-digital converter array, two digital-to-analog converter arrays, a control circuit array, and a memory array, characterized in that, Its optical pulse neural network chip is based on a III / V group monolithic integrated circuit. The output of the multi-channel tunable light source is connected to the optical input of the modulator array; the output of the modulator array is connected to the input of the optical pulse neural network chip; the two outputs of the controller are connected to the inputs of two digital-to-analog converter arrays; the outputs of the two digital-to-analog converter arrays are connected to the RF terminal of the modulator and the current control terminal of the optical pulse neural network chip, respectively; the output of the optical pulse neural network chip is connected to the input of the PD array; the output of the PD array is connected to the input of the transimpedance amplifier array; and the output of the transimpedance amplifier array is connected to the input of the analog-to-digital converter array. The output of the analog-to-digital converter array is connected to the input of the control circuit; the control circuit and the memory are interconnected for data storage and retrieval; regarding the optical pulse neural network chip, the modulator's output is connected to the input of the on-chip beamsplitter; the beamsplitter's output is connected to the input of the arrayed waveguide grating; the arrayed waveguide grating's output is connected to the input of the SOA synapse; the SOA synapse's output is connected to the input of the second arrayed waveguide grating; the second arrayed waveguide grating's output is connected to the DFB-SA neuron array; the output of the DFB-SA neuron array is used as the output of the optical pulse neural network chip for further transformation and analysis.

2. The apparatus for an optical pulse neural network processor according to claim 1, characterized in that, A semiconductor optical amplifier (SOA) is used as a photonic synapse, and a feedback semiconductor laser (DFB-SA) with a saturation absorption region is used as a photonic neuron. Both the photonic synapse and the photonic neuron are based on III / V group materials, and can be monolithically integrated into an optical pulse neural network chip.

3. The apparatus for an optical pulse neural network processor according to claim 1, characterized in that, The optical pulse neural network processor can be flexibly configured through connections such as optoelectronic / optoelectronic interfaces and control circuits.

4. The apparatus for an optical pulse neural network processor according to claim 1, characterized in that, The number of nodes in an optical pulse neural network chip can be expanded to n×n.

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