Data selection circuit, display substrate and display device

Abstract

The present disclosure provides a data selection circuit, comprising: at least two gating circuits, the gating circuit comprising: a control circuit, an adjustment circuit, an output circuit and a reset circuit; the control circuit is configured to write a valid level voltage to a control node in response to the control of a gating control signal line; the adjustment circuit is configured to receive a reference voltage provided by a data signal input terminal while the control circuit writes the valid level voltage to the control node, and subsequently write an adjustment voltage to the control node when the voltage provided by the data signal input terminal changes from the reference voltage to the data voltage, the adjustment voltage being equal to the difference between the sum of the valid level voltage and the data voltage and the reference voltage; the output circuit is configured to output a corresponding on-state current according to the difference between the voltage at the control node and the voltage at the data signal input terminal; the reset circuit is configured to write a non-valid level voltage to the control node in response to the control of a reset control signal line.

Description

Technical Field

[0001] The present disclosure relates to the field of display, and in particular to a data selection circuit, a display substrate, and a display device. Background Art

[0002] In order to reduce the number of source driver chips (Source ICs), the related art proposes a solution of setting a data selector (Multiplexer, also called a multiplexer) between the source driver chip and the data line; that is, one terminal of the source driver chip is connected to two or more data lines through the data selector, so that the one terminal can provide data voltage to the two or more data lines at different times. Summary of the Invention

[0003] In a first aspect, an embodiment of the present disclosure provides a data selection circuit, configured with a data signal input terminal and at least two data signal output terminals, the data selection circuit comprising: at least two gating circuits corresponding one-to-one to the data signal output terminals, each gating circuit being configured with a corresponding gating control signal line and a reset control signal line;

[0004] The gating circuit includes: a control circuit, an adjustment circuit, an output circuit and a reset circuit, wherein the control circuit, the adjustment circuit, the output circuit and the reset circuit are connected to a control node;

[0005] The control circuit is connected to the corresponding strobe control signal line and is configured to write a valid level voltage to the control node in response to control of the strobe control signal line;

[0006] the adjustment circuit being connected to the data signal input terminal and configured to receive a reference voltage provided by the data signal input terminal while the control circuit writes the effective level voltage to the control node, and subsequently write an adjustment voltage to the control node when the voltage provided by the data signal input terminal changes from the reference voltage to the data voltage, the adjustment voltage being equal to the difference between the reference voltage and the sum of the effective level voltage and the data voltage;

[0007] The output circuit is connected to the data signal input terminal and the corresponding data signal output terminal, and is configured to output a corresponding on-state current according to the difference between the voltage at the control node and the voltage at the data signal input terminal;

[0008] The reset circuit is connected to the corresponding reset control signal line and is configured to write a non-active level voltage to the control node in response to control of the reset control signal line.

[0009] In some embodiments, the control circuit includes a first transistor, the reset circuit includes a second transistor, the output circuit includes a third transistor, and the adjustment circuit includes a capacitor;

[0010] The control electrode of the first transistor is connected to the corresponding selection control signal line, the first electrode of the first transistor is connected to the effective level voltage supply line, and the second electrode of the first transistor is connected to the control node;

[0011] The control electrode of the second transistor is connected to the corresponding reset control signal line, the first electrode of the second transistor is connected to the non-active level voltage supply line, and the second electrode of the second transistor is connected to the control node;

[0012] The control electrode of the third transistor is connected to the control node, the first electrode of the third transistor is connected to the data signal input terminal, and the second electrode of the third transistor is connected to the corresponding data signal output terminal;

[0013] The first end of the capacitor is connected to the data signal input end, and the second end of the capacitor is connected to the corresponding data signal output end.

[0014] In some embodiments, the effective level voltage supply line connected to the first electrode of the first transistor is the selection control signal line connected to the control electrode of the same first transistor.

[0015] In some embodiments, the non-active level voltage supply line connected to the first electrode of the second transistor is the gating control signal line connected to the control electrode of the first transistor in the same gating circuit.

[0016] In some embodiments, the number of the gating circuits is N, wherein the data signal output terminal of the first gating circuit to the data signal output terminal of the Nth gating circuit outputs data in sequence;

[0017] The reset control signal line configured for the i-th gating circuit is the gating control signal line configured for the i+1-th gating circuit, where 1≤i≤N-1 and i is an integer;

[0018] The reset control signal line configured for the Nth selection circuit is the selection control signal line configured for the first selection circuit.

[0019] In some embodiments, all transistors in the gating circuit are metal oxide transistors.

[0020] In some embodiments, the number of the gating circuits is 2, and the number of the gating control signal lines is 2;

[0021] The gate control signal line extends along a first direction, and two gate control signal lines are arranged along a second direction, and the first direction intersects the second direction;

[0022] The two gating circuits are both located between the two gating control signal lines and arranged along the first direction.

[0023] In some embodiments, the two gating circuits are respectively a first gating circuit and a second gating circuit, and the two gating control signal lines are respectively a first gating control signal line and a second gating control signal line;

[0024] In the first gating circuit, the first electrode of the first transistor is connected to the first gating control signal line, which is a valid level voltage supply line, and the first electrode of the second transistor is connected to the second gating control signal line, which is a non-valid level voltage supply line. The second transistor is located on a side of the first transistor away from the first gating control signal line.

[0025] In the second gating circuit, the first electrode of the first transistor is connected to the effective level voltage supply line of the second gating control signal line, the first electrode of the second transistor is connected to the non-effective level voltage supply line of the first gating control signal line, and the second transistor is located on the side of the first transistor away from the second gating control signal line.

[0026] In some embodiments, in any one of the gating circuits, the first transistor and the second transistor are arranged along the second direction, and the third transistor and the first transistor are arranged along a third direction, and the third direction intersects with the second direction.

[0027] In some embodiments, the data selection circuit includes: a first conductive layer, a first insulating layer, a semiconductor layer, and a second conductive layer formed sequentially;

[0028] The first conductive layer includes: the first gate control signal line, the second gate control signal line, the control electrode of the first transistor, the control electrode of the second transistor, the control electrode of the third transistor, and the first plate of the capacitor;

[0029] The semiconductor layer includes: an active layer pattern of the first transistor, an active layer pattern of the second transistor, and an active layer pattern of the third transistor;

[0030] The second conductive layer includes: a first electrode of the first transistor, a second electrode of the first transistor, a first electrode of the second transistor, a second electrode of the second transistor, a first electrode of the third transistor, and a second electrode of the third transistor;

[0031] The second electrode of the first transistor is connected to the control electrode of the third transistor through a via hole penetrating the first insulating layer.

[0032] In some embodiments, the data selection circuit includes a first conductive layer, a first insulating layer, a semiconductor layer, a second conductive layer, a second insulating layer, and a third conductive layer formed sequentially;

[0033] The first conductive layer includes: the first gate control signal line, the second gate control signal line, the control electrode of the first transistor, the control electrode of the second transistor, the control electrode of the third transistor, and the first plate of the capacitor;

[0034] The semiconductor layer includes: an active layer pattern of the first transistor, an active layer pattern of the second transistor, and an active layer pattern of the third transistor;

[0035] The second conductive layer includes: a first electrode of the first transistor, a second electrode of the first transistor, a first electrode of the second transistor, a second electrode of the second transistor, a first electrode of the third transistor, and a second electrode of the third transistor;

[0036] The third conductive layer includes: a first conductive connection pattern, a portion of the first conductive connection pattern is electrically connected to the second electrode of the first transistor through a via hole penetrating the second insulating layer, and another portion of the first conductive connection pattern is electrically connected to the control electrode of the third transistor through a via hole penetrating the second insulating layer and the first insulating layer.

[0037] In some embodiments, the material of the third conductive layer includes a transparent conductive material.

[0038] In a second aspect, an embodiment of the present disclosure further provides a display substrate, comprising: the data selection circuit provided in the first aspect above.

[0039] In some embodiments, the display substrate further comprises: a base substrate, the base substrate being divided into a display area and a peripheral area located around the display area, the data selection circuit being located in the peripheral area;

[0040] A switching transistor is provided in the display area;

[0041] The data selection circuit further includes a third conductive layer, which is arranged on a side of the switch transistor away from the base substrate. The third conductive layer further includes: a pixel electrode and / or a common electrode.

[0042] In a third aspect, an embodiment of the present disclosure further provides a display device, comprising: the display substrate provided in the second aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 A schematic diagram of a circuit structure of a data selector involved in the related art;

[0044] Figure 2 Schematic diagram showing how the on-state current Ids output by the output transistor in the gating circuit varies with the gate-source voltage in the related art;

[0045] Figure 3 A schematic diagram of a circuit structure of a data selection circuit provided in an embodiment of the present disclosure;

[0046] Figure 4 A schematic diagram of a circuit structure of a gating circuit in an embodiment of the present disclosure;

[0047] Figure 5 Schematic diagram of another circuit structure of the gating circuit in the embodiment of the present disclosure;

[0048] Figure 6 for Figure 5 An operation timing diagram of the gating circuit shown;

[0049] Figure 7 A schematic diagram of a circuit structure of a data selection circuit provided in an embodiment of the present disclosure;

[0050] Figure 8 for Figure 7 A layout of the data selection circuit shown;

[0051] Figure 9 for Figure 8 A schematic cross-sectional view in the A-A' direction;

[0052] Figure 10 for Figure 7 Another layout of the data selection circuit shown;

[0053] Figure 11 for Figure 10 A schematic cross-sectional view of the BB direction. DETAILED DESCRIPTION

[0054] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the following will be combined with the drawings of the embodiments of the present disclosure. The technical solutions of the embodiments of the present disclosure are clearly and completely described. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0055] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0056] It should be noted that the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same or similar characteristics. Since the source and drain of the transistors used are symmetrical, the two can be interchanged. In the embodiments of the present disclosure, in order to distinguish the source and drain of the transistor, one of the electrodes is called the first electrode, the other electrode is called the second electrode, and the gate is called the control electrode. In addition, transistors can be divided into N-type and P-type according to their characteristics. When an N-type transistor is used, the first electrode is the drain of the N-type transistor, and the second electrode is the source of the N-type transistor. The situation is the opposite for the P-type transistor. The "effective level" in the present disclosure refers to a level signal that can control the conduction of the corresponding transistor; specifically, for the transistor to be controlled being an N-type transistor, the corresponding effective level is a high level; for the transistor to be controlled being a P-type transistor, the corresponding effective level is a low level.

[0057] Figure 1 The figure is a schematic diagram of a circuit structure of a data selector involved in the related art. Figure 1As shown in the related art, a data selector includes N (N ≥ 2 and is a positive integer) strobe circuits S_1 to S_N. Each strobe circuit S_1 to S_N includes an output transistor M0. The control electrode of the output transistor M0 is connected to the corresponding strobe control signal line MUX_1 to MUX_N. The first electrode of the output transistor M0 is connected to the data signal input terminal IN (connected to an output terminal of the source driver chip), and the second electrode of the output transistor M0 is connected to the corresponding data signal output terminal OUT_1 to OUT_N (connected to the corresponding data line DATA). The signal provided by the strobe control signal line MUX_1 to MUX_N is used to control the corresponding output transistor M0 to be turned on or off. By controlling the multiple output transistors M0 to be turned on in sequence, the data voltage provided by the data signal input terminal IN is output to different data lines DATA in sequence. Specifically, a selection control signal line MUX_i provides an active-level voltage to the control electrode of the corresponding output transistor M0. Upon receiving the active-level signal, the output transistor M0 outputs an on-state current to charge the corresponding data line DATA. The on-state current output by the output transistor M0 is related to the gate-source voltage Vgs of the output transistor M0. For example, if the selection control signal line provides an active-level voltage of VGH and the data voltage provided by the data signal input terminal IN is Vdata, the gate-source voltage of the output transistor M0 is Vgs = VGH - Vdata.

[0058] To prevent liquid crystal polarization, positive and negative polarity frames are typically displayed alternately. In positive polarity frames, a positive data voltage (data voltage greater than the common voltage) is used for display control, while in negative polarity frames, a negative data voltage (data voltage less than the common voltage) is used for display control.

[0059] Figure 2 Schematic diagram showing the change of the on-state current Ids output by the output transistor in the gating circuit in the related art as the gate-source voltage changes. Figure 2 As shown, the common voltage Vcom is 8.68V, the positive polarity data voltage Vdata 正 9.4V~15.8V, negative polarity data voltage Vdata 负 The gate-source voltage Vgs of the output transistor M0 is 1.56~7.96V, and the row scanning driving voltage Vg is 32V. 正 =VGH-Vdata 正 ,Vgs 正 Range: 16.2 ~ 22.6V; in the negative polarity frame, the gate-source voltage Vgs of the output transistor M0 负 =VGH-Vdata 负 , Vgs negative range: 24.04V~30.44V. Figure 2 As shown in FIG, the charging speed of the output transistor M0 in the positive polarity frame (represented by the on-state current Ids, where a larger current Ids indicates a faster charging speed) is smaller than that in the negative polarity frame. In other words, there is a charging difference between the positive and negative polarity frames.

[0060] In high-resolution products, the on-time of each selector circuit S_1-S_N is relatively short. During this period, different on-state currents Ids result in differences in the data voltage actually supplied to the data line DATA. Specifically, the charging rate of the data selector on the data line DATA differs from that on the data selector on the negative polarity screen. This can lead to image sticking during display. The charging rate of the data selector on the data line DATA is the ratio of the data voltage actually written to the data line DATA by the data selector to the data voltage supplied by the data signal input terminal IN of the data selector.

[0061] In addition, when the same output transistor M0 writes negative polarity data voltages or positive polarity data voltages of different sizes to the same data line DATA, due to the different sizes of the data voltages, the gate-source voltages of the output transistor M0 are also different, so the output on-state current of the output transistor M0 is also different, and at this time there will also be a problem of different charging rates.

[0062] In order to effectively improve the problem in the related art that when a selection circuit transmits different data voltages, the on-state current output by the output transistor is different, resulting in different charging rates of the data selector for the data line, the present disclosure provides a corresponding solution.

[0063] Figure 3 A schematic diagram of a circuit structure of a data selection circuit provided in an embodiment of the present disclosure. Figure 4 FIG. 1 is a schematic diagram of a circuit structure of a gating circuit in an embodiment of the present disclosure. Figure 3 and Figure 4 As shown, the data selection circuit is configured with a data signal input terminal IN and at least two data signal output terminals OUT_1~OUT_N. The data selection circuit includes: at least two selection circuits S_1~S_N corresponding to the data signal output terminals OUT_1~OUT_N one by one, and each selection circuit S_1~S_N is configured with a corresponding selection control signal line MUX_i and a reset control signal line RST_i; the selection circuit S_i includes: a control circuit 1, an adjustment circuit 4, an output circuit 3 and a reset circuit 2, and the control circuit 1, the adjustment circuit 4, the output circuit 3 and the reset circuit 2 are connected to the control node CN.

[0064] The control circuit 1 is connected to the corresponding selection control signal line MUX_i, and is configured to write a valid level voltage to the control node CN in response to the control of the selection control signal line MUX_i, so as to control the output circuit 3 to be in an operating state.

[0065] The adjustment circuit 4 is connected to the data signal input terminal IN. The adjustment circuit 4 is configured to receive the reference voltage provided by the data signal input terminal IN while the control circuit 1 writes the effective level voltage to the control node CN, and subsequently write an adjustment voltage to the control node CN when the voltage provided by the data signal input terminal IN changes from the reference voltage to the data voltage. The adjustment voltage is equal to the difference between the sum of the effective level voltage and the data voltage and the reference voltage.

[0066] The output circuit 3 is connected to the data signal input terminal IN and the corresponding data signal output terminal OUT_i. When in operation, the output circuit 3 is configured to output a corresponding on-state current according to the difference between the voltage at the control node CN and the voltage at the data signal input terminal IN.

[0067] The reset circuit 2 is connected to the corresponding reset control signal line RST_i. The reset circuit 2 is configured to write a non-active level voltage to the control node CN in response to the control of the reset control signal line RST_i to control the output circuit 3 to be in a non-operating state.

[0068] Taking the working process of a strobe circuit S_i as an example, it specifically includes: a control stage, an adjustment and writing stage, and a reset stage.

[0069] In the control phase, the control circuit 1 writes an effective level voltage to the control node CN in response to the control of the selection control signal line MUX_i, while the data signal input terminal IN provides a reference voltage, where the effective level voltage is VGH and the reference voltage is Vref.

[0070] At this time, the difference between the voltage at the control node CN and the voltage at the data signal input terminal IN is △V_t1:

[0071] △V_t1=VGH-Vref.

[0072] Therefore, in the control stage, the output circuit 3 outputs the corresponding on-state current according to ΔV_t1.

[0073] During the adjustment and writing phase, the control circuit 1 stops writing the effective level voltage to the control node CN, and the voltage provided by the data signal input terminal IN changes from the reference voltage to the data voltage, where the data voltage is Vdata. At this time, the adjustment circuit 4 writes an adjustment voltage to the control node CN, and the adjustment voltage is equal to the difference between the sum of the effective level voltage and the data voltage and the reference voltage; wherein the adjustment voltage is Vp, Vp = VGH + Vdata - Vref.

[0074] At this time, the difference between the voltage at the control node CN and the voltage at the data signal input terminal IN is △V_t2:

[0075] △V_t2=VGH+Vdata-Vref-Vdata=VGH-Vref

[0076] Therefore, in the control phase, the output circuit 3 outputs the corresponding on-state current according to ΔV_t2. Since ΔV_t1 = ΔV_t2 = VGH - Vref, the on-state current output by the output circuit 3 in the control phase and the adjustment and writing phase is the same.

[0077] In the reset phase, the reset circuit 2 writes a non-active level voltage to the control node CN in response to the control of the reset control signal line RST_i, so as to control the output circuit 3 to be in a non-working state and the output circuit 3 stops outputting.

[0078] Thus, the on-state current of the output circuit 3 during the adjustment and writing phases in the present disclosure is only related to the difference between the effective voltage level provided by the control circuit 1 and the reference voltage provided by the data signal input terminal IN during the control phase, and is unrelated to the data voltage provided by the data signal input terminal IN during the adjustment and writing phases. Therefore, the technical solution of the present disclosure enables the selection circuit S_i to transmit different data voltages with the same on-state current (same charging speed), thereby ensuring the consistency of the charging rate of the data line DATA by the data selector under different data voltages, thereby improving the afterimage problem that occurs in the related art.

[0079] Figure 5 FIG. 1 is another circuit structure diagram of the gating circuit in the embodiment of the present disclosure. Figure 5 As shown, in some embodiments, Figure 5 The gating circuit shown is based on Figure 4 In some embodiments, the control circuit 1 includes a first transistor M1 , the reset circuit 2 includes a second transistor M2 , the output circuit 3 includes a third transistor M3 , and the adjustment circuit 4 includes a capacitor C.

[0080] The control electrode of the first transistor M1 is connected to the corresponding selection control signal line MUX_i, the first electrode of the first transistor M1 is connected to the effective level voltage supply line, and the second electrode of the second transistor M2 is connected to the control node CN.

[0081] A control electrode of the second transistor M2 is connected to the corresponding reset control signal line RST_i, a first electrode of the second transistor M2 is connected to the non-active level voltage supply line, and a second electrode of the second transistor M2 is connected to the control node CN.

[0082] A control electrode of the third transistor M3 is connected to the control node CN, a first electrode of the third transistor M3 is connected to the data signal input terminal IN, and a second electrode of the third transistor M3 is connected to the corresponding data signal output terminal OUT_i.

[0083] A first end of the capacitor C is connected to the data signal input terminal IN, and a second end of the capacitor C is connected to the corresponding data signal output terminal OUT_i.

[0084] In some embodiments, the active-level voltage supply line connected to the first electrode of the first transistor M1 is the same as the gate control signal line MUX_i connected to the control electrode of the same first transistor M1. In the disclosed embodiments, by multiplexing the gate control signal line MUX_i as the active-level voltage supply line, the number of signal lines configured in the data selection circuit can be effectively reduced, which helps simplify the circuit structure and reduce the overall size of the data selection circuit.

[0085] In some embodiments, the non-active voltage supply line connected to the first electrode of the second transistor M2 is the same as the selection control signal line MUX_i connected to the control electrode of the first transistor M1 in the same selection circuit S_i. In the disclosed embodiments, by multiplexing the selection control signal line MUX_i as the non-active voltage supply line, the number of signal lines configured in the data selection circuit can be effectively reduced, which helps to simplify the circuit structure and reduce the overall size of the data selection circuit.

[0086] In some embodiments, the number of selection circuits S_1-S_N is N, wherein the data signal output terminals OUT_1 of the first selection circuit S_1 through OUT_N of the Nth selection circuit S_N sequentially output data; wherein the reset control signal line RST_1i configured for the i-th selection circuit S_i is the selection control signal line MUX_i+1 configured for the i+1-th selection circuit S_i+1, where 1≤i≤N-1 and i is an integer; and the reset control signal line RST_N configured for the N-th selection circuit S_N is the selection control signal line MUX_1 configured for the first selection circuit S_1. In the disclosed embodiments, by multiplexing the selection control signal lines MUX_1-MUX_N as the reset control signal lines RST_1-RST_N, the number of signal lines configured for the data selection circuit can be effectively reduced, thereby simplifying the circuit structure and reducing the overall size of the data selection circuit.

[0087] It should be noted that Figure 5 Only the circuit structure of the i-th gating circuit S_i is shown as an example.

[0088] In the disclosed embodiments, each transistor in the gating circuits S_1 to S_N can be independently designed as an N-type transistor or a P-type transistor. In some embodiments, all transistors in the gating circuits S_1 to S_N are N-type transistors or P-type transistors. In this case, all transistors in the gating circuits S_1 to S_N can be fabricated simultaneously using the same transistor fabrication process.

[0089] In addition, the data selection circuit in the present disclosure can be applied to a display substrate, and switching transistors are also provided in the display area of ​​the display substrate. Therefore, in the embodiment of the present disclosure, each transistor in the selection circuit S_1 to S_N can be designed to be the same transistor type as the switching transistor in the display area. Therefore, the data selection circuit can be simultaneously prepared based on the existing display substrate preparation process, and therefore there is no need to add additional processes for the preparation of the data selection circuit.

[0090] In some embodiments, all transistors in the gating circuits S_1 to S_N are metal oxide transistors. In the disclosed embodiments, each transistor in the gating circuits S_1 to S_N switches between an on-state and an off-state. When the value of N is large, the time the transistor is in the off-state is significantly longer than the time it is in the on-state, which can easily lead to leakage current in the transistor. Using metal oxide transistors effectively reduces leakage current in the off-state.

[0091] The following takes the case where all transistors in the gating circuits S_1 to S_N are N transistors as an example to explain Figure 5 The working process of the gating circuits S_1 to S_N is described in detail.

[0092] Figure 6 for Figure 5 A working timing diagram of the gating circuit shown in FIG. Figure 6 As shown, the working process of the gating circuit S_i specifically includes: a control phase t1, an adjustment and writing phase t2, and a reset phase t3.

[0093] In control phase t1, the selection control signal line MUX_i provides a high level, and the reset control signal line RST_i provides a low level. The first transistor M1 is turned on to write the effective level voltage VGH to the control node CN, and the second transistor M2 is turned off. At the same time, the data signal input terminal IN provides the reference voltage Vref. At this time, the difference between the voltage at the control node CN and the voltage at the data signal input terminal IN is ΔV_t1:

[0094] △V_t1=VGH-Vref.

[0095] At this time, the voltage difference across the capacitor C is VGH-Vref; the gate-source voltage Vgs of the third transistor M3 is VGH-Vref, and the third transistor M3 outputs an on-state current corresponding to VGH-Vref.

[0096] In the adjustment and writing phase t2, the selection control signal line MUX_i provides a low level, and the reset control signal line RST_i provides a low level; the first transistor M1 and the second transistor M2 are both turned off. At this time, the control node CN is in a floating state, and the voltage provided by the data signal input terminal IN changes from the reference voltage Vref to the data voltage Vdata;

[0097] Under the bootstrap effect of capacitor C, the voltage at control node CN changes from VGH to Vp = VGH + Vdata - Vref (i.e., the regulated voltage), and the voltage difference across capacitor C is maintained at VGH - Vref. When Vdata > Vref, the voltage at control node CN is pulled up; when Vdata is less than Vref, the voltage at control node CN is pulled down. Figure 6 FIG. 4 only illustrates the case where the control node CN is pulled up.

[0098] The gate-source voltage Vgs of the third transistor M3 is VGH-Vref, and the third transistor M3 outputs an on-state current corresponding to VGH-Vref. Therefore, the on-state current output by the third transistor M3 in the control phase and the adjustment and writing phase is the same.

[0099] In the reset phase t3 , the selection control signal line MUX_i provides a low level, and the reset control signal line RST_i provides a low high level; the first transistor M1 is turned off, the second transistor M2 is turned on to write the non-active level voltage VGL to the control node CN, and the third transistor M3 is turned off.

[0100] It should be noted that when the reset control signal line RST_i configured for the i-th selection circuit S_i is the selection control signal line MUX_i configured for the i+1-th selection circuit S_i, the reset phase of the i-th selection circuit S_i and the control phase of the i+1-th selection circuit S_i+1 correspond to the same time period.

[0101] Figure 7 A schematic diagram of a circuit structure of a data selection circuit provided in an embodiment of the present disclosure. Figure 8 for Figure 7 One layout of the data selection circuit shown. Figure 9 for Figure 8 A schematic cross-sectional view along the A-A' direction. Figure 10 for Figure 7 An alternative layout of the data selection circuit is shown. Figure 11 for Figure 10 A cross-sectional diagram of the BB direction. Figures 7 to 11 As shown, in some embodiments, the number of the gating circuits S_1-S_2 is 2, the number of the gating control signal lines MUX_1-MUX_2 is 2; the gating control signal lines MUX_1-MUX_2 are along the first direction (for example Figure 8 and Figure 10 The two selection control signal lines MUX_1 to MUX_2 extend in the second direction (e.g., Figure 8 and Figure 10 The two selection circuits S_1 and S_2 are both located between the two selection control signal lines MUX_1 and MUX_2 and are arranged along the first direction.

[0102] See also Figure 8 and Figure 10 As shown, in some embodiments, the two gating circuits are respectively a first gating circuit S_1 and a second gating circuit S_2, and the two gating control signal lines are respectively a first gating control signal line MUX_1 and a second gating control signal line MUX_2; in the first gating circuit S_1, the effective level voltage supply line connected to the first electrode of the first transistor M1 is the first gating control signal line MUX_1, the ineffective level voltage supply line connected to the first electrode of the second transistor M2 is the second gating control signal line MUX_2, and the second transistor M2 is located on a side of the first transistor M1 away from the first gating control signal line MUX_1; in the second gating circuit S_2, the effective level voltage supply line connected to the first electrode of the first transistor M1 is the second gating control signal line MUX_2, the ineffective level voltage supply line connected to the first electrode of the second transistor M2 is the first gating control signal line MUX_1, and the second transistor M2 is located on a side of the first transistor M1 away from the second gating control signal line MUX_2.

[0103] In some embodiments, within any one of the gating circuits S_1 to S_2, the first transistor M1 and the second transistor M2 are arranged along a second direction, and the third transistor M3 and the first transistor M1 are arranged along a third direction that intersects the second direction. Optionally, the third direction may be parallel to the first direction.

[0104] See also Figure 8 and Figure 9As shown, in some embodiments, the data selection circuit includes: a first conductive layer LC1, a first insulating layer LC2, a semiconductor layer ACT and a second conductive layer LC3 formed in sequence; the first conductive layer LC1 includes: first selection control signal lines MUX_1~MUX_N, second selection control signal lines MUX_1~MUX_N, a control electrode of the first transistor M1, a control electrode of the second transistor M2, a control electrode of the third transistor M3, and a first plate of the capacitor C; the semiconductor layer ACT includes: an active layer pattern of the first transistor M1, an active layer pattern of the second transistor M2 and an active layer pattern of the third transistor M3; the second conductive layer LC3 includes: a first electrode of the first transistor M1, a second electrode of the first transistor M1, a first electrode of the second transistor M2, a second electrode of the second transistor M2, a first electrode of the third transistor M3, and a second electrode of the third transistor M3; the second electrode on the first transistor M1 is connected to the control electrode of the third transistor M3 through a via hole penetrating the first insulating layer LC2.

[0105] In addition, the first electrode of the second transistor M2 in the first selection circuit S_1 is connected to the first selection control signal line MUX_1 through a via hole penetrating the first insulating layer LC2, and the first electrode of the second transistor M2 in the second selection circuits S_1 to S_N is connected to the second selection control signal line MUX_2 through a via hole penetrating the first insulating layer LC2.

[0106] See also Figure 10 and Figure 11 As shown, in some embodiments, the data selection circuit includes a first conductive layer LC1, a first insulating layer LC2, a semiconductor layer ACT, a second conductive layer LC3, a second insulating layer LC4, and a third conductive layer LC5 formed in sequence; the first conductive layer LC1 includes: a first selection control signal line MUX_1, a second selection control signal line MUX_2, a control electrode of the first transistor M1, a control electrode of the second transistor M2, a control electrode of the third transistor M3, and a first plate of the capacitor C; the semiconductor layer ACT includes: an active layer pattern of the first transistor M1, an active layer pattern of the second transistor M2, and an active layer pattern of the third transistor M3 Pattern; the second conductive layer LC3 includes: a first electrode of the first transistor M1, a second electrode of the first transistor M1, a first electrode of the second transistor M2, a second electrode of the second transistor M2, a first electrode of the third transistor M3, and a second electrode of the third transistor M3; the third conductive layer LC5 includes: a first conductive connection pattern DD, a portion of the first conductive connection pattern DD is electrically connected to the second electrode of the first transistor M1 through a via hole penetrating the second insulating layer LC4, and another portion of the first conductive connection pattern DD is electrically connected to the control electrode of the third transistor M3 through a via hole penetrating the second insulating layer LC4 and the first insulating layer LC2.

[0107] In some embodiments, the material of the third conductive layer LC5 includes a transparent conductive material.

[0108] In an actual display substrate, a switching transistor is also provided in the display area of ​​the display substrate. A pixel electrode is provided on the side of the switching transistor away from the base substrate. Of course, both the pixel electrode and the common electrode may be provided at the same time. In the embodiment disclosed herein, the third conductive layer may be the layer structure where the pixel electrode is located, that is, the first conductive connection pattern is provided on the same layer as the pixel electrode. Of course, the third conductive layer may be the layer structure where the common electrode is located, that is, the first conductive connection pattern is provided on the same layer as the common electrode. In this case, the first conductive connection electrode can be prepared simultaneously based on the preparation process of the pixel electrode or the common electrode.

[0109] Based on the same inventive concept, an embodiment of the present disclosure further provides a display substrate, which includes a data selector. For a detailed description of the data selector, please refer to the content in the previous embodiment and will not be repeated here.

[0110] In some embodiments, the display substrate further includes: a base substrate, the base substrate is divided into a display area and a peripheral area located around the display area, and the data selector is located in the peripheral area; a switching transistor is arranged in the display area, and a third conductive layer is arranged on the side of the switching transistor away from the base substrate. The third conductive layer not only includes the first conductive connection pattern in the previous embodiment, but also includes: a pixel electrode and / or a common electrode.

[0111] When the third conductive layer includes both the pixel electrode and the common electrode, that is, the first conductive connection pattern, the pixel electrode, and the common electrode are arranged in the same layer.

[0112] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device, which includes the display substrate provided in the above embodiment. For a detailed description of the display substrate, please refer to the content in the previous embodiment and will not be repeated here.

[0113] The display device provided in the embodiments of the present disclosure may specifically be a structure or product with a display function, such as a liquid crystal display, a tablet, a computer, a mobile phone, or a navigator.

[0114] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A data selection circuit, characterized in that: The data selection circuit is provided with a data signal input terminal and at least two data signal output terminals, wherein the data selection circuit includes: at least two gating circuits corresponding to the data signal output terminals one by one, each gating circuit being provided with a corresponding gating control signal line and a reset control signal line; The gating circuit includes: a control circuit, an adjustment circuit, an output circuit and a reset circuit, wherein the control circuit, the adjustment circuit, the output circuit and the reset circuit are connected to a control node; The control circuit is connected to the corresponding strobe control signal line and is configured to write a valid level voltage to the control node in response to control of the strobe control signal line; the adjustment circuit being connected to the data signal input terminal and configured to receive a reference voltage provided by the data signal input terminal while the control circuit writes the effective level voltage to the control node, and subsequently write an adjustment voltage to the control node when the voltage provided by the data signal input terminal changes from the reference voltage to the data voltage, the adjustment voltage being equal to the difference between the reference voltage and the sum of the effective level voltage and the data voltage; The output circuit is connected to the data signal input terminal and the corresponding data signal output terminal, and is configured to output a corresponding on-state current according to the difference between the voltage at the control node and the voltage at the data signal input terminal; The reset circuit is connected to the corresponding reset control signal line and is configured to write a non-active level voltage to the control node in response to control of the reset control signal line.

2. The data selection circuit according to claim 1, wherein: The control circuit includes a first transistor, the reset circuit includes a second transistor, the output circuit includes a third transistor, and the adjustment circuit includes a capacitor; The control electrode of the first transistor is connected to the corresponding selection control signal line, the first electrode of the first transistor is connected to the effective level voltage supply line, and the second electrode of the first transistor is connected to the control node; The control electrode of the second transistor is connected to the corresponding reset control signal line, the first electrode of the second transistor is connected to the non-active level voltage supply line, and the second electrode of the second transistor is connected to the control node; The control electrode of the third transistor is connected to the control node, the first electrode of the third transistor is connected to the data signal input terminal, and the second electrode of the third transistor is connected to the corresponding data signal output terminal; The first end of the capacitor is connected to the data signal input end, and the second end of the capacitor is connected to the corresponding data signal output end.

3. The data selection circuit according to claim 2, wherein: The effective level voltage supply line connected to the first electrode of the first transistor is the gate control signal line connected to the control electrode of the same first transistor.

4. The data selection circuit according to claim 2, wherein: The non-active level voltage supply line connected to the first electrode of the second transistor is the gate control signal line connected to the control electrode of the first transistor in the same gate circuit.

5. The data selection circuit according to claim 2, wherein: The number of the gating circuits is N, wherein the data signal output end of the first gating circuit to the data signal output end of the Nth gating circuit outputs data in sequence; The reset control signal line configured for the i-th gating circuit is the gating control signal line configured for the i+1-th gating circuit, where 1≤i≤N-1 and i is an integer; The reset control signal line configured for the Nth selection circuit is the selection control signal line configured for the first selection circuit.

6. The data selection circuit according to claim 2, wherein: All transistors in the gating circuit are metal oxide transistors.

7. The data selection circuit according to any one of claims 2 to 6, characterized in that: The number of the gating circuits is 2, and the number of the gating control signal lines is 2; The gate control signal line extends along a first direction, and two gate control signal lines are arranged along a second direction, and the first direction intersects the second direction; The two gating circuits are both located between the two gating control signal lines and arranged along the first direction.

8. The data selection circuit according to claim 7, wherein: The two gating circuits are respectively a first gating circuit and a second gating circuit, and the two gating control signal lines are respectively a first gating control signal line and a second gating control signal line; In the first gating circuit, a first electrode of the first transistor is connected to a first gating control signal line as a voltage supply line having an effective level, a first electrode of the second transistor is connected to a second gating control signal line as a voltage supply line having an ineffective level, and the second transistor is located on a side of the first transistor away from the first gating control signal line; In the second selection circuit, the effective level voltage supply line connected to the first electrode of the first transistor is the second selection control signal line, the ineffective level voltage supply line connected to the first electrode of the second transistor is the first selection control signal line, and the second transistor is located on the side of the first transistor away from the second selection control signal line.

9. The data selection circuit according to claim 8, wherein: In any one of the gating circuits, the first transistor and the second transistor are arranged along the second direction, and the third transistor and the first transistor are arranged along a third direction, which intersects with the second direction.

10. The data selection circuit according to claim 8, wherein: The data selection circuit includes: a first conductive layer, a first insulating layer, a semiconductor layer, and a second conductive layer formed in sequence; The first conductive layer includes: the first gate control signal line, the second gate control signal line, the control electrode of the first transistor, the control electrode of the second transistor, the control electrode of the third transistor, and the first plate of the capacitor; The semiconductor layer includes: an active layer pattern of the first transistor, an active layer pattern of the second transistor, and an active layer pattern of the third transistor; The second conductive layer includes: a first electrode of the first transistor, a second electrode of the first transistor, a first electrode of the second transistor, a second electrode of the second transistor, a first electrode of the third transistor, and a second electrode of the third transistor; The second electrode of the first transistor is connected to the control electrode of the third transistor through a via hole penetrating the first insulating layer.

11. The data selection circuit according to claim 8, wherein: The data selection circuit includes a first conductive layer, a first insulating layer, a semiconductor layer, a second conductive layer, a second insulating layer and a third conductive layer which are formed in sequence; The first conductive layer includes: the first gate control signal line, the second gate control signal line, the control electrode of the first transistor, the control electrode of the second transistor, the control electrode of the third transistor, and the first plate of the capacitor; The semiconductor layer includes: an active layer pattern of the first transistor, an active layer pattern of the second transistor, and an active layer pattern of the third transistor; The second conductive layer includes: a first electrode of the first transistor, a second electrode of the first transistor, a first electrode of the second transistor, a second electrode of the second transistor, a first electrode of the third transistor, and a second electrode of the third transistor; The third conductive layer includes: a first conductive connection pattern, a portion of the first conductive connection pattern is electrically connected to the second electrode of the first transistor through a via hole penetrating the second insulating layer, and another portion of the first conductive connection pattern is electrically connected to the control electrode of the third transistor through a via hole penetrating the second insulating layer and the first insulating layer.

12. The data selection circuit according to claim 11, wherein: The material of the third conductive layer includes a transparent conductive material.

13. A display substrate, characterized in that: include: A data selection circuit as claimed in any one of claims 1 to 11.

14. The display substrate according to claim 13, wherein: The display substrate further comprises: a base substrate, the base substrate being divided into a display area and a peripheral area located around the display area, the data selection circuit being located in the peripheral area; A switching transistor is provided in the display area; The data selection circuit further includes a third conductive layer, which is arranged on a side of the switch transistor away from the base substrate. The third conductive layer further includes: a pixel electrode and / or a common electrode.

15. A display device, characterized in that: include: A display substrate as claimed in claim 13 or 14.

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