Method of forming a semiconductor structure
By depositing and doping the reactive material layer in the semiconductor structure, the problem of inconsistent reactive layer thickness was solved, high-quality formation of metal silicide layer was achieved, contact resistance was reduced, and the performance of semiconductor structure was improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SEMICON MFG INT (SHANGHAI) CORP
- Filing Date
- 2021-09-07
- Publication Date
- 2026-06-26
Smart Images
Figure CN115775770B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a method for forming a semiconductor structure. Background Technology
[0002] With the continuous development of integrated circuit manufacturing technology, people have increasingly higher requirements for the integration level and performance of integrated circuits. In order to improve integration level and reduce costs, the critical dimensions of components are constantly shrinking, and the circuit density inside integrated circuits is increasing. This development makes it impossible for the wafer surface to provide enough area to fabricate the required interconnects.
[0003] To meet the interconnect requirements of reduced critical dimensions, current interconnect structures are used to achieve conduction between different metal layers or between a metal layer and a substrate. Interconnect structures include interconnect lines and contact holes formed within contact openings. The contact holes connect to semiconductor devices, and the interconnect lines connect the contact holes to form a circuit. Contact holes within a transistor structure include gate contact holes located on the surface of the gate structure for connecting the gate structure to external circuitry, and source / drain contact holes located on the surfaces of the source / drain doped layers for connecting the source / drain doped layers to external circuitry. Summary of the Invention
[0004] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure, which is beneficial to improving the performance of the semiconductor structure.
[0005] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, on which a gate structure is formed, source / drain doped layers are formed in the substrate on both sides of the gate structure, and a raised interlayer dielectric layer is formed on the substrate on the side of the gate structure, with openings exposed in the interlayer dielectric layers on both sides of the gate structure; depositing a reactant material layer on the top of the interlayer dielectric layer, the sidewalls of the openings, and the top of the source / drain doped layers; and performing a doping treatment on the reactant material layer, wherein the material layer located between the interlayer dielectric layer and the source / drain doped layers... The doping concentration in the material layer to be reacted at the top of the layer is greater than the doping concentration in the material layer to be reacted located on the sidewall of the opening. After doping the material layer to be reacted, the material layer to be reacted on the sidewall of the opening is removed, and the material layer to be reacted located at the top of the source / drain doped layer is used as the material layer to be reacted. After the material layer to be reacted is formed, it is treated with silicide to transform it into a metal silicide layer. After the metal silicide layer is formed, a source / drain interconnect layer is formed in the opening, and the source / drain interconnect layer is electrically connected to the source / drain doped layer through the metal silicide layer.
[0006] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:
[0007] This invention provides a method for forming a semiconductor structure. A reactive material layer is deposited on top of the interlayer dielectric layer, the sidewall of the opening, and the top of the source / drain doped layer. The reactive material layer is then doped. The deposition method improves the thickness uniformity of the reactive material layer. Furthermore, after doping, the doping concentration in the reactive material layer located on top of the interlayer dielectric layer and the source / drain doped layer is greater than the doping concentration in the reactive material layer located on the sidewall of the opening. By achieving different doping concentrations in the reactive material layer at different locations, an etching selectivity ratio is created between the reactive material layer located on top of the source / drain doped layer and the reactive material layer located on the sidewall of the opening. Correspondingly, in… During the formation of the reaction layer, it is easy to remove the reaction material layer on the opening sidewall and retain the reaction material layer on top of the source / drain doped layer to form a metal silicide layer. Compared with the current method of forming the reaction material layer and then removing the exposed reaction material layer by means of a filler layer formed on top of the reaction material layer to form the reaction layer, the embodiments of the present invention reduce the process difficulty of removing the reaction material layer on the opening sidewall, and at the same time make the top surface of the reaction layer flatter, which improves the formation quality of the metal silicide layer subsequently formed on top of the source / drain doped layer. This reduces the contact resistance between the source / drain interconnect layer and the source / drain doped layer formed in the subsequent process, thereby improving the performance of the semiconductor structure. Attached Figure Description
[0008] Figures 1 to 4 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.
[0009] Figures 5 to 12 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation
[0010] The performance of current semiconductor structures needs improvement. This paper analyzes the reasons why the performance of a semiconductor structure needs further improvement, using a specific semiconductor structure formation method as an example.
[0011] Figures 1 to 4 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.
[0012] refer to Figure 1 A substrate 10 is provided, on which a gate structure (not shown) is formed. Source and drain doped layers 13 are formed in the substrate 10 on both sides of the gate structure. An interlayer dielectric layer 12 is formed on the substrate 10 on the side of the gate structure. An opening 20 is formed in the interlayer dielectric layer 12 between adjacent gate structures to expose the source and drain doped layers 13.
[0013] The substrate 10 includes a first device region 10A and a second device region 10B, and the source and drain doping layers 13 located in the first device region and the second device region 10A and 10B have opposite doping types.
[0014] refer to Figure 2 The source / drain doped layer 13 of a certain thickness is amorphized using an ion implantation process, and a reaction layer 16 is formed on the surface of the remaining source / drain doped layer 13.
[0015] refer to Figure 3 A metal layer 17 is formed on the surface of the layer to be reacted using a selective deposition process.
[0016] refer to Figure 4 Annealing is performed on the reaction layer 16 and the metal layer 17 to react them and form a metal silicide layer 18 on the surface of the source / drain doped layer 103.
[0017] Studies have found that the uniformity of ion implantation results can lead to inconsistent amorphization levels in the source / drain doped layers 13 across different regions, which in turn can result in inconsistent thicknesses of the reaction layer 16 (e.g., ...). Figure 2 (As shown).
[0018] In particular, the source and drain doped layers 13 in the first device region 10A and the second device region 10B have opposite doping types, which further exacerbates the problem of inconsistent amorphization levels between the first device region 10A and the second device region 10B. For example, as Figure 2 As shown, the thickness of the reaction layer 16 in the second device region 10B is greater than the thickness of the reaction layer 16 in the first device region 10A.
[0019] Correspondingly, due to the inconsistent thickness of the reaction layer 16, it is easy for the metal layer 17 to be excessive in some areas, or for the reaction layer 16 to be excessive in some areas.
[0020] Specifically, taking the substrate 10, which includes a first device region 10A and a second device region 10B, as an example, during the formation of the metal silicide layer 18 on top of the source / drain doped layer 13, since the thickness of the reactive layer 16 in the second device region 10B is greater than that in the first device region 10A, when the thickness of the metal layer 17 matches the thickness of the reactive layer 16 in the first device region 10A, there may still be unreacted portions of the reactive layer 16 in the second device region 10B. This results in excessively high contact resistance between the source / drain interconnect layer and the source / drain doped layer 13 subsequently formed in the second device region 10B, thus affecting the performance of the semiconductor structure. Alternatively, when the thickness of the metal layer 17 matches the thickness of the reactive layer 16 in the second device region 10B, there may still be unreacted portions of the metal layer 17 in the first device region 10A. This also results in excessively high contact resistance between the source / drain interconnect layer and the source / drain doped layer 13 subsequently formed in the first device region 10A, thus affecting the performance of the semiconductor structure.
[0021] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, on which a gate structure is formed, source and drain doped layers are formed in the substrate on both sides of the gate structure, and a raised interlayer dielectric layer is formed on the substrate on the side of the gate structure, with openings exposed in the interlayer dielectric layers on both sides of the gate structure; depositing a material layer to be reacted on the top of the interlayer dielectric layer, the sidewalls of the openings, and the top of the source and drain doped layers; and performing a doping treatment on the material layer to be reacted, wherein the material layer located between the interlayer dielectric layer and the source and drain doped layers... The doping concentration in the material layer to be reacted at the top of the doped layer is greater than the doping concentration in the material layer to be reacted located on the sidewall of the opening; after doping the material layer to be reacted, the material layer to be reacted on the sidewall of the opening is removed, and the material layer to be reacted located at the top of the source / drain doped layer is used as the material layer to be reacted; after forming the material layer to be reacted, the material layer to be reacted is treated with silicide to transform the material layer to be reacted into a metal silicide layer; after forming the metal silicide layer, a source / drain interconnect layer is formed in the opening, and the source / drain interconnect layer is electrically connected to the source / drain doped layer through the metal silicide layer.
[0022] This invention provides a method for forming a semiconductor structure. A reactive material layer is deposited on top of the interlayer dielectric layer, the sidewall of the opening, and the top of the source / drain doped layer. The reactive material layer is then doped. The deposition method improves the thickness uniformity of the reactive material layer. Furthermore, after doping, the doping concentration in the reactive material layer located on top of the interlayer dielectric layer and the source / drain doped layer is greater than the doping concentration in the reactive material layer located on the sidewall of the opening. By achieving different doping concentrations in the reactive material layer at different locations, an etching selectivity ratio is created between the reactive material layer located on top of the source / drain doped layer and the reactive material layer located on the sidewall of the opening. Correspondingly, in… During the formation of the reaction layer, it is easy to remove the reaction material layer on the opening sidewall and retain the reaction material layer on top of the source / drain doped layer to form a metal silicide layer. Compared with the current method of forming the reaction material layer and then removing the exposed reaction material layer by means of a filler layer formed on top of the reaction material layer to form the reaction layer, the embodiments of the present invention reduce the process difficulty of removing the reaction material layer on the opening sidewall, and at the same time make the top surface of the reaction layer flatter, which improves the formation quality of the metal silicide layer subsequently formed on top of the source / drain doped layer. This reduces the contact resistance between the source / drain interconnect layer and the source / drain doped layer formed in the subsequent process, thereby improving the performance of the semiconductor structure.
[0023] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0024] Figures 5 to 12 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.
[0025] refer to Figure 5 A substrate (not shown) is provided, on which a gate structure (not shown) is formed. Source and drain doped layers 103 are formed in the substrate on both sides of the gate structure. An interlayer dielectric layer 102 is formed on the substrate on the side of the gate structure. An opening 120 is formed in the interlayer dielectric layer 102 on both sides of the gate structure to expose the source and drain doped layers 103.
[0026] The substrate is used to provide a process platform for subsequent process manufacturing.
[0027] In this embodiment, the substrate is used to form a fin field-effect transistor (FinFET). The substrate includes a substrate 100 and fins 101 protruding from the substrate 100. In other embodiments, when the substrate is used to form a planar field-effect transistor, the substrate is correspondingly a planar substrate.
[0028] In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate may also be made of germanium, silicon carbide, gallium arsenide, or indium gallium phosphate, and may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
[0029] In this embodiment, the material of the fin 101 is the same as the material of the substrate 100, which is silicon. Specifically, the fin 101 and the substrate 100 are an integral structure. In other embodiments, the materials of the fin and the substrate may be different. The appropriate material is selected for the fin according to the performance requirements of the transistor.
[0030] When the device is in operation, the gate structure is used to control the opening or closing of the conductive channel.
[0031] In this embodiment, the gate structure is located on the substrate 100, and the gate structure spans the fin 101 and covers part of the top and part of the sidewall of the fin 101.
[0032] In this embodiment, the gate structure is a metal gate structure, and the gate structure 104 includes a gate dielectric layer and a gate electrode layer covering the gate dielectric layer.
[0033] The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3; the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.
[0034] In this embodiment, the source / drain doped layer 103 is located in the fins 101 on both sides of the gate structure.
[0035] It should be noted that, for ease of illustration, this embodiment only shows the source / drain doped layer 103 on one side of the gate structure for the first device region 100A or the second device region 100B. It can be understood that source / drain doped layers 103 are formed on both sides of the gate structure.
[0036] In this embodiment, the substrate includes a first device region 100A and a second device region 100B, and the source and drain doping layers 103 located in the first device region 100A and the second device region 100B have opposite doping types.
[0037] Specifically, when the first device region 100A is used to form a PMOS transistor, the material of the source / drain doped layer 103 located in the first device region 100A is silicon germanide doped with P-type ions, wherein the P-type ions include B, Ga, or In. When the second device region 100B is used to form an NMOS transistor, the material of the source / drain doped layer 103 located in the second device region 100B is silicon carbide or silicon doped with N-type ions, wherein the N-type ions include P, As, or Sb.
[0038] In other embodiments, the first device region is used to form an NMOS transistor, and the second device region is used to form a PMOS transistor. Accordingly, the material of the source / drain doped layer in the first device region is silicon carbide or silicon doped with N-type ions, and the material of the source / drain doped layer in the second device region is silicon germanide doped with P-type ions.
[0039] In other embodiments, the doping type of the source / drain doped layers 103 located in the first device region and the second device region may be the same.
[0040] The interlayer dielectric layer 102 is used to isolate adjacent devices.
[0041] In this embodiment, the material of the interlayer dielectric layer 102 is an insulating material, and the material of the interlayer dielectric layer 102 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxycarbide, silicon carbonitride, and silicon carbonitride. In this embodiment, the material of the interlayer dielectric layer 102 is silicon oxide.
[0042] The opening 120 provides space for the subsequent formation of the metal silicide layer and the source / drain interconnect layer.
[0043] In this embodiment, the process for forming the opening 120 includes a dry etching process. Specifically, after forming an interlayer dielectric layer 102 covering the sidewalls of the gate structure on the substrate on the side of the gate structure, the interlayer dielectric layers 102 on both sides of the gate structure are etched to form the opening 120.
[0044] The dry etching process includes anisotropic dry etching, which has the characteristics of anisotropic etching. That is, the longitudinal etching rate is greater than the lateral etching rate, which can remove the interlayer dielectric layer 106 on top of the source / drain doped layer while ensuring the morphology quality of the sidewalls of the opening 120.
[0045] refer to Figure 6 A reaction material layer 104 is deposited on top of the interlayer dielectric layer 102, on the sidewall of the opening 120, and on top of the source / drain doped layer 103.
[0046] The material layer 104 to be reacted provides the process basis for the subsequent formation of the reaction layer.
[0047] It should be noted that the thickness of the reactant material layer 104 should not be too large or too small. If the thickness of the reactant material layer 104 is too large, it increases the difficulty of the subsequent removal of the reactant material layer 104 from the sidewall of the opening 120. Simultaneously, during the subsequent formation of the metal silicide layer, the thickness of the metal silicide layer will also be too large, resulting in increased contact resistance between the subsequently formed source / drain interconnect layer and the source / drain doped layer 103, thus affecting the performance of the semiconductor structure. If the thickness of the reactant material layer 104 is too small, the thickness of the subsequently formed metal silicide layer will also be too small, making it difficult to meet the process requirements. Therefore, in this embodiment, the thickness of the reactant material layer 104 is 2 nanometers to 6 nanometers.
[0048] In this embodiment, a deposition process is used to form the material layer 104 to be reacted.
[0049] Compared to the scheme of using ion implantation to amorphize a portion of the source / drain doped layer and forming a reaction layer on the remaining surface of the source / drain doped layer, the method of using deposition to form the reaction material layer 104 ensures that the thickness of the reaction material layer 104 on top of the source / drain doped layer 103 is uniform. This improves the uniformity of the thickness of the reaction material layer 104 on top of the source / drain doped layer 103 in each region. Consequently, it improves the uniformity of the thickness of the metal silicide layer subsequently formed on top of the source / drain doped layer 103, thereby reducing the contact resistance between the subsequently formed source / drain interconnect layer and the source / drain doped layer 103.
[0050] Furthermore, since the thickness uniformity of the reactant material layer 104 at the top of the source / drain doped layer 103 is relatively high, it is easy to form a reactant material layer 104 with a thickness that meets the actual requirements. In the subsequent silicide treatment of the reactant layer, a metal layer with a thickness matching that of the reactant material layer 104 can also be formed, thereby reducing the probability of problems such as excessive reactant material layer 104 or excessive metal layer.
[0051] In this embodiment, the process of forming the reactant material layer 104 on the top of the interlayer dielectric layer 102, the sidewall of the opening 120, and the top of the source / drain doped layer 103 includes atomic layer deposition or chemical vapor deposition.
[0052] The atomic layer deposition (ALD) process involves multiple ALD cycles, which helps improve the thickness uniformity of the reactant material layer 104 and provides good step coverage, allowing the reactant material layer 104 to cover the top of the interlayer dielectric layer 102, the sidewalls of the opening 120, and the top of the source / drain doped layer 103. In other embodiments, the reactant material layer can also be formed using chemical vapor deposition (CVD).
[0053] In this embodiment, the material of the reactant layer 104 includes amorphous silicon.
[0054] The material of the reactant layer 104 needs to meet the following requirements: the reactant layer 104 is easy to remove from the sidewall of the opening 120, and the process of removing the reactant layer 104 from the sidewall of the opening 120 causes minimal damage to other film layers. Furthermore, the material of the reactant layer 104 is a material capable of silicide treatment.
[0055] Therefore, the material of the reactant layer 104 includes amorphous silicon. Amorphous silicon can react with metals during the annealing process, and its crystal orientation is irregular, exhibiting instability, making it easy to remove the amorphous silicon from the sidewalls of the opening 120.
[0056] It should be noted that the material to be reacted 104 is formed by a deposition process in this embodiment, so the material of the material to be reacted 104 can be flexibly selected to meet the process requirements of silicide treatment and the performance requirements of the device.
[0057] refer to Figure 7 The reactant material layer 104 is doped, wherein the doping concentration in the reactant material layer 104 located at the top of the interlayer dielectric layer 102 and the source / drain doped layer 103 is greater than the doping concentration in the reactant material layer 104 located on the sidewall of the opening 120.
[0058] Specifically, by making the reactant material layer 104 at different locations have different doping concentrations, an etching selectivity ratio is generated between the reactant material layer 104 located on top of the source / drain doped layer 103 and the reactant material layer 104 located on the sidewall of the opening 120. Accordingly, in the subsequent formation of the reactant layer, it is easy to remove the reactant material layer 104 on the sidewall of the opening 120 and retain the reactant material layer 104 on top of the source / drain doped layer 103 to form a metal silicide layer.
[0059] In this embodiment, the doping ions include B ions.
[0060] After doping the reactant material layer 104, the ion-doped reactant material layer 104 is not easily removed by the etching solution in the subsequent wet etching process. Therefore, compared with the undoped reactant material layer 104, the etching rate of the ion-doped reactant material layer 104 is reduced, and the higher the doping concentration, the lower the etching rate. For this reason, in this embodiment, the doping ions include boron ions.
[0061] In this embodiment, the step of doping the material layer 104 to be reacted includes: performing an ion implantation process on the material layer 104 to be reacted, wherein the implantation direction of the ion implantation process is perpendicular to the substrate surface.
[0062] Specifically, the ion implantation process is a process of implanting ions accelerated to a certain high energy into the surface layer of a solid material to change the physical and chemical properties of the surface layer. It has the characteristics of high efficiency and strong modified layer.
[0063] During ion implantation of the reactant material layer 104, ion implantation is performed in a direction perpendicular to the surface of the substrate 100. Under the same ion implantation process environment, the ion implantation depth of the reactant material layer 104 located at the top of the interlayer dielectric layer 102 and the source / drain doped layer 103 is less than the ion implantation depth of the reactant material layer 104 located on the sidewall of the opening 120. This results in a higher doping concentration in the reactant material layer 104 located at the top of the interlayer dielectric layer 102 and the source / drain doped layer 103 than in the reactant material layer 104 located on the sidewall of the opening 120. Consequently, the etching rate of the reactant material layer 104 located on the sidewall of the opening 120 is greater than that of the reactant material layer 104 located at the top of the source / drain doped layer 103 and the interlayer dielectric layer 102. This reduces the process difficulty of removing the reactant material layer 104 from the sidewall of the opening 120, simplifies the process steps, and reduces process costs.
[0064] It should be noted that the ion implantation energy should not be too high or too low. If the ion implantation energy is too high, the probability of implanted ions entering the substrate will increase, thus affecting the performance of the semiconductor structure. If the ion implantation energy is too low, the etching selectivity between the reactant material layer 104 on the sidewall of the opening 120 and the reactant material layer 104 on top of the source / drain doped layer 103 may not meet the process requirements, thereby increasing the difficulty of subsequent removal of the reactant material layer 104 on the sidewall of the opening 120. Therefore, in this embodiment, the ion implantation energy is 1 keV to 3 keV.
[0065] It should also be noted that the ion implantation dose should not be too high or too low. If the ion implantation dose is too high, the ion concentration implanted in the reactive material layer 104 on top of the source / drain doped layer 103 will be too high, resulting in a higher contact resistance between the subsequently formed source / drain interconnect layer and the source / drain doped layer 103, thus affecting the performance of the semiconductor structure. If the ion implantation dose is too low, the etching selectivity between the reactive material layer 104 on the sidewall of the opening 120 and the reactive material layer 104 on top of the source / drain doped layer 103 will not meet the process requirements, thus increasing the difficulty of subsequently removing the reactive material layer 104 on the sidewall of the opening 120. Therefore, in this embodiment, the ion implantation dose range is 1E15 atom / cm 2 Up to 8E15atom / cm 2 .
[0066] refer to Figure 8 After doping the material layer 104 to be reacted, the material layer 104 to be reacted on the sidewall of the opening 120 is removed, and the material layer 104 to be reacted located on the top 103 of the source and drain doped layer is used as the material layer 105 to be reacted.
[0067] The reaction layer 105 provides the process basis for the subsequent formation of the metal silicide layer.
[0068] In this embodiment, the process of removing the reactive material layer 104 from the sidewall of the opening 120 includes a wet etching process.
[0069] The wet etching process is characterized by isotropic etching, with features such as strong etching target, high etching efficiency, and strong lateral etching capability. It can reduce damage to the reactant material layer 104 at the bottom of the opening 120 during the lateral removal of the reactant material layer 104 on the sidewall of the opening 102, so that the reactant material layer 104 with sufficient thickness can be transformed into a metal silicide layer in the subsequent silicide processing.
[0070] Moreover, the wet etching process has a high etching selectivity for the reactant material layer 104 with different doping concentrations, so that after removing the reactant material layer 104 on the sidewall of the opening 120, the reactant material layer 104 located on the top 103 of the source / drain doped layer is retained.
[0071] It should be noted that the etching selectivity ratio between the reactant material layer 104 on the sidewall of the opening 120 and the reactant material layer 104 on the top of the source / drain doped layer 103 should not be too small. If the etching selectivity ratio between the reactant material layer 104 on the sidewall of the opening 120 and the reactant material layer 104 on the top of the source / drain doped layer 103 is too small, the reactant material layer 104 on top of the source / drain doped layer 103 may also be easily removed during the removal of the reactant material layer 104 on the sidewall of the opening 120, thus affecting the formation quality of the metal silicide layer subsequently formed on top of the source / drain doped layer 103. Therefore, in this embodiment, the etching selectivity ratio between the reactant material layer 104 on the sidewall of the opening 120 and the reactant material layer 104 on the top of the source / drain doped layer 103 is greater than 20:1.
[0072] In this embodiment, the solution used in the wet etching process includes ammonia.
[0073] Ammonia solution readily reacts with amorphous silicon, but it does not readily react with amorphous silicon doped with boron ions. This results in a large etching selectivity between the material layer 104 to be reacted on the sidewall of the opening 120 and the material layer 104 to be reacted on the top of the source / drain doped layer 103, thereby enabling the removal of the material layer 104 to be reacted on the sidewall of the opening 120 by the ammonia solution.
[0074] It should be noted that the ion implantation process is performed on the material layer 104 to be reacted, and the implantation direction of the ion implantation process is perpendicular to the substrate surface. The doping concentration of the material layer 104 to be reacted at the top of the interlayer dielectric layer 106 is also relatively high. Therefore, the material layer 104 to be reacted at the top of the interlayer dielectric layer 106 is also used as the material layer 105 to be reacted after the sidewall of the opening 120 is removed.
[0075] refer to Figures 9 to 10 After forming the reaction layer 105, the reaction layer 105 is subjected to silicide treatment to transform the reaction layer 105 into a metal silicide layer 107.
[0076] The metal silicide layer 107 can reduce the contact resistance between the subsequently formed source / drain interconnect layer and the source / drain doped layer 103.
[0077] In this embodiment, the step of performing silicide treatment on the reaction layer 105 to convert the reaction layer 105 into a metal silicide layer 107 includes: as follows Figure 9 As shown, a selective deposition process is used to form a metal layer 106 on the surface of the reaction layer 105; as Figure 10As shown, the metal layer 106 and the reaction layer 105 are annealed to react the reaction layer 105 and the metal layer 106 to form a metal silicide layer 107 located on the surface of the source / drain doped layer 103.
[0078] In this embodiment, the material of the metal layer 106 includes one or more of titanium, nickel, and platinum.
[0079] Titanium, nickel, and platinum possess properties such as high electrical conductivity and hardness, enabling them to react with the reactant layer 105 to form a metal silicide layer 107. This not only satisfies the electrical connection requirements between the source / drain interconnect layer and the source / drain doped layer 103, but also allows the reacted metal silicide layer 107 to protect the source / drain doped layer 103. Furthermore, using these materials facilitates the formation of the metal layer 106 using a selective deposition process.
[0080] In this embodiment, the metal layer 106 is formed using a selective deposition process.
[0081] Specifically, during the selective deposition process to form the metal layer 106, the deposition rate of the metal layer 106 on the surface of the reactant layer 105 is greater than the deposition rate on the sidewall of the opening 120. Because the metal layer 106 is thinner, the metal layer 120 deposited on the sidewall of the opening 120 is also thinner. Furthermore, in the subsequent cleaning process, the small amount of metal layer 120 formed on the sidewall of the opening 120 is completely removed.
[0082] In this embodiment, the selective deposition process includes pulsed plasma deposition.
[0083] In this embodiment, the material of the metal silicide layer includes one or more of TiSi, NiSi, and CoSi.
[0084] TiSi, NiSi, and CoSi possess properties such as high conductivity and high hardness. While fulfilling the electrical connection function between the source / drain interconnect layer and the source / drain doped layer 103, they can also ensure protection of the top of the source / drain doped layer 103.
[0085] It should be noted that in the step of converting the reaction layer 105 into a metal silicide layer 107, the reaction layer 105 located on top of the interlayer dielectric layer 106 will also be converted into a metal silicide layer 107.
[0086] refer to Figures 11 to 12 After the metal silicide layer 107 is formed, a source-drain interconnect layer 108 is formed in the opening 120. The source-drain interconnect layer 108 is electrically connected to the source-drain doped layer 103 through the metal silicide layer 107.
[0087] The source-drain interconnect layer 108 is used to realize the electrical connection between the source-drain doped layer 1003 and external circuits or other interconnect structures.
[0088] In this embodiment, the step of forming the source-drain interconnect layer 108 in the opening 120 includes: as follows Figure 11 As shown, a conductive material layer 130 is formed in the opening 120, and the conductive material layer 130 also covers the top of the interlayer dielectric layer 102; as Figure 12 As shown, with the top of the interlayer dielectric layer 102 as the stop position, the conductive material layer 130 above the top of the interlayer dielectric layer 102 is planarized, and the remaining conductive material layer 130 located in the opening 120 serves as the source-drain interconnect layer 108.
[0089] It should be noted that the planarization process for the conductive material layer 130 above the top of the interlayer dielectric layer 102 also includes: removing the metal silicide layer 107 above the top of the interlayer dielectric layer 102.
[0090] In this embodiment, the planarization process for the conductive material layer 130 above the top of the interlayer dielectric layer 102 includes a chemical mechanical polishing process.
[0091] In this embodiment, the source-drain interconnect layer 108 is made of tungsten. Tungsten has low resistivity, which helps to improve the signal delay of the subsequent RC circuit and increase the processing speed of the chip. It also helps to reduce the resistance of the source-drain interconnect layer 108, thereby reducing power consumption. In other embodiments, the source-drain interconnect layer can also be made of conductive materials such as molybdenum or ruthenium.
[0092] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a substrate, a gate structure is formed on the substrate, source and drain doped layers are formed in the substrate on both sides of the gate structure, a raised interlayer dielectric layer is formed on the substrate on the side of the gate structure, and openings are formed in the interlayer dielectric layers on both sides of the gate structure to expose the source and drain doped layers. A layer of material to be reacted is deposited on top of the interlayer dielectric layer, on the sidewall of the opening, and on top of the source / drain doped layer; The material layer to be reacted is doped using an ion implantation process, and the implantation direction of the ion implantation process is perpendicular to the substrate surface. The doping concentration in the material layer to be reacted located at the top of the interlayer dielectric layer and the source / drain doped layer is greater than the doping concentration in the material layer to be reacted located at the opening sidewall. After doping the material layer to be reacted, the material layer to be reacted on the opening sidewall is removed, and the material layer to be reacted located on top of the source / drain doped layer is used as the material layer to be reacted. After the reaction layer is formed, the reaction layer is subjected to silicide treatment to transform the reaction layer into a metal silicide layer. After the metal silicide layer is formed, a source-drain interconnect layer is formed in the opening, and the source-drain interconnect layer is electrically connected to the source-drain doped layer through the metal silicide layer.
2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of treating the layer to be reacted with silicide to transform it into a metal silicide layer includes: forming a metal layer on the surface of the layer to be reacted using a selective deposition process; and annealing the metal layer and the layer to be reacted to form a metal silicide layer located on the surface of the source / drain doped layer.
3. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of doping the material layer to be reacted, the doping ions include B ions.
4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The parameters of the ion implantation process include: ion implantation energy ranging from 1 keV to 3 keV; and ion implantation dose ranging from 1 E15 atom / cm2 to 8 E15 atom / cm2.
5. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of depositing the material layer to be reacted, the thickness of the material layer to be reacted is 2 nanometers to 6 nanometers.
6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process of depositing the reactant material layer on top of the interlayer dielectric layer, the sidewall of the opening, and the top of the source / drain doped layer includes atomic layer deposition or chemical vapor deposition.
7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process for removing the reactive material layer from the sidewall of the opening includes a wet etching process.
8. The method for forming a semiconductor structure as described in claim 7, characterized in that, The solution used in the wet etching process includes ammonia.
9. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming a source-drain interconnect layer in the opening includes: forming a conductive material layer in the opening, the conductive material layer further covering the top of the interlayer dielectric layer; using the top of the interlayer dielectric layer as a stop position, planarizing the conductive material layer above the top of the interlayer dielectric layer, and the remaining conductive material layer in the opening serves as the source-drain interconnect layer.
10. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of depositing the reactive material layer, the material of the reactive material layer includes amorphous silicon.
11. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of treating the reaction layer with silicide, the material of the metal silicide layer includes one or more of TiSi, NiSi, and CoSi.
12. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of providing a substrate, the substrate includes a first device region and a second device region, and the source and drain doping layers located in the first device region and the second device region have opposite doping types.