Device with Electrostatic Discharge Protection Structure and Method for Manufacturing the Same

Abstract

The present invention relates to a device with an electrostatic discharge protection structure and a manufacturing method thereof. The device includes a device region and an ESD region. The device region includes: a substrate; an insulating layer provided on the substrate; a device active region layer provided on the insulating layer. The ESD region includes: a semiconductor layer connected to the substrate; a second conductivity type well region provided in the semiconductor layer; a first doped region provided on the surface of the second conductivity type well region; a second doped region provided on the surface of the second conductivity type well region. Among them, the first doped region serves as the emitter of the first triode, the semiconductor layer serves as the emitter of the second triode, the second doped region serves as the collector of the first triode and the second triode, and the second conductivity type well region serves as the base of the first triode and the second triode. The present invention can avoid the failure of the ESD protection structure due to thermal breakdown caused by poor heat dissipation. The ESD region has two current discharge paths, improving the current discharge efficiency and having a high ESD protection ability.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and particularly to a device with an electrostatic discharge protection structure, and also to a manufacturing method of a device with an electrostatic discharge protection structure. Background Art

[0002] SOI (Silicon on Insulator) refers to the silicon-on-insulator technology. The SOI process technology is a fully dielectric isolation technology. Devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs) are fabricated on the top silicon film, and there is an oxide layer between the top silicon film and the substrate for isolation. This technology completely eliminates the latch-up effect of the traditional bulk silicon process, has small parasitic capacitance, and has advantages such as high speed, low power consumption, high integration, and high reliability.

[0003] Since the MOS device is formed above the buried oxide layer, together with the shallow trench isolation (STI, Shallow Trench Isolation) structure on the buried oxide layer, the MOS device is completely isolated by the thick oxide layer, and the heat dissipation ability of the silicon dioxide material is extremely poor, far inferior to that of the silicon material. Therefore, heat is easily accumulated in the silicon film, and the SOI self-heating effect "self-heating" will become a new problem.

[0004] Electrostatic discharge (ESD) failure is one of the most common problems faced by the electronics industry in terms of reliability. It is statistically shown that up to 35% of the integrated circuit failures are caused by ESD, resulting in losses to the electronics industry in billions of dollars every year. Therefore, protecting the device is crucial for the stability and safe operation of the integrated circuit, and the industry's requirements for ESD protection diodes are getting higher and higher.

[0005] From the perspective of ESD protection analysis, thermal breakdown is the most main failure mode of ESD protection devices. Once heat accumulates in the silicon film, the "self-heating effect" will cause irreversible damage to the protection device, and the MOS circuit will lose ESD protection. Summary of the Invention

[0006] Based on this, it is necessary to provide a device with an electrostatic discharge protection structure.

[0007] A device with an electrostatic discharge protection structure includes a device area and an ESD area. The device area includes: a substrate having a first conductivity type; an insulating layer provided on the substrate; a device active region layer provided on the insulating layer. The ESD area includes: a semiconductor layer connected to the substrate and having a first conductivity type; a second conductivity type well region provided in the semiconductor layer; a first doping region having a first conductivity type provided on the surface of the second conductivity type well region; a second doping region having a first conductivity type provided on the surface of the second conductivity type well region. Among them, the first doping region serves as the emitter of the first triode, the semiconductor layer serves as the emitter of the second triode, the second doping region serves as the collector of the first triode and the second triode, and the second conductivity type well region serves as the base of the first triode and the second triode. The first conductivity type and the second conductivity type are opposite conductivity types.

[0008] In one embodiment, the device is a silicon-on-insulator device, the substrate is a silicon substrate, the device active region layer is a top silicon layer, and the semiconductor layer is a silicon epitaxial layer.

[0009] In one embodiment, the insulating layer is a buried oxide layer.

[0010] In one embodiment, it further includes a third doping region located in the second conductivity type well region. The third doping region is located below the second doping region and is in direct contact with the second doping region. The third doping region has a first conductivity type.

[0011] In one embodiment, it further includes a first isolation structure provided between the first doping region and the second doping region.

[0012] In one embodiment, it further includes a second isolation structure provided at the junction of the device area and the ESD area. The bottom of the second isolation structure extends to the insulating layer.

[0013] In one embodiment, the first isolation structure is a shallow trench isolation structure.

[0014] In one embodiment, a metal oxide semiconductor field effect transistor is provided in the device area.

[0015] In one embodiment, the device is a fully depleted silicon-on-insulator device. The source region and the drain region of the metal oxide semiconductor field effect transistor are provided in the device active region layer, and the bottoms of the source region and the drain region extend to the insulating layer.

[0016] In one embodiment, the first conductivity type is N-type and the second conductivity type is P-type.

[0017] It is also necessary to provide a method for manufacturing a device with an electrostatic discharge protection structure.

[0018] A method for manufacturing a device with an electrostatic discharge protection structure includes: obtaining a substrate; the substrate includes a substrate, an insulating layer, and an active region layer stacked in sequence, and the substrate has a first conductivity type; removing the active region layer and the insulating layer in the ESD region to expose the substrate in the ESD region; filling a semiconductor material in the positions where the active region layer and the insulating layer are removed to form a semiconductor layer, and the semiconductor layer has a first conductivity type; forming a second conductivity type well region, a first doping region, and a second doping region on the semiconductor layer, the first doping region and the second doping region are formed on the surface of the second conductivity type well region, and the first doping region and the second doping region have a first conductivity type; wherein, the first doping region serves as the emitter of the first triode, the substrate in the ESD region serves as the emitter of the second triode, the second doping region serves as the collector of the first triode and the second triode, and the second conductivity type well region serves as the base of the first triode and the second triode; the first conductivity type and the second conductivity type are opposite conductivity types.

[0019] In one embodiment, the device is a silicon-on-insulator device, the substrate is a silicon substrate, and the active region layer is a top silicon layer; before the step of removing the active region layer and the insulating layer in the ESD region, there is also a step of forming a silicon oxide layer on the surface of the top silicon layer; the step of filling a semiconductor material in the positions where the active region layer and the insulating layer are removed to form a semiconductor layer includes forming the semiconductor layer by an epitaxial process.

[0020] In one embodiment, the step of removing the active region layer and the insulating layer in the ESD region includes removing the silicon oxide layer, the active region layer, and the insulating layer in the ESD region by photolithography and dry etching.

[0021] In one embodiment, there is also a step of removing the silicon oxide layer and the excess semiconductor layer by chemical mechanical polishing so that the surface of the semiconductor layer is flush with the surface of the active region layer.

[0022] For the above device with an electrostatic discharge protection structure and its manufacturing method, the front and back of the ESD region are not isolated by an insulating layer, which can avoid the thermal breakdown and failure of the ESD protection structure due to poor heat dissipation. The ESD region has a horizontal first triode and a vertical second triode as the ESD protection device, so that there are two current discharge paths when the ESD protection device operates, improving the current discharge efficiency and having a high ESD protection ability. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] To better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the presently described embodiments and / or examples, and the presently understood best mode of these inventions.

[0024] Figure 1 is a schematic diagram of an equivalent triode structure of an ESD protection structure of a device with an electrostatic discharge protection structure in an embodiment;

[0025] Figure 2 is a schematic diagram of a current discharge path of an ESD protection structure of a device with an electrostatic discharge protection structure in an embodiment;

[0026] Figures 3a - 3k is a cross-sectional schematic diagram of a device during the process of manufacturing a device with an electrostatic discharge protection structure in an embodiment;

[0027] Figure 4 is a flowchart of a manufacturing method of a device with an electrostatic discharge protection structure in an embodiment;

[0028] Figure 5a is a schematic diagram of the structure of an exemplary fully depleted SOI MOS device, Figure 5b is a schematic diagram of the structure of an exemplary "H" gate structure. Detailed Description of the Embodiments

[0029] To facilitate understanding of the present invention, the present invention will be described more comprehensively below with reference to the relevant accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present invention is thorough and comprehensive.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this invention belongs. The terms used herein in the specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0031] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or portion from another. Thus, a first element, component, region, layer, or portion discussed below may be denoted as a second element, component, region, layer, or portion without departing from the teachings of the present invention.

[0032] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. are used herein for convenience in describing the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are intended to also encompass different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "under" or "beneath" or "below" another element or feature will be oriented as "above" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0033] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present invention. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0034] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the invention. As such, variations from the shapes as shown are to be expected, for example, due to manufacturing techniques and / or tolerances. Accordingly, embodiments of the invention should not be limited to the specific shapes of regions shown herein, but include shape deviations, for example, due to manufacturing. For example, an implantation region shown as rectangular will typically have rounded or curved features and / or an implantation concentration gradient at its edges, rather than a binary change from the implantation region to the non-implantation region. Similarly, a buried region formed by implantation can result in some implantation in the region between the buried region and the surface through which the implantation occurs. Thus, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the invention.

[0035] The semiconductor field-related terms used herein are common technical terms for those skilled in the art. For example, for P-type and N-type impurities, to distinguish the doping concentrations, simply, P+ type represents P-type with a high doping concentration, P type represents P-type with a medium doping concentration, P- type represents P-type with a low doping concentration, N+ type represents N-type with a high doping concentration, N type represents N-type with a medium doping concentration, and N- type represents N-type with a low doping concentration.

[0036] According to the thickness relationship between the device depletion region and the top silicon film, silicon-on-insulator metal-oxide-semiconductor field-effect transistors (SOI MOS) devices are divided into fully depleted SOI (Full Depleted SOI) and partially depleted SOI (Partial Depleted SOI). Referring to Figure 5a , for fully depleted SOI devices, since the silicon film is very thin, the N+ at the source and drain diffuses to the buried oxide layer (BOX) at the bottom, isolating the P well (PW), making it difficult to achieve an effective body contact. To achieve the body contact extraction of fully depleted SOI devices, one method is to use an "H"-type body contact structure, as shown in Figure 5b . The disadvantage of this structure is that it increases the layout area of the MOS transistor and reduces the integration degree of the integrated circuit, so the cost is relatively high.

[0037] Figure 1 is a schematic diagram of the equivalent triode structure of the ESD protection structure of a device with an electrostatic discharge protection structure in an embodiment, Figure 2 is a schematic diagram of the current discharge path of the ESD protection structure of a device with an electrostatic discharge protection structure in an embodiment. As shown in Figure 1 , a device with an electrostatic discharge protection structure includes a device region and an ESD region; please also refer to Figure 2, where the device region includes a substrate 110, an insulating layer 120, and a device active region layer 130. The substrate 110 has a first conduction type, the insulating layer 120 is disposed on the substrate 110, and the device active region layer 130 is disposed on the insulating layer 120. Devices such as metal oxide semiconductor field effect transistors can be provided in the device region, and structures such as the active region and well region of the device can be provided in the device active region layer 130. The ESD region is used to form an ESD protection structure, including a semiconductor layer 112, a second conduction type well region 152, a first doping region 154, and a second doping region 156. The semiconductor layer 112 is connected to the substrate 110 and has a first conduction type. The second conduction type well region 152 is disposed in the semiconductor layer 112. The first doping region 154 and the second doping region 156 have a first conduction type and are disposed on the surface of the second conduction type well region 152.

[0038] In Figure 1 and Figure 2 In the illustrated embodiment, the first conduction type is N-type, the second conduction type is P-type, the first doping region 154 and the second doping region 156 are N+ regions, the substrate 110 is an N+ substrate, and the doping concentration of the semiconductor layer 112 can be lower than that of the substrate 110. In other embodiments, the first conduction type can also be P-type, and the second conduction type is correspondingly N-type.

[0039] The ESD protection structure includes a first triode and a second triode. The first doping region 154 serves as the emitter of the first triode, the substrate 110 of the ESD region serves as the emitter of the second triode, the second doping region 156 serves as the collector of the first triode and the second triode, and the second conduction type well region 152 serves as the base of the first triode and the second triode. In Figure 1 the illustrated embodiment, both the first triode and the second triode are NPN triodes.

[0040] When the ESD protection structure is working (i.e., it has been deployed and can perform ESD protection), the emitters and bases of the first triode and the second triode are grounded (i.e., the second conduction type well region 152 and the substrate 110 of the ESD region are grounded), and the collectors of the first triode and the second triode (i.e., the second doping region 156) are connected to the position where the integrated circuit needs ESD protection, i.e., connected to a positive voltage during operation. In the initial stage of ESD operation (i.e., when static electricity just conducts to the ESD protection structure), mainly the lateral first triode works. In the later stage of ESD (i.e., when static electricity discharge is nearly completed), mainly the vertical second triode works.

[0041] For the above device with an electrostatic discharge (ESD) protection structure, the front and back of the ESD region are not isolated by the insulating layer 120, and heat can be longitudinally dissipated through the substrate 110, thus avoiding the thermal breakdown and failure of the ESD protection structure due to poor heat dissipation. The ESD region has a lateral first triode and a longitudinal second triode as ESD protection devices, so that there are two current discharge paths when the ESD protection devices operate, improving the current discharge efficiency and having a high ESD protection ability. It can achieve a high ESD protection ability of 4 kV or even above 10 kV, realizing a qualitative leap in the ESD protection ability. Moreover, the body contact lead-out of the above device with an electrostatic discharge protection structure is not affected by the thickness of the SOI top silicon film, and is applicable to both fully depleted SOI and partially depleted SOI processes, meeting the design requirements under different process nodes, having strong compatibility, being applicable to various different process nodes, and being beneficial for developers to design.

[0042] In an embodiment of the present application, the device with an electrostatic discharge protection structure is a SOI device, the substrate 110 is a silicon substrate, the device active region layer 130 is the top silicon layer, the semiconductor layer 112 is a silicon epitaxial layer, and the insulating layer 120 is a buried oxide layer, the material of which can be silicon oxide, such as silicon dioxide.

[0043] See Figure 2 , in this embodiment, the ESD protection structure further includes a third doping region 158 located in the second conductive type well region 152. The third doping region 158 is located below the second doping region 156 and is in direct contact with the second doping region 156, and the third doping region 158 has the second conductive type. By setting the third doping region 158, a Zener diode can be formed between the second doping region 156 and the third doping region 158, increasing the response speed of the first triode and the second triode in the initial stage of operation and achieving a fast response.

[0044] In an embodiment of the present application, a MOSFET is provided in the device region, the device is a fully depleted silicon-on-insulator device, the source region and the drain region of the MOSFET are provided in the device active region layer 130, and the bottoms of the source region and the drain region of the MOSFET extend to the insulating layer 120.

[0045] In Figure 2 In the shown embodiment, the ESD region further includes a first isolation structure 144, and the first isolation structure 144 is provided between the first doping region 154 and the second doping region 156. In an embodiment of the present application, the depth of the bottom of the first isolation structure 144 is shallower than that of the second conductive type well region 152, that is, the bottom of the first isolation structure 144 cannot penetrate downward through the bottom of the second conductive type well region 152. In an embodiment of the present application, the depth of the bottom of the first isolation structure 144 is deeper than that of the first doping region 154 and the second doping region 156. In an embodiment of the present application, the first isolation structure 144 is a STI.

[0046] In Figure 2 the embodiment shown, the device with an electrostatic discharge protection structure further includes a second isolation structure 142. The second isolation structure 142 is provided at the junction of the device area and the ESD area. The bottom of the second isolation structure 142 extends to the insulating layer 120, so as to achieve insulation isolation between the device active region layer 130 and the semiconductor layer 112. In an embodiment of the present application, the second isolation structure 142 is STI.

[0047] Figure 4 is a flowchart of a manufacturing method of a device with an electrostatic discharge protection structure in an embodiment, including the following steps:

[0048] S410, obtain a substrate.

[0049] Refer to Figure 3a , the substrate includes a substrate 110, an insulating layer 120, and a device active region layer 130 stacked in sequence. The substrate 110 has a first conduction type.

[0050] In an embodiment of the present application, the device with an electrostatic discharge protection structure is a SOI device, the substrate 110 is a silicon substrate, the device active region layer ......

[0051] S420, remove the active region layer and the insulating layer in the ESD area.

[0052] In an embodiment of the present application, the device active region layer......

[0053] In Figure 3b the embodiment shown, before step S420, there is also a step of forming a silicon oxide layer 132 on the device active region layer 130. The silicon oxide layer 132 in the ESD area will be removed in step S420. The material of the silicon oxide layer 132 can be silicon dioxide.

[0054] Refer to Figure 3c , the remaining photoresist 21 after lithography covers the device area. Step S420 performs dry etching under the block of the photoresist 21. The etching must penetrate through the thick silicon dioxide dielectric isolation, so that the etched ESD area is all silicon material (substrate material).

[0055] S430, fill a semiconductor material at the position of the removed active region layer and insulating layer to form a semiconductor layer.

[0056] In an embodiment of the present application, a semiconductor layer 112 of the first conduction type is formed by epitaxial growth process. Refer to Figure 3d It should be noted that the content of "the device active region layer ......" in the translation of item and is incomplete in the original text you provided. You may need to check and supplement it for a more accurate translation.。In one embodiment of the present application, the semiconductor layer 112 is N-type silicon. In one embodiment of the present application, the silicon oxide layer 132 can prevent the growth of N-type silicon in the device region during epitaxy. The photoresist 21 can be removed before the epitaxy in step S430.

[0057] In one embodiment of the present application, after epitaxy, the excess semiconductor layer 112 can be polished flat. Specifically, the silicon oxide layer 132 and the excess semiconductor layer 112 can be removed by chemical mechanical polishing (CMP), so that the upper surface of the semiconductor layer 112 is flush with the upper surface of the device active region layer 130, as Figure 3e shown.

[0058] S440, form a second conductive type well region, a first doping region and a second doping region in the semiconductor layer.

[0059] The first doping region 154 and the second doping region 156 are formed on the surface of the second conductive type well region 152, and the first doping region 154 and the second doping region 156 have the first conductive type.

[0060] In one embodiment of the present application, after CMP, it further includes the step of forming a first isolation structure 144 and a second isolation structure 142. Refer to Figure 3f , first form a silicon dioxide layer 134 on the device active region layer 130 and the semiconductor layer 112, and then form a silicon nitride layer 136 on the silicon dioxide layer 134 to prepare for forming the first isolation structure 144 and the second isolation structure 142. Refer to Figure 3g , the second isolation structure 142 is formed at the junction of the device region and the ESD region, and the first isolation structure 144 is used to isolate the first doping region 154 and the second doping region 156. Specifically, trenches can be dug at the positions of the first isolation structure 144 and the second isolation structure 142 through photolithography and etching, and then silicon dioxide is deposited in the trenches to form the first isolation structure 144 and the second isolation structure 142. Since the silicon nitride layer 136 needs to be removed in subsequent steps, the surface of the first isolation structure 144 and the second isolation structure 142 can be etched to be flush with the surface of the silicon dioxide layer 134 by wet etching first (the photoresist formed before the trenches of the first isolation structure 144 and the second isolation structure 142 can be retained until this wet etching step), and then the silicon nitride layer 136 is etched off, as Figure 3h shown. In one embodiment of the present application, the first isolation structure 144 and the second isolation structure 142 are STI.

[0061] In one embodiment of the present application, after forming the first isolation structure 144 and the second isolation structure 142, second conductive type ions can be implanted into the semiconductor layer 112 through photolithography and ion implantation processes to form the second conductive type well region 152, referring to Figure 3i; then, ions of the first conductivity type are implanted into the second conductivity type well region 152 to form a first doped region 154 and a second doped region 156, refer to Figure 3j . Among them, the first doped region 154 serves as the emitter of the first triode, the semiconductor layer 112 or the substrate 110 of the ESD region serves as the emitter of the second triode, the second doped region 156 serves as the collector of the first triode and the second triode, and the second conductivity type well region 152 serves as the base of the first triode and the second triode.

[0062] In an embodiment of the present application, it further includes the step of forming a third doped region 158 in the second conductivity type well region 152 by ion implantation. Specifically, a third doped region 158 that is in direct contact with the second doped region 156 is formed below the second doped region 156 by implanting ions of the second conductivity type, refer to Figure 3k . After forming the third doped region 158, the silicon dioxide layer 134 can be removed. By providing the third doped region 158, a Zener diode can be formed between the second doped region 156 and the third doped region 158, increasing the response speed of the first triode and the second triode at the initial stage of operation and achieving a fast response.

[0063] In an embodiment of the present application, the first conductivity type is N-type, the second conductivity type is P-type, the first doped region 154 and the second doped region 156 are N+ regions, the substrate 110 is an N+ substrate, and the doping concentration of the semiconductor layer 112 can be lower than that of the substrate 110. In other embodiments, the first conductivity type can also be P-type, and the second conductivity type is correspondingly N-type.

[0064] It should be understood that although the steps in the flowcharts of the present application are displayed in sequence according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear indication in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts of the present application may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same moment, but can be executed at different moments, and the execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or steps or stages in other steps.

[0065] In the description of this specification, the descriptions referring to terms such as "some embodiments", "other embodiments", "ideal embodiments", etc. mean that the specific features, structures, materials or features described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0066] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0067] The above-described embodiments merely represent several implementation manners of the present invention. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the invention patent should be subject to the appended claims.

Claims

1. A device having an electrostatic discharge protection structure, characterized in that: It includes a device area and an ESD area, wherein the device area includes: a substrate having a first conductivity type; an insulating layer, disposed on the substrate; A device active region layer is provided on the insulating layer; The ESD zone includes: a semiconductor layer connected to the substrate and having a first conductivity type; A second conductive type well region is provided in the semiconductor layer; A first doped region having a first conductivity type and disposed on a surface of the second conductivity type well region; A second doped region having a first conductivity type and disposed on a surface of the second conductivity type well region; Among them, the first doped region serves as the emitter of the first triode, the semiconductor layer serves as the emitter of the second triode, the second doped region serves as the collector of the first triode and the second triode, and the second conductive type well region serves as the base of the first triode and the second triode; the first conductive type and the second conductive type are opposite conductive types.

2. The device with an electrostatic discharge protection structure according to claim 1, characterized in that: The device is a silicon-on-insulator device, the substrate is a silicon substrate, the device active region layer is a top silicon layer, and the semiconductor layer is a silicon epitaxial layer.

3. The device with an electrostatic discharge protection structure according to claim 1, wherein: The third doping region is located in the second conductive type well region, the third doping region is located below the second doping region and is in direct contact with the second doping region, and the third doping region has the first conductive type.

4. The device with an electrostatic discharge protection structure according to claim 1, wherein: The method further includes a first isolation structure, wherein the first isolation structure is disposed between the first doping region and the second doping region.

5. The device with an electrostatic discharge protection structure according to claim 1, wherein: It also includes a second isolation structure, which is arranged at the junction of the device area and the ESD area, and the bottom of the second isolation structure extends to the insulating layer.

6. The device with an electrostatic discharge protection structure according to claim 4, characterized in that: The first isolation structure is a shallow trench isolation structure.

7. The device having an electrostatic discharge protection structure according to any one of claims 1 to 6, characterized in that: The first conductivity type is N-type, and the second conductivity type is P-type.

8. A method for manufacturing a device having an electrostatic discharge protection structure, comprising: Obtaining a substrate; The base comprises a substrate, an insulating layer and an active region layer stacked in sequence, and the substrate has a first conductivity type; removing the active region layer and the insulating layer in the ESD region to expose the substrate in the ESD region; Filling the removed active region layer and insulating layer with a semiconductor material to form a semiconductor layer, wherein the semiconductor layer has a first conductivity type; forming a second conductive type well region, a first doped region, and a second doped region in the semiconductor layer, wherein the first doped region and the second doped region are formed on a surface of the second conductive type well region, and the first doped region and the second doped region have the first conductive type; Among them, the first doped region serves as the emitter of the first transistor, the substrate of the ESD region serves as the emitter of the second transistor, the second doped region serves as the collector of the first transistor and the second transistor, and the second conductive type well region serves as the base of the first transistor and the second transistor; the first conductive type and the second conductive type are opposite conductive types.

9. The method for manufacturing a device having an electrostatic discharge protection structure according to claim 8, wherein: The device is a silicon-on-insulator device, the substrate is a silicon substrate, and the active area layer is a top silicon layer; before the step of removing the active area layer and the insulating layer in the ESD zone, the step also includes the step of forming a silicon oxide layer on the surface of the top silicon layer; the step of filling the position of the removed active area layer and the insulating layer with semiconductor material to form a semiconductor layer includes forming the semiconductor layer through an epitaxial process.

10. The method for manufacturing a device having an electrostatic discharge protection structure according to claim 9, wherein: The step of removing the active region layer and the insulating layer in the ESD region includes removing the silicon oxide layer, the active region layer and the insulating layer in the ESD region by photolithography and dry etching.

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