Bidirectional multi-level conversion circuit

Abstract

The application discloses a bidirectional multi-level conversion circuit, comprising: a first resistor, a first end of which is connected with a communication link signal, and a second end of which is connected with a power supply voltage; a second resistor, a first end of which is connected with the communication link signal, and a second end of which is connected with the power supply voltage through a second switch device; a fifth resistor, a first end of which is connected with a control end of a third switch device, and a second end of which is connected between a seventh resistor and a first switch device; a sixth resistor, a first end of which is connected with the control end of the third switch device, and a second end of which is connected with the power supply voltage; the seventh resistor is connected with the ground through the first switch device; a control end of the first switch device is connected with the communication link signal through a third resistor; a control end of the second switch device is connected with the power supply voltage through the third switch device, and the control end of the second switch device is connected with the first switch device through the seventh resistor. The application has the advantages of better signal quality, lower low level, slower rising edge, higher communication rate, and low cost.

Description

Technical Field

[0001] This invention relates to the field of electronic circuits, and in particular to a bidirectional multilevel conversion circuit for open-drain communication buses such as I2C, SMI, and PMbus. Background Technology

[0002] The electronics industry is developing rapidly, and the pace of technological updates is also quite fast. Many electronic products are moving towards lower power consumption, so the I / O levels of some chips are becoming lower and lower. This leads to the coexistence of chips with different voltage levels. When different voltage levels communicate with each other, a level conversion circuit is required.

[0003] When bidirectional level conversion is required for buses such as I2C, SMI, and PMbus, MOSFET-based conversion chips are a common solution. (See reference...) Figure 1 As shown. When one side is low, the internal MOSFET will conduct, and the other side will be pulled low as well; when both sides are high, the MOSFET will not conduct, and the voltage level is determined by its pull-up voltage. When electronic systems are complex, there may be many buses with different voltage levels that need to communicate, or when the same voltage needs to be isolated between different power rails, multiple conversion chips are required for conversion. (Refer to...) Figure 2 As shown.

[0004] When multiple conversion chips work together, some problems arise. When one outputs a low level, the corresponding MOSFETs of all the conversion chips will turn on. This means all the pull-up resistors are effectively connected in parallel to pull up to a certain voltage. Consequently, the sink current of the low-level output I / O increases. If this increase reaches its limit, the low-level voltage will rise. When the voltage across this circuit... OL When the voltage level exceeds the VILmax of the terminal device, communication will fail. Current solutions involve increasing the pull-up resistor. However, the bus has parasitic capacitance on the PCB. When the signal transitions from low to high, the MOSFET becomes non-conductive, and the capacitor can only charge via the pull-up voltage source. Because the pull-up resistor is larger, charging becomes slower. Figure 3 The signal waveform shown will then become as follows Figure 4 As shown, this waveform signal may not meet the signal integrity requirements. Even if it does, it can only operate at low speeds. When the bus speed needs to be increased, it will not meet the requirements, thus limiting the maximum communication rate of the bus. Summary of the Invention

[0005] The summary of this invention introduces a series of simplified concepts, all of which are simplifications of existing technologies in the field, and will be further explained in detail in the detailed description section. This summary is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0006] The technical problem to be solved by the present invention is to provide a bidirectional multilevel conversion circuit for a communication bus with open-drain structure for multiple conversion chips (such as I2C, SMI and PMbus), which will not cause low-level rise or excessively slow rising edge, and can meet the requirements of high communication rate.

[0007] To solve the above-mentioned technical problems, the present invention provides a bidirectional multilevel conversion circuit, characterized in that it includes:

[0008] The first resistor R1 has its first end connected to the communication link signal SCL and its second end connected to the power supply voltage VCC.

[0009] The second resistor R2 has its first end connected to the communication link signal SCL, and its first end is connected to the power supply voltage VCC through the second switching device T2.

[0010] The fifth resistor R5 has its first end connected to the control terminal of the third switching device T3, and its second end connected between the seventh resistor R7 and the first switching device T1.

[0011] The sixth resistor R6 has its first end connected to the control terminal of the third switching device T3, and its second end connected to the power supply voltage VCC.

[0012] The seventh resistor R7 is connected to ground GND via the first switching device T1;

[0013] The first switching device T1 has its control terminal connected to the communication link signal SCL via the third resistor R3;

[0014] The second switching device T2 has its control terminal connected to the power supply voltage VCC via the third switching device T3, and its control terminal is connected to the first switching device T1 via the seventh resistor R7.

[0015] Among them, the resistance value of the fifth resistor R5 is greater than or equal to the resistance value of the seventh resistor R7. Whether the second switching device T2 is turned on determines whether the second resistor R2 is working. The second switching device T2 and the third switching device T3 are the same device.

[0016] Alternatively, the bidirectional multilevel conversion circuit may be further improved by including:

[0017] The fourth resistor R4 is connected between the control terminal of the first switching device T1 and ground GND;

[0018] Alternatively, the bidirectional multilevel conversion circuit can be further improved such that the second switching device T2 is turned on only when the first switching device T1 is turned on and the third switching device T3 is not turned on.

[0019] Alternatively, the bidirectional multilevel switching circuit can be further improved by using an NPN transistor as the first switching device T1, and PNP transistors as the second and third switching devices T2 and T3.

[0020] Optionally, the bidirectional multilevel conversion circuit can be further improved. When the communication link signal SCL is low, the base of the first switching device T1 is still low after voltage division by the third resistor R3 and the fourth resistor R4. The first switching device T1 is not turned on, the base of the second switching device T2 is high, the emitter and base of the second switching device T2 cannot be forward biased, the second switching device T2 is not turned on, and the second resistor R2 does not work. At this time, the pull-up resistor is the first resistor R1.

[0021] When the communication link signal SCL is rising, and the voltage divided by the third resistor R3 and the fourth resistor R4 is greater than 0.5V-0.9V (preferably 0.7V), the first switching device T1 is turned on, the base of the second switching device T2 is low, the second switching device T2 is turned on, and the second resistor R2 is working. At this time, the pull-up resistor is the first resistor R1 and the second resistor R2 connected in parallel.

[0022] When the communication link signal SCL is high, the first switching device T1 is turned on, the third switching device T3 is turned on, the base voltage of the second switching device T2 becomes the supply voltage VCC, and the second switching device T2 is not turned on.

[0023] Alternatively, the bidirectional multilevel switching circuit can be further improved such that the on-time of the second switching device T2 during the rising edge can be adjusted by changing the resistance values ​​of the fifth resistor R5, the sixth resistor R6, and the seventh resistor R7.

[0024] Alternatively, the bidirectional multilevel conversion circuit can be further improved by setting the value of the first resistor R1 to be approximately R1≈R PU n+1

[0025] R PU It assumes that the pull-up resistor of the bus when no conversion chip is needed is determined by the requirements of the terminal device and the parasitic capacitance on the PCB.

[0026] The range of the second resistor R2 is: R1 / / R2≈R PU ;

[0027] The third resistor R3 and the fourth resistor R4 satisfy the following resistance relationship;

[0028]

[0029]

[0030] K is a specified coefficient.

[0031] Alternatively, the bidirectional multilevel conversion circuit can be further improved, with K ranging from 1 / 4 to 2 / 3.

[0032] The working principle of this invention is explained as follows:

[0033] refer to Figure 5 As shown, a multi-link open-drain communication bus is illustrated. Taking the communication link signal SCL end as an example, the operation of the second resistor R2 depends on whether the second switching device T2 (PNP transistor) is turned on. The conduction of the second switching device T2 depends on the conduction states of the first switching device T1 (NPN transistor) and the third switching device T3 (PNP transistor). The second switching device T2 will only conduct when the first switching device T1 is turned on and the third switching device T3 is not turned on. That is, when the communication link signal SCL is at its rising edge, the first switching device T1 will turn on first, and the collector voltage of the first switching device T1 will be close to 0V.

[0034] Because R5 ≥ R7, and the third switching device T3 has an additional pull-up resistor R6 at its base, the base voltage of the third switching device T3 is slightly higher than the base voltage of the second switching device T2 at the instant the first switching device T1 turns on. Therefore, the second switching device T2 will turn on before the third switching device T3. When the rising edge of the communication link signal continues to rise and the parasitic capacitance of the third switching device T3 has been discharged, the third switching device T3 will turn on. After the third switching device T3 turns on, the base voltage of the second switching device T2 becomes VCC, meaning the second switching device T2 becomes non-conductive. During the rising edge, the second switching device T2 will only be on for a short period, and this on-time can be adjusted by the resistance values ​​of R5, R6, and R7.

[0035] The main design idea is that when the link is low, if the pull-up resistor is too small, the driving capability of the output low-level IO may be insufficient. Therefore, the pull-up resistor should be large, so the second switching device T2 should not be turned on, the second resistor R2 does not play a role, and only the first resistor R1 is a pull-up resistor. The resistance value of the first resistor R1 should be slightly larger.

[0036] When a low level needs to transition to a high level, if the first resistor R1 is too large, the voltage on the link will rise too slowly. Figure 4As shown, signal integrity is poor, so the pull-up resistor needs to be small. This means that by turning on the second switching device T2, the second resistor R2 operates. The actual pull-up resistor is the parallel connection of the first resistor R1 and the second resistor R2. When the link signal stabilizes at a high level, the second switching device T2 should not be turned on to ensure a low level can be reached next time. That is, the second switching device T2 is turned on for a short period on the rising edge to reduce the rising edge time and reach the high level more quickly.

[0037] The conduction control circuit for the second switching device T2 consists of a third resistor R3, a fourth resistor R4, and the first and third switching devices T1 and T3. When SCL is low, the base of the first switching device T1 remains low after voltage division through the third and fourth resistors R3 and R4, so T1 is not conducting. The base of the second switching device T2 is high, and the emitter and base of T2 cannot be forward biased, so T2 is not conducting. The second resistor R2 is inactive, and the pull-up resistor is the first resistor R1. When SCL is a rising edge, when the voltage divided by the third and fourth resistors R3 is greater than 0.5V-0.9V, the first switching device T1 conducts, the base of the second switching device T2 is low, T2 conducts, and the second resistor R2 is active. In this case, the pull-up resistor is the first resistor R1 and the second resistor R2 connected in parallel. When SCL is high, the first switching device T1 is fully turned on, the third switching device T3 also turns on, and the base voltage of the second switching device T2 becomes VCC, that is, the second switching device T2 becomes non-conductive.

[0038] Let R be the pull-up resistor of the bus when no conversion chip is needed. PU (The RPU is determined by the requirements of the terminal device and the parasitic capacitance on the PCB), in this invention, R1 is taken as R1≈R PU (n+1). The value of R2 is such that R1 / / R2 ≈ R PU The third resistor R3 and the fourth resistor R4 must satisfy these two conditions. The K value is mainly used to set the threshold V for the first switching device T1 to turn on. TH K is The threshold value is set to half of VCC. K can be increased or decreased depending on the actual situation. For example, if the number of converters n is large, the value of the first resistor R1 will increase, and K can be appropriately decreased. The second switching device T2 and the third switching device T3 must be PNP transistors of the same type to ensure that the third switching device T3 turns on later than the second switching device T2.

[0039] The signal waveform provided by this invention is as follows: Figure 7 As shown, comparison Figure 3 , Figure 4The waveform shown has better signal quality, with low levels not being too high and rising edges not being too slow, enabling higher communication rates. This invention solves the technical problems existing in multiple conversion chip circuits at low cost. Attached Figure Description

[0040] The accompanying drawings are intended to illustrate the general characteristics of the methods, structures, and / or materials used in specific exemplary embodiments of the invention, supplementing the description in the specification. However, the drawings are schematic diagrams not drawn to scale and may not accurately reflect the precise structural or performance characteristics of any of the given embodiments. The drawings should not be construed as limiting or restricting the range of numerical values ​​or properties covered by exemplary embodiments of the invention. The invention will now be described in further detail with reference to the accompanying drawings and specific embodiments:

[0041] Figure 1 This is a schematic diagram of an existing MOSFET-based conversion chip structure.

[0042] Figure 2 This is a schematic diagram of another existing MOSFET-based conversion chip structure.

[0043] Figure 3 This is a waveform illustration of existing technology. Figure 1 .

[0044] Figure 4 This is a waveform illustration of existing technology. Figure 2 .

[0045] Figure 5 This is a schematic diagram of the structure of Embodiment 1 of the present invention.

[0046] Figure 6 This is a schematic diagram of the structure of Embodiment 2 of the present invention.

[0047] Figure 7 This is a waveform diagram of the present invention. Detailed Implementation

[0048] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can fully understand other advantages and technical effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through different specific embodiments, and the details in this specification can also be applied based on different viewpoints, with various modifications or changes made without departing from the overall design concept of the invention. It should be noted that, unless otherwise specified, the following embodiments and features can be combined with each other. The following exemplary embodiments of the present invention can be implemented in many different forms and should not be construed as being limited to the specific embodiments set forth herein. It should be understood that these embodiments are provided to make the disclosure of the present invention thorough and complete, and to fully convey the technical solutions of these exemplary embodiments to those skilled in the art.

[0049] Example 1;

[0050] refer to Figure 5 As shown, the present invention provides a bidirectional multilevel conversion circuit, comprising:

[0051] The first resistor R1 has its first end connected to the communication link signal SCL and its second end connected to the power supply voltage VCC.

[0052] The second resistor R2 has its first end connected to the communication link signal SCL, and its first end is connected to the power supply voltage VCC through the second switching device T2.

[0053] The fifth resistor R5 has its first end connected to the control terminal of the third switching device T3, and its second end connected between the seventh resistor R7 and the first switching device T1.

[0054] The sixth resistor R6 has its first end connected to the control terminal of the third switching device T3, and its second end connected to the power supply voltage VCC.

[0055] The seventh resistor R7 is connected to ground GND via the first switching device T1;

[0056] The first switching device T1 has its control terminal connected to the communication link signal SCL via the third resistor R3;

[0057] The second switching device T2 has its control terminal connected to the power supply voltage VCC via the third switching device T3, and its control terminal is connected to the first switching device T1 via the seventh resistor R7.

[0058] Among them, the resistance value of the fifth resistor R5 is greater than or equal to the resistance value of the seventh resistor R7. Whether the second switching device T2 is turned on determines whether the second resistor R2 is working. The second switching device T2 and the third switching device T3 are the same device.

[0059] Example 1;

[0060] refer to Figure 5 As shown, the present invention provides a bidirectional multilevel conversion circuit, comprising:

[0061] The first resistor R1 has its first end connected to the communication link signal SCL and its second end connected to the power supply voltage VCC.

[0062] The second resistor R2 has its first end connected to the communication link signal SCL, and its first end is connected to the power supply voltage VCC through the second switching device T2.

[0063] The fifth resistor R5 has its first end connected to the control terminal of the third switching device T3, and its second end connected between the seventh resistor R7 and the first switching device T1.

[0064] The sixth resistor R6 has its first end connected to the control terminal of the third switching device T3, and its second end connected to the power supply voltage VCC.

[0065] The seventh resistor R7 is connected to ground GND via the first switching device T1;

[0066] The first switching device T1 has its control terminal connected to the communication link signal SCL via the third resistor R3;

[0067] The second switching device T2 has its control terminal connected to the power supply voltage VCC via the third switching device T3, and its control terminal is connected to the first switching device T1 via the seventh resistor R7.

[0068] Among them, the resistance value of the fifth resistor R5 is greater than or equal to the resistance value of the seventh resistor R7. Whether the second switching device T2 is turned on determines whether the second resistor R2 is working. The second switching device T2 and the third switching device T3 are the same device.

[0069] Example 2;

[0070] refer to Figure 6 As shown, the present invention provides a bidirectional multilevel conversion circuit, comprising:

[0071] The first resistor R1 has its first end connected to the communication link signal SCL and its second end connected to the power supply voltage VCC.

[0072] The second resistor R2 has its first end connected to the communication link signal SCL, and its first end is connected to the power supply voltage VCC through the second switching device T2.

[0073] The fourth resistor R4 is connected between the control terminal of the first switching device T1 and ground GND;

[0074] The fifth resistor R5 has its first end connected to the control terminal of the third switching device T3, and its second end connected between the seventh resistor R7 and the first switching device T1.

[0075] The sixth resistor R6 has its first end connected to the control terminal of the third switching device T3, and its second end connected to the power supply voltage VCC.

[0076] The seventh resistor R7 is connected to ground GND via the first switching device T1;

[0077] The first switching device T1 has its control terminal connected to the communication link signal SCL via the third resistor R3;

[0078] The second switching device T2 has its control terminal connected to the power supply voltage VCC via the third switching device T3, and its control terminal is connected to the first switching device T1 via the seventh resistor R7.

[0079] Among them, the resistance value of the fifth resistor R5 is greater than or equal to the resistance value of the seventh resistor R7. Whether the second switching device T2 is turned on determines whether the second resistor R2 works. The second switching device T2 and the third switching device T3 are the same device. The second switching device T2 is turned on only when the first switching device T1 is turned on and the third switching device T3 is not turned on. The first switching device T1 is an NPN transistor, and the second switching device T2 and the third switching device T3 are PNP transistors.

[0080] When the communication link signal SCL is low, after voltage division by the third resistor R3 and the fourth resistor R4, the base of the first switching device T1 is still low, and the first switching device T1 is not turned on. The base of the second switching device T2 is high, and the emitter and base of the second switching device T2 cannot be forward biased. The second switching device T2 is not turned on, and the second resistor R2 does not work. At this time, the pull-up resistor is the first resistor R1.

[0081] When the communication link signal SCL is rising, when the voltage divided by the third resistor R3 and the fourth resistor R4 is greater than 0.5V-0.9V, the first switching device T1 is turned on, the base of the second switching device T2 is low, the second switching device T2 is turned on, and the second resistor R2 is working. At this time, the pull-up resistor is the first resistor R1 and the second resistor R2 connected in parallel.

[0082] When the communication link signal SCL is high, the first switching device T1 is turned on, the third switching device T3 is turned on, the base voltage of the second switching device T2 becomes the supply voltage VCC, and the second switching device T2 is not turned on.

[0083] During the rising edge, the on-time of the second switching device T2 can be adjusted by changing the resistance values ​​of the fifth resistor R5, the sixth resistor R6, and the seventh resistor R7.

[0084] Optionally, the range of values ​​for the first resistor R1 is: R1≈R PU n+1;

[0085] R PUIt assumes that the pull-up resistor of the bus when no conversion chip is needed is determined by the requirements of the terminal device and the parasitic capacitance on the PCB.

[0086] The range of the second resistor R2 is: R1 / / R2≈R PU ;

[0087] The third resistor R3 and the fourth resistor R4 satisfy the following resistance relationship;

[0088]

[0089]

[0090] K is a specified coefficient, ranging from 1 / 4 to 2 / 3, preferably 1 / 2.

[0091] Unless otherwise defined, all terms used herein, including technical and scientific terms, shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will also be understood that, unless explicitly defined herein, terms such as those defined in a general dictionary shall be interpreted as having the meaning consistent with their meaning in the relevant field context, and not as having an idealized or overly formal meaning.

[0092] The present invention has been described in detail above through specific embodiments and examples, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A bidirectional multi-level conversion circuit, characterized by, include: The first resistor (R1) has its first end connected to the communication link signal (SCL) and its second end connected to the power supply voltage (VCC). The second resistor (R2) has its first end connected to the communication link signal (SCL) and its second end connected to the power supply voltage (VCC) via the second switching device (T2). The fifth resistor (R5) has its first end connected to the control terminal of the third switching device (T3), and its second end connected between the seventh resistor (R7) and the first switching device (T1). The sixth resistor (R6) has its first end connected to the control terminal of the third switching device (T3) and its second end connected to the supply voltage (VCC). The seventh resistor (R7) is connected to ground (GND) via the first switching device (T1); The first switching device (T1) has its control terminal connected to the communication link signal (SCL) via the third resistor (R3). The second switching device (T2) has its control terminal connected to the power supply voltage (VCC) via the third switching device (T3), and its control terminal is connected to the first switching device (T1) via the seventh resistor (R7). Among them, the resistance value of the fifth resistor (R5) is greater than or equal to the resistance value of the seventh resistor (R7). Whether the second switching device (T2) is conducting determines whether the second resistor (R2) is working. The second switching device (T2) and the third switching device (T3) are the same device. The first switching device (T1) is an NPN transistor, and the second switching device (T2) and the third switching device (T3) are PNP transistors.

2. The bidirectional multi-level conversion circuit of claim 1, wherein, Also includes: The fourth resistor (R4) is connected between the control terminal of the first switching device (T1) and ground (GND).

3. The bidirectional multilevel conversion circuit as described in claim 1, characterized in that: The second switching device (T2) is turned on only when the first switching device (T1) is turned on and the third switching device (T3) is not turned on.

4. The bidirectional multilevel conversion circuit as described in claim 1, characterized in that: When the communication link signal (SCL) is low, after voltage division by the third resistor (R3) and the fourth resistor (R4), the base of the first switching device (T1) is still low, and the first switching device (T1) is not turned on. The base of the second switching device (T2) is high, and the emitter and base of the second switching device (T2) cannot be forward biased. The second switching device (T2) is not turned on, and the second resistor (R2) does not work. At this time, the pull-up resistor is the first resistor (R1). When the communication link signal (SCL) is on the rising edge, when the voltage divided by the third resistor (R3) and the fourth resistor (R4) is greater than 0.5V-0.9V, the first switching device (T1) is turned on, the base of the second switching device (T2) is low, the second switching device (T2) is turned on, and the second resistor (R2) is working. At this time, the pull-up resistor is the first resistor (R1) and the second resistor (R2) connected in parallel. When the communication link signal (SCL) is high, the first switching device (T1) is turned on, the third switching device (T3) is turned on, the base voltage of the second switching device (T2) becomes the supply voltage (VCC), and the second switching device (T2) is not turned on.

5. The bidirectional multi-level conversion circuit of claim 1, wherein: During the rising edge, the conduction time of the second switching device (T2) can be adjusted by changing the resistance values of the fifth resistor (R5), the sixth resistor (R6) and the seventh resistor (R7).

6. The bidirectional multi-level conversion circuit of claim 2, wherein: The first resistor (R1) has a value range of R1≈RPU(n+1); RPU is the pull-up resistance of the bus when the conversion chip is not needed, which is determined by the terminal device requirement and the parasitic capacitance on the PCB; The second resistor (R2) has a value range of R1 / / R2≈RPU; The third resistor (R3) and the fourth resistor (R4) satisfy the following resistance relationship: ； ； K is a specified coefficient, R1 is the resistance value of the first resistor, R2 is the resistance value of the second resistor, R3 is the resistance value of the third resistor, R4 is the resistance value of the fourth resistor, and n is the number of converters.

7. The bidirectional multi-level conversion circuit of claim 6, wherein: The range of K is 1 / 4~2 / 3.

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