antenna array
By dividing the antenna array into subarray modules and a carrier board, and using a T-type power divider and daisy-chain signal lines, the complexity and expansion challenges of antenna arrays in 5G millimeter-wave equipment are solved, achieving flexible expansion and cost reduction.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- DATANG MOBILE COMM EQUIP CO LTD
- Filing Date
- 2021-12-30
- Publication Date
- 2026-06-05
AI Technical Summary
In 5G millimeter-wave equipment, as the antenna array size increases, the complexity of the power supply network and beam control network also increases, and the integrated design is costly and difficult to expand to different application scenarios.
The traditional integrated design is divided into two parts: subarray modules and carrier board. The subarray modules are standardized, and the antenna array is expanded by integrating different numbers of subarray modules through the carrier board. The signal lines adopt T-type power dividers and daisy chain design. Multi-channel chips are accommodated in the carrier board grooves, and heat sinks and thermal pads are used for auxiliary heat dissipation.
It enables flexible expansion of the antenna array, reduces manufacturing difficulty and cost, is suitable for various application scenarios, and improves signal transmission efficiency and heat dissipation.
Smart Images
Figure CN116417773B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of antenna technology, and in particular to an antenna array. Background Technology
[0002] 5G millimeter-wave equipment employs active antenna array technology. Due to its high operating frequency and significant signal path loss, large-scale antenna arrays are typically required to improve base station coverage. However, as the antenna array size increases, the corresponding feeding network, beam control network, and power supply network also become more complex. Among related technologies, millimeter-wave phased arrays use an integrated design, requiring special materials even in non-antenna areas, resulting in higher costs. Furthermore, the array size is not easily expandable for different application scenarios. Summary of the Invention
[0003] This application aims to at least partially address one of the technical problems in the related art.
[0004] Therefore, the first objective of this application is to provide an antenna array comprising: a subarray module and a carrier board; the subarray module comprising a multichannel chip, an antenna element, pads, and a multilayer printed circuit board; the multichannel chip and the pads are disposed on the top layer of the multilayer printed circuit board, and the antenna element is disposed on the bottom layer of the multilayer printed circuit board; the subarray module is connected to the carrier board via the pads.
[0005] The antenna array proposed in this application separates the traditional integrated design into two parts: subarray modules and carrier board. This standardizes the subarray modules. When it is necessary to expand the antenna array, different numbers of subarray modules can be integrated together through the carrier board, thereby expanding the antenna array and making it suitable for different application scenarios.
[0006] According to the antenna array proposed in this application, when there is a free area on the carrier board, and the area of the free area is greater than or equal to the area of the subarray module, a new subarray module is welded in the free area to expand the antenna array.
[0007] According to the antenna array proposed in this application, two or more carrier plates on which the subarray modules are welded are spliced together to expand the antenna array.
[0008] According to the antenna array proposed in this application, the carrier plate includes at least one groove, the number of grooves being consistent with the number of multi-channel chips disposed on the top layer, and the multi-channel chips being accommodated in the grooves.
[0009] According to the antenna array proposed in this application, the metal layers of the multilayer printed circuit board include a ground layer, a signal layer, and a power layer.
[0010] According to the antenna array proposed in this application, the antenna array further includes: a T-type power divider, the T-type power divider including an input port and an output port, the input port being connected to the radio frequency port of the signal layer, and the output port being connected to the signal input pin of the multi-channel chip included in the subarray module; the T-type power divider is used to distribute the radio frequency signal obtained from the radio frequency port to each of the multi-channel chips of the subarray module, and transmit it to the antenna element through the multi-channel chip, wherein the radio frequency port is connected to the pad of the top layer, and the transmission line in the pad transmits the radio frequency signal sent by the carrier board.
[0011] According to the antenna array proposed in this application, the subarray module includes N multi-channel chips, where N is a positive integer greater than or equal to 1, each multi-channel chip includes multiple signal lines, and the multiple signal lines between the N multi-channel chips form a daisy chain.
[0012] According to the antenna array proposed in this application, the multiple signal lines include data input / output lines, clock signal lines, and enable signal lines. The data input / output lines start from one of the multi-channel chips and are sequentially connected in series to the remaining multi-channel chips. The clock signal lines and the enable signal lines are connected in parallel to each of the N multi-channel chips.
[0013] According to the antenna array proposed in this application, the carrier board further includes: a controller and a serial peripheral interface control bus, wherein the serial peripheral interface leads out a serial peripheral interface control bus from the controller in the same number as the number of subarray modules, and controls the plurality of subarray modules respectively.
[0014] The antenna array proposed in this application also includes a heat sink, wherein the heat sink is located below the carrier plate.
[0015] The antenna array proposed in this application also includes a thermal pad, wherein the thermal pad is located between the multi-channel chip and the heat sink.
[0016] Therefore, a second objective of this application is to provide a communication device comprising the antenna array described in any of the above embodiments. Attached Figure Description
[0017] Figure 1 This is a side view of an antenna array according to an embodiment of this application.
[0018] Figure 2 This is a side view of a subarray module according to an embodiment of this application.
[0019] Figure 3 This is a front view of a subarray module according to an embodiment of this application.
[0020] Figure 4 This is a reverse schematic diagram of a subarray module according to an embodiment of this application.
[0021] Figure 5 This is a schematic diagram of the radio frequency network design of a subarray module according to an embodiment of this application.
[0022] Figure 6 This is a schematic diagram of a T-type power divider with two-stage impedance transformation according to an embodiment of this application.
[0023] Figure 7 This is a schematic diagram of a daisy-chain design of a waveguide network according to an embodiment of this application.
[0024] Figure 8 This is a schematic diagram of four subarray modules integrated on a carrier board according to one embodiment of this application.
[0025] Figure 9 This is a schematic diagram of 16 subarray modules integrated on a carrier board according to an embodiment of this application.
[0026] Figure 10 This is a schematic diagram of a carrier board overall according to one embodiment of this application.
[0027] Figure 11 This is a schematic diagram of an antenna array for auxiliary heat dissipation according to one embodiment of this application. Detailed Implementation
[0028] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.
[0029] To better understand the antenna array arrangement proposed in this application, Figure 1 A side view of an antenna array proposed in this application is shown, as follows. Figure 1 As shown, the antenna array includes subarray modules and a carrier board. The subarray modules include multi-channel chips, antenna elements, and multilayer printed circuit boards (PCBs). Optionally, the antenna array proposed in this application can be used for 5G millimeter-wave communication. It should be noted that, since this is a side view of the antenna array, the carrier board appears to be segmented; in reality, the carrier board is a single board with multiple grooves.
[0030] Figure 2 This is a side view of a subarray module included in an antenna array according to this application, as shown. Figure 2As shown, multiple multi-channel chips are soldered onto the top layer of a multi-layer printed circuit board, which also includes pads. Antenna elements are placed on the bottom layer of the multi-layer printed circuit board. The multi-channel chips, the multi-layer printed circuit board pads, and the antenna elements together form a subarray module. Figure 2 The small circles between each multichannel chip and the multilayer printed circuit board represent the pins of the multichannel chip. For example... Figure 1 As shown, the subarray module is soldered to the carrier board via pads, thus fixing the subarray module and the carrier board together to form an antenna array. Within the antenna array, multi-channel chips are housed in recesses on the carrier board.
[0031] It is important to note that, in Figure 1 In this configuration, the subarray modules are inverted on the carrier board; in fact, the subarray modules are like... Figure 2 As shown, the multi-channel chip and pads are located on the top layer of the subarray module, and the antenna unit is located on the bottom layer of the subarray module.
[0032] The antenna array proposed in this application separates the traditional integrated design into two parts: subarray modules and carrier board. This standardizes the subarray modules. When it is necessary to expand the antenna array, different numbers of subarray modules can be integrated together through the carrier board, thereby expanding the antenna array and making it suitable for different application scenarios.
[0033] Next, we will introduce in detail the subarray modules and carrier board that make up the antenna array.
[0034] As described above, the subarray module includes a multilayer printed circuit board (PCB), which comprises multiple metal layers, namely a ground layer, a signal layer, and a power layer. Optionally, there can be one or more ground, signal, and power layers. Table 1 is a schematic diagram of the multilayer printed circuit board design of a subarray module proposed in this application, implemented using an 8-layer PCB board. The thickness and definition of each layer are shown in the table below.
[0035] Table 1. Schematic diagram of the multilayer printed circuit board design for the subarray module.
[0036]
[0037] As shown in Table 1, the subarray module contains a total of 8 metal layers arranged sequentially from top to bottom, namely layers L1 to L8. Among them, layer L1 is the top layer of the subarray module, and the copper thickness of layer L1 is a 0.5 ounce (oz) spray-plated layer; layer L2 is the first ground layer of the subarray module, and the copper thickness of layer L2 is 0.5 oz; layer L3 is the first signal layer of the subarray module, and the copper thickness of layer L3 is 0.5 oz; layer L4 is the second ground layer of the subarray module, and the copper thickness of layer L4 is 0.5 oz; layer L5 is the power layer of the subarray module, and the copper thickness of layer L5 is 0.5 oz; layer L6 is the second signal layer of the subarray module, and the copper thickness of layer L6 is 0.5 oz; layer L7 is the third ground layer of the subarray module, and the copper thickness of layer L7 is 0.5 oz; layer L8 is the bottom layer of the subarray module, and the copper thickness of layer L8 is a 0.5 oz spray-plated layer.
[0038] In the table above, prepreg (PP) is a thin insulating material for PCBs. Prepreg, before lamination, is also known as prepreg material and is mainly used as an adhesive and insulating material for the inner conductive patterns of multilayer printed circuit boards. After lamination, the semi-cured epoxy resin is squeezed out, begins to flow and solidify, bonding the multilayer circuit boards together and forming a reliable insulating layer.
[0039] The core is the basic material for making printed circuit boards (PCBs). It has a certain degree of hardness and thickness, and is copper-faced on both sides. Therefore, multilayer boards are actually made by laminating the core and the prepreg together.
[0040] As shown in Table 1, L2 and L3 are the upper and lower metal layers of a core board with a dielectric thickness of 100 μm, L4 and L5 are the upper and lower metal layers of a core board with a dielectric thickness of 100 μm, L6 and L7 are the upper and lower metal layers of a core board with a dielectric thickness of 200 μm, and L1 and L2 are bonded together with a 100 μm Prepreg, L3 and L4 are bonded together with a 100 μm PP, L5 and L6 are bonded together with a 100 μm PP, and L7 and L8 are bonded together with a 750 μm Prepreg.
[0041] Multiple multi-channel chips are soldered onto the top layer L1 of a multilayer printed circuit board, and the antenna unit is placed on the bottom layer L8 of the multilayer printed circuit board. That is, when looking at the subarray module from the front, what you see are the pads on the top layer of the multilayer printed circuit board and the multiple multi-channel chips soldered on the top layer of the multilayer printed circuit board; when looking at the subarray module from the back, what you see are the antenna units on the bottom layer of the multilayer printed circuit board.
[0042] Figure 3This is a front view of a subarray module in an antenna array proposed in this application, as shown in the figure. Figure 3 As shown, the front of the subarray module includes multiple multi-channel chips and multiple pads.
[0043] Figure 3 The illustration is based on an example of a subarray module having four multi-channel chips on the front. It should be noted that in practice, the number of multi-channel chips on the front of each subarray module can be changed according to actual needs. For example, each subarray module may have eight or sixteen multi-channel chips on the front. The four chips shown here are just an example and do not constitute a limitation on this application.
[0044] In this configuration, multiple pads on the front side of each subarray module can be spaced out to surround all the multi-channel chips; alternatively, multiple pads on the front side of each subarray module can be spaced out to surround each multi-channel chip on the front side of the subarray module. It is important to note that... Figure 3 The number of pads is for illustrative purposes only and should not be construed as limiting the scope of this application.
[0045] Figure 4 This is a reverse schematic diagram of a subarray module in an antenna array proposed in this application, as shown below. Figure 4 As shown, the reverse side of the subarray module includes multiple antenna elements, which are arranged at intervals. Figure 4 The example shown is based on the subarray module having 16 antenna elements on the reverse side. It should be noted that in practice, the number of antenna elements on the reverse side of each subarray module can be changed according to actual needs. For example, the number of antenna elements on the reverse side of each subarray module can also be 32 or 64, etc. The 16 here is just an example and does not constitute a limitation on this application.
[0046] Figure 5 This is a schematic diagram of the RF network design of the subarray module proposed in this application, as shown below. Figure 5 As shown, the RF network of the subarray module uses a T-type power divider to distribute the RF signal obtained from the RF port (Radio Frequency Component Object Mode, RF COM) of the signal layer to each multi-channel chip of the subarray module. The T-type power divider includes an input port and an output port. The input port is connected to the RF port, and the output port is connected to the signal input pins of the multi-channel chips included in the subarray module. The T-type power divider is used to distribute the RF signal obtained from the RF port to each multi-channel chip of the subarray module, and then transmit it to the antenna element via the multi-channel chip. The RF port is connected to the top-layer pads, and the transmission lines in the pads obtain the RF signal from the carrier board and transmit the RF signal sent by the carrier board to the RF port.
[0047] To achieve a smooth impedance transition for RF traces, the T-type power divider can optionally be designed with multi-stage impedance transformation. Figure 6 This is a schematic diagram of a T-type power divider with two-stage impedance transformation, as shown below. Figure 6 As shown, the T-type power divider with two-stage impedance transformation distributes the RF signal obtained from the RF port to each multi-channel chip in the subarray module.
[0048] This application uses a T-type power divider, which eliminates the need for Wilkinson resistors. This eliminates the need for buried resistors during PCB fabrication, simplifying the manufacturing process. Furthermore, the T-type power divider with multi-stage impedance transformation enables a smooth transition of RF trace impedance.
[0049] The subarray module comprises multiple multi-channel chips, each with multiple signal lines, including data input / output lines, clock signal lines, and enable signal lines. These signal lines are used to implement the wave control network. To minimize the number of external interfaces and thus reduce the number of pads on the top layer of the subarray module, the signal lines between the multiple multi-channel chips on each subarray module are daisy-chained.
[0050] Figure 7 This is a schematic diagram of a daisy-chain design of a wave-controlled network proposed in this application, as shown below. Figure 7 As shown, each multi-channel chip has multiple signal lines, including a serial data output (SDO) signal line, a serial data input (SDI) signal line, a serial clock (SCLK) signal line, and a chip select (CS) signal line. Specifically, the SDO signal line represents master device data output and slave device data input; the SDI signal line represents master device data input and slave device data output; the SCLK signal line represents the clock signal, generated by the master device; and the CS signal line represents the slave device enable signal, controlled by the master device in the SPI master-slave structure. CS controls whether the chip is selected; that is, operations on this chip are only effective when the chip select signal is a pre-defined enable signal.
[0051] like Figure 7 As shown, the SDO and SDI signal lines start from one of the multi-channel chips and are sequentially connected in series to the remaining multi-channel chips; the SCLK and CS signal lines are connected in parallel to each of the multiple multi-channel chips in each subarray module.
[0052] The design of the carrier board for the subarray module will be described in detail below. The carrier board includes at least one recess, and the number of recesses is consistent with the number of multi-channel chips placed on the top layer. The recess design facilitates heat dissipation and, given the height of the multi-channel chips, placing them in the recess reduces the difficulty of interconnecting the subarray module with the carrier board. This eliminates the need for additional ball-mounting processing of the subarray module, thereby reducing manufacturing complexity and cost.
[0053] In addition to the recesses, the carrier board also features a controller and a Serial Peripheral Interface (SPI) control bus. SPI is a high-speed, full-duplex, synchronous communication bus. The controller outputs an SPI control bus with the same number of subarray modules as the number of subarray modules, allowing for the control of multiple subarray modules. Optionally, the controller can be a Field-Programmable Gate Array (FPGA) controller.
[0054] As one feasible approach, when there is unused area on the carrier board, and the area of this unused area is greater than or equal to the area of the subarray module, new subarray modules can be soldered into the unused area to expand the antenna array. For example, Figure 8 This is a schematic diagram showing the integration of four subarray modules onto a carrier board. For example, Figure 9 This is a schematic diagram showing the integration of 16 subarray modules onto a carrier board.
[0055] As another feasible approach, two or more carrier boards with welded subarray modules can be spliced together to expand the antenna array.
[0056] Figure 10 This is a schematic diagram of the overall carrier plate included in an antenna array proposed in this application, as shown below. Figure 10 The diagram shown illustrates an antenna array with 16 subarray modules integrated onto a single carrier board. Figure 10 Each small square on the grid represents a groove, and four adjacent small squares of the same color depth represent a sub-array module. Figure 8 There are a total of 16 sub-array modules. On this carrier board, 16 SPI control buses are led out from the controller, and multiple sub-array modules are controlled by means of the daisy-chain design described above.
[0057] Figure 11 This is a schematic diagram of an antenna array proposed in this application, as shown below. Figure 11As shown, based on the above embodiments, the antenna array may further include a heat sink, which is located below the carrier board and is used for auxiliary heat dissipation during the use of the antenna array. Furthermore, the antenna array may also include a thermally conductive pad, which is located between the multi-channel chip and the heat sink and is used for auxiliary heat dissipation during the use of the antenna array.
[0058] This application also proposes a communication device that includes the antenna array described in any of the above embodiments.
[0059] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.
[0060] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0061] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.
[0062] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.
Claims
1. An antenna array, characterized in that, include: Subarray modules and carrier boards; The subarray module includes a multi-channel chip, an antenna unit, pads, and a multi-layer printed circuit board, wherein the metal layers of the multi-layer printed circuit board include a ground layer, a signal layer, and a power layer. The multi-channel chip and the pads are disposed on the top layer of the multilayer printed circuit board, and the antenna unit is disposed on the bottom layer of the multilayer printed circuit board. The subarray module is connected to the carrier board via the solder pads, and the carrier board controls multiple subarray modules; two or more carrier boards with the soldered subarray modules are spliced together to expand the antenna array. The subarray module includes N multi-channel chips, where N is a positive integer greater than 1. Each multi-channel chip includes multiple signal lines, and the multiple signal lines among the N multi-channel chips form a daisy chain. The multiple signal lines include data input / output lines, clock signal lines, and enable signal lines. The data input / output lines start from one of the multi-channel chips and are sequentially connected in series to the remaining multi-channel chips. The clock signal lines and the enable signal lines are connected in parallel to each of the N multi-channel chips.
2. The antenna array according to claim 1, characterized in that, When there is an empty area on the carrier board, and the area of the empty area is greater than or equal to the area of the subarray module, a new subarray module is welded into the empty area to expand the antenna array.
3. The antenna array according to any one of claims 1-2, characterized in that, The carrier board includes at least one groove, the number of which is the same as the number of the multi-channel chips disposed on the top layer, and the multi-channel chips are accommodated in the groove.
4. The antenna array according to claim 1, characterized in that, The antenna array also includes: The T-type power divider includes an input port and an output port. The input port is connected to the radio frequency port of the signal layer, and the output port is connected to the signal input pin of the multi-channel chip included in the subarray module. The T-type power divider is used to distribute the radio frequency signal obtained from the radio frequency port to each of the multi-channel chips of the subarray module, and transmit it to the antenna unit through the multi-channel chips. The radio frequency port is connected to the pad of the top layer, and the transmission line in the pad transmits the radio frequency signal sent by the carrier board.
5. The antenna array according to claim 4, characterized in that, The carrier plate also includes: The controller and serial peripheral interface control bus, wherein the serial peripheral interface leads out from the controller to the same number of serial peripheral interface control buses as the number of subarray modules, and controls the multiple subarray modules respectively.
6. The antenna array according to claim 1, characterized in that, It also includes a heat sink, wherein the heat sink is located below the carrier plate.
7. The antenna array according to claim 6, characterized in that, It also includes a thermal pad, wherein the thermal pad is located between the multichannel chip and the heat sink.
8. A communication device, characterized in that, The antenna array includes any one of claims 1-7.