Sram cell and method of forming the same, and sram memory device

Abstract

An SRAM cell and a method for forming the same, and an SRAM memory device, the method comprising: after forming source-drain doped regions, performing cutting processing on a gate structure and a channel structure thereunder, removing a preset gate structure above a part of a second channel structure between a pull-up region and a transfer region and extending in the transfer region, and a part of the second channel structure below the preset gate structure, forming a cutting opening in the second channel structure of the transfer region, thereby adjusting the number of the second channel structures of the transfer region, correspondingly adjusting the effective channel width of a transfer gate transistor, and further adjusting the saturation current ratio of the transfer gate transistor and a pull-down transistor, and correspondingly adjusting the read-write margin of the SRAM device; and cutting the second channel structure of the transfer device by using the gate cutting process to adjust the number of the second channel structures of the transfer region, which is not only conducive to improving process compatibility and integration, but also conducive to saving masks and reducing costs.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor manufacturing, and in particular, to an SRAM cell and a forming method thereof, and an SRAM memory device. BACKGROUND

[0002] With the continuous development of digital integrated circuits, on-chip integrated memories have become an important part of digital systems. SRAM (Static Random Access Memory) has become an indispensable part of on-chip memories due to its low power consumption and high speed. SRAM can save data as long as it is powered, without the need for continuous refreshing.

[0003] An SRAM usually includes a plurality of array-arranged storage units (SRAM cells), and in a 6T SRAM storage unit, it usually includes two pull-up transistors: a first pull-up transistor PU1 and a second pull-up transistor PU2; two pull-down transistors: a first pull-down transistor PD1 and a second pull-down transistor PD2; and two pass-gate transistors: a first pass-gate transistor PG1 and a second pass-gate transistor PG2.

[0004] For a static random access memory cell, the read margin and the write margin are both related to the proportion of the saturation drive current (Idsat) of the pull-up transistor, the pull-down transistor and the pass-gate transistor.

[0005] However, the flexibility of adjusting the read and write margins of the SRAM device needs to be improved. SUMMARY

[0006] The problem solved by embodiments of the present application is to provide an SRAM cell and a forming method thereof, and an SRAM memory device, which flexibly adjusts the read and write margins of the SRAM device.

[0007] To solve the above problems, the embodiment of the present application provides a SRAM unit, comprising: a substrate, the substrate comprises a storage unit area, the storage unit area comprises a first area and a second area which are symmetrically and adjacently connected, the first area and the second area both comprise a pull-up area, a pull-down area and a transfer area, which are respectively used for forming a pull-up transistor, a pull-down transistor and a transfer transistor; a plurality of protruding structures which are separated on the substrate, the protruding structure comprises a protruding part and a channel structure which is located on the protruding part, a plurality of the protruding structures are arranged in parallel and spaced apart; the channel structure comprises a first channel structure which is located in the pull-up area, and a plurality of second channel structures which are extended along the arrangement direction of the transfer area and the pull-down area and are located in the transfer area and the pull-down area; an isolation layer which is located on the substrate and surrounds the protruding part and exposes the channel structure; a plurality of device gate structures which are located on the isolation layer and cross the channel structure, a plurality of device gate structures are arranged in parallel and spaced apart, and the extension direction of the device gate structure is perpendicular to the extension direction of the channel structure; the device gate structure comprises a transfer device gate which is located in the transfer area, and a pull device gate structure which is located in the pull-up area and the pull-down area; along the extension direction of the device gate structure, the end of the transfer device gate and the pull device gate are oppositely arranged, and the transfer device gate and the pull device gate are a gate cut-off area, in the projection plane which is parallel to the substrate, the gate cut-off area crosses a part of the second channel structure in the transfer area; a source-drain doped area which is located in the channel structure on both sides of the device gate structure, and the number of the protruding parts under the source-drain doped area in the transfer area is the same as the number of the protruding parts under the source-drain doped area in the pull-down area; a cut-off structure which is located between the transfer device gate and the pull device gate along the extension direction of the device gate structure, and penetrates the second channel structure under the gate cut-off area.

[0008] Correspondingly, the embodiment of the present application also provides a SRAM storage device, comprising a storage array, the storage array comprises one or more array-arranged storage units, and the storage unit is the SRAM unit provided by the embodiment of the present application.

[0009] Correspondingly, the embodiment of the application also provides a forming method of the SRAM unit, comprising: providing a substrate, the substrate comprising a storage unit area, the storage unit area comprising a first area and a second area which are symmetrically and adjacently connected, the first area and the second area each comprising a pull-up area, a pull-down area and a transfer area, respectively used for forming a pull-up transistor, a pull-down transistor and a transfer gate transistor; a plurality of discrete protruding structures are formed on the substrate, the protruding structure comprising a protruding part and a channel structure on the protruding part, the plurality of protruding structures being arranged in parallel and spaced apart; the channel structure comprising a first channel structure on the pull-up area and a plurality of second channel structures extending along the arrangement direction of the transfer area and the pull-down area and located in the transfer area and the pull-down area; the number of the second channel structures of the transfer area and the pull-down area is the same; an isolation layer is formed on the substrate and surrounds the protruding part, the isolation layer exposing the channel structure; a plurality of gate structures are formed on the isolation layer and cross the channel structure, the plurality of gate structures being arranged in parallel and spaced apart, and the extension direction of the gate structure being perpendicular to the extension direction of the channel structure; the gate structure comprising a preset gate structure located in the transfer area and extending to the adjacent pull-up area and pull-down area; a source-drain doped area is formed in the channel structure on both sides of the gate structure, and the number of the protruding parts below the source-drain doped area located in the transfer area is the same as the number of the protruding parts below the source-drain doped area located in the pull-down area; after the source-drain doped area is formed, the gate structure and the channel structure below the gate structure are subjected to cutting processing, the part width preset gate structure between the pull-up area and the transfer area along the extension direction of the gate structure and extending to the transfer area and the second channel structure below the part width preset gate structure are removed, a cutting opening is formed in the preset gate structure and the second channel structure in the transfer area, the remaining preset gate structure located in the transfer area is used as a transfer gate, and the remaining preset gate structure located in the pull-up area and the pull-down area is used as a pull gate; a cutting structure is formed in the cutting opening.

[0010] Compared with the prior art, the technical scheme of the embodiment of the application has the following advantages:

[0011] The SRAM unit provided by the embodiment of the present application is provided with a cutting structure, which is located between the transfer device gate and the pull device gate along the extension direction of the device gate structure and penetrates a part of the second channel structure between the transfer device gate and the pull device gate, so that the number of the second channel structure of the transfer region is adjusted by the cutting structure, the number of the channel included in the transfer gate transistor is adjusted accordingly, the effective channel width of the transfer gate transistor is further adjusted, the effective channel width of the transfer gate transistor and the pull-down transistor is made to have a difference, and the saturation current ratio between the transfer gate transistor and the pull-down transistor and the pull-up transistor is adjusted, and the read margin and the write margin of the SRAM device are adjusted accordingly.

[0012] In the SRAM unit forming method provided by the embodiment of the present application, after the source-drain doped region is formed, the preset gate structure located above a part of the second channel structure between the pull-up region and the transfer region and extending in the transfer region and a part of the second channel structure below the preset gate structure are removed along the extension direction of the gate structure, a cutting opening is formed in the second channel structure of the transfer region, so that the number of the second channel structure of the transfer region is adjusted, the number of the channel included in the transfer gate transistor is adjusted accordingly, the effective channel width of the transfer gate transistor is further adjusted, the effective channel width of the transfer gate transistor and the pull-down transistor is made to have a difference, and the saturation current ratio between the transfer gate transistor and the pull-down transistor is adjusted, and the read margin and the write margin of the SRAM device are adjusted accordingly; and in the step of removing the part width preset gate structure located between the pull-up region and the transfer region and extending in the transfer region, a part of the second channel structure below the preset gate structure is removed, so that the number of the second channel structure of the transfer region is adjusted by the process of gate cutting, which is not only beneficial to improve the process compatibility and the process integration, but also beneficial to save the mask, and further reduce the cost. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 is a local layout schematic diagram of an SRAM memory array;

[0014] Figure 2 is a top view schematic diagram of an SRAM unit;

[0015] Figure 3 is Figure 2 is an equivalent circuit structure schematic diagram of an SRAM unit in the embodiment;

[0016] Figure 4 is a top view schematic diagram of an SRAM unit in an embodiment of the present application;

[0017] Figure 5is Figure 4 a cross-sectional view along the a-a1 direction;

[0018] Figure 6 is Figure 4 a cross-sectional view along the b-b1 direction;

[0019] Figures 7 to 22 is a structural schematic diagram corresponding to each step in an embodiment of the method for forming the SRAM cell. DETAILED DESCRIPTION

[0020] Figure 1 is a partial layout schematic diagram of an SRAM memory array. The memory array includes a plurality of array-arranged memory cells (SRAM cells).

[0021] Figure 2 is a layout schematic diagram of an SRAM cell (SRAM cell). Figure 3 shows an equivalent circuit structure schematic diagram of an SRAM cell (SRAM cell).

[0022] Taking a 6T SRAM memory cell as an example, in a 6T SRAM memory cell, two pull-up transistors, a first pull-up transistor PU1 and a second pull-up transistor PU2, two pull-down transistors, a first pull-down transistor PD1 and a second pull-down transistor PD2, and two pass-gate transistors, a first pass-gate transistor PG1 and a second pass-gate transistor PG2, are usually included.

[0023] The first pull-down transistor PD1 is connected to the first pull-up transistor PU1, and the second pull-down transistor PD2 is connected to the second pull-up transistor PU2. The first pass-gate transistor PG1 is connected to the first pull-down transistor PD1, and the second pass-gate transistor PG2 is connected to the second pull-down transistor PD2.

[0024] As known from the background art, for a static random access memory cell, both read margin and write margin are related to the proportion of the saturation drive current (Idsat) between the pull-up transistor, the pull-down transistor and the pass-gate transistor.

[0025] Specifically, for an SRAM memory cell, the proportion of the saturation drive current of the pull-up transistor, the pull-down transistor and the pass-gate transistor is adjusted via the effective channel width of each of the pull-up transistor, the pull-down transistor and the pass-gate transistor, more specifically, the number of channels included in each of the pull-up transistor, the pull-down transistor and the pass-gate transistor is adjusted.

[0026] As Figure 2As shown, and each transistor in the SRAM cell is a fin field effect transistor as an example, the SRAM cell comprises:

[0027] A substrate (not shown) comprising a memory cell region, the memory cell region comprising a first region 10I and a second region 10II which are symmetrically adjacent, each of the first region 10I and the second region 10II comprising: a pull-up region 10PU for forming a pull-up transistor, a pull-down region 10PD for forming a pull-down transistor, and a pass region 10PG for forming a pass transistor; the pull-up region 10PU comprising a first pull-up region and a second pull-up region located in the first region 10I and the second region 10II respectively, the pull-down region 10PD comprising a first pull-down region and a second pull-down region located in the first region 10I and the second region 10II respectively; the pass region 10PG comprising a first pass region and a second pass region located in the first region 10I and the second region 10II respectively; a plurality of fins on the substrate, the plurality of fins being arranged in parallel and spaced apart; in the memory cell, the fins comprise a first fin 11 extending along the arrangement direction of the pass region 10PG and the pull-down region 10PD and located in the pass region 10PG and the pull-down region 10PD, and a second fin 12 located in the pull-up region 10PU, the first fin 11 being a plurality; a plurality of gate structures located on the substrate and across the fins, the plurality of gate structures being arranged in parallel and spaced apart, the extension direction of the gate structure being perpendicular to the extension direction of the fin; the gate structure comprises: a pass gate 13 located in the pass region 10PG, and a pull gate structure 14 located in the pull-up region 10PU and the pull-down region 10PD, the pull-down region 10PD and the pull-up region 10PU sharing the pull gate structure 14; the ends of the pass gate 13 and the pull gate 14 are oppositely arranged along the extension direction of the gate structure; a fin cut structure 15 is located at the end of a plurality of fins below the pass gate structure 13 along the extension direction of the fin; a source / drain doping region 16 is located in the fin on both sides of the gate structure.

[0028] In the above SRAM cell, the end of the fin below the pass gate structure 13 along the extension direction of the fin is provided with a fin cut structure.

[0029] Specifically, the fin is used to provide a conductive channel of a fin field effect transistor, and in the forming process of the SRAM cell, after the fin is formed on the patterned semiconductor layer, a part of the number of fins of the transfer region 10PG is removed before the gate structure or the dummy gate structure is formed, so that the number of fins covered by the gate structure of the transfer region 10PG is less than the number of fins covered by the gate structure of the pull-down region, thereby playing a role of adjusting the number of fins of the transfer region 10PG, and further making the effective channel width of the transfer region 10PG and the pull-down region 10PD different, and correspondingly adjusting the saturation current ratio among the transfer transistor, the pull-down transistor and the pull-up transistor, and further adjusting the read and write margins of the SRAM memory device.

[0030] However, in the forming process of the above-mentioned SRAM cell, the saturation current ratio among the transfer transistor, the pull-down transistor and the pull-up transistor is adjusted by removing a part of the number of fins of the transfer region 10PG, which requires an additional mask to be used, and is not conducive to cost saving.

[0031] In order to solve the technical problem, the embodiment of the present application provides an SRAM cell, wherein a cutting structure is arranged in the SRAM cell, and the cutting structure is located between the transfer device gate and the pull device gate along the extension direction of the device gate structure, and penetrates a part of the number of second channel structures between the transfer device gate and the pull device gate, so that the number of second channel structures of the transfer region is adjusted by the cutting structure, the number of channels included in the transfer transistor is correspondingly adjusted, and the effective channel width of the transfer transistor is further adjusted, so that the effective channel width of the transfer transistor and the pull-down transistor has a difference, and the saturation current ratio among the transfer transistor, the pull-down transistor and the pull-up transistor is further adjusted, and the read margin and the write margin of the SRAM device are correspondingly adjusted.

[0032] To solve the technical problem, the embodiment of the present application also provides a SRAM cell forming method, after forming a source-drain doped region, removing a preset gate structure above a part of the second channel structure between the pull-up region and the transfer region and extending in the transfer region and a part of the second channel structure below the preset gate structure along the extension direction of the gate structure, forming a cut opening in the second channel structure of the transfer region, thereby adjusting the number of the second channel structures of the transfer region, adjusting the number of channels included in the transfer gate transistor accordingly, adjusting the effective channel width of the transfer gate transistor, making the effective channel width of the transfer gate transistor and the pull-down transistor different, thereby adjusting the saturation current ratio of the transfer gate transistor and the pull-down transistor, adjusting the read margin and the write margin of the SRAM device accordingly; and in the step of removing the preset gate structure with a part of the width extending between the pull-up region and the transfer region and in the transfer region, removing a part of the second channel structure below the preset gate structure, thereby adjusting the number of the second channel structures of the transfer region by the process of gate cutting, which is not only beneficial to improve the process compatibility and the process integration, but also beneficial to save the mask, thereby reducing the cost.

[0033] To make the above-mentioned purposes, features and advantages of the embodiments of the present application more obvious and easy to understand, the specific embodiments of the present application are described in detail below with reference to the drawings. Refer to Figures 4 to 6 , Figure 4 is a top view, Figure 5 is Figure 4 is a sectional view along the a-a1 direction, Figure 6 is Figure 4 is a sectional view along the b-b1 direction, which shows a structural schematic diagram of an embodiment of the SRAM cell of the present application.

[0034] As Figures 4 to 6As shown, in the embodiment, the SRAM cell comprises: a substrate 100, the substrate 100 comprising a memory cell region 100C, the memory cell region 100C comprising a first region 100I and a second region 100II which are symmetrically and adjacently connected, the first region 100I and the second region 100II each comprising a pull-up region 100PU, a pull-down region 100PD and a transfer region 100PG, which are respectively used for forming a pull-up transistor, a pull-down transistor and a transfer gate transistor; a plurality of protruding structures 115 which are separately arranged on the substrate 100, the protruding structures 115 comprising a protruding portion 112 and a channel structure 110 which is arranged on the protruding portion 112, and the plurality of protruding structures 115 are arranged in parallel and spaced apart; the channel structure 110 comprises a first channel structure 110(1) which is arranged in the pull-up region 100PU, and a plurality of second channel structures 110(2) which are arranged along the arrangement direction of the transfer region 100PG and the pull-down region 100PD and are arranged in the transfer region 100PG and the pull-down region 100PD; an isolation layer 120 which is arranged on the substrate 100 and surrounds the protruding portion 112 and exposes the channel structure 110; a plurality of device gate structures 180 which are arranged on the isolation layer 120 and cross the channel structure 110, the plurality of device gate structures 180 are arranged in parallel and spaced apart, and the extension direction of the device gate structure 180 is perpendicular to the extension direction of the channel structure 110; the device gate structure 180 comprises a transfer device gate 180g which is arranged in the transfer region 100PG, and a pull device gate structure 180p which is arranged in the pull-up region 100PU and the pull-down region 100PD; along the extension direction of the device gate structure 180, the end portions of the transfer device gate 180g and the pull device gate 180p are oppositely arranged, and a gate cut-off region 180c is arranged between the transfer device gate 180g and the pull device gate 180p, and along the projection plane which is parallel to the substrate 100, the gate cut-off region 180c crosses a part of the plurality of second channel structures 110(2) in the transfer region 100PG; a source / drain doped region 140 which is arranged in the channel structure 110 on both sides of the device gate structure 180, and the number of the protruding portions 112 which are arranged below the source / drain doped region 140 in the transfer region 100PG is the same as the number of the protruding portions 112 which are arranged below the source / drain doped region 140 in the pull-down region 100PD; a cut-off structure 170 which is arranged between the transfer device gate 180g and the pull device gate 180p along the extension direction of the device gate structure 180, and penetrates the second channel structure 110(2) below the gate cut-off region 180c.

[0035] The substrate 100 is used to provide a process platform for forming a semiconductor structure.

[0036] In this embodiment, the material of the substrate 100 includes one or more of monocrystalline silicon, germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium arsenide. As an example, the substrate 100 is a silicon substrate, i.e., the material of the substrate 100 is monocrystalline silicon.

[0037] The storage unit region 100C is used to form storage units, the number of which is a plurality, and the plurality of storage units are arranged in a matrix on the substrate 100 to constitute a storage array. The storage array is used to form an SRAM memory device.

[0038] In this embodiment, the storage unit is an SRAM unit.

[0039] In this embodiment, the SRAM unit is taken as an example of a 6T SRAM unit for illustration.

[0040] Correspondingly, in this embodiment, the pull-up transistor includes a first pull-up transistor and a second pull-up transistor, which correspond to the pull-up region 100PU of the first region 100I and the pull-up region 100PU of the second region 100II, respectively; the pull-down transistor includes a first pull-down transistor and a second pull-down transistor, which correspond to the pull-down region 100PD of the first region 100I and the pull-down region 100PD of the second region 100II, respectively; and the transfer gate transistor includes a first transfer gate transistor and a second transfer gate transistor, which correspond to the transfer region 100PG of the first region 100I and the transfer region 100PG of the second region 100II, respectively.

[0041] Among them, the first pull-down transistor and the first pull-up transistor share the pull device gate structure 100p; the first pull-down transistor and the first transfer gate transistor share a part of the number of second channel structures 110(2).

[0042] In other embodiments, the SRAM unit can also be an 8T SRAM unit or other types of SRAM units.

[0043] The protruding part 112 is used to support the channel structure 110. In this embodiment, the material of the protruding part 112 includes one or more of monocrystalline silicon, germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium arsenide. As an example, the material of the protruding part 112 is silicon.

[0044] In this embodiment, the protruding part 112 and the substrate 100 are of an integrated structure.

[0045] The channel structure 110 is used to provide a conductive channel of a transistor.

[0046] In this embodiment, the material of the channel structure 110 includes one or more of monocrystalline silicon, germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium arsenide. As an example, the material of the channel structure 110 is the same as the material of the substrate 100, and the material of the channel structure 110 is monocrystalline silicon.

[0047] In this embodiment, the number of the second channel structures 110(2) is multiple, so as to adjust the number of the second channel structures 110(2) of the transfer region 180g by adjusting the number of the second channel structures 110(2) penetrated by the cut-off structure 170, and further adjust the effective channel width of the transfer transistor.

[0048] For simplicity of illustration, this embodiment is described by taking an example of two second channel structures 110(2). In other embodiments, the number of the second channel structures can also be greater than two.

[0049] As an example, the protruding structure 115 is a fin, and the channel structure 110 is a corresponding effective fin, which is used to provide a conductive channel of a fin field effect transistor. The channel structure 110 and the protruding structure 112 are an integrated structure.

[0050] In other embodiments, other types of transistors can also be formed, such as a gate-all-around (GAA) transistor. Accordingly, the channel structure is a channel structure layer suspended on the protruding structure, and the channel structure layer includes one or more channel layers suspended in a spaced manner.

[0051] The top surface of the isolation layer 120 is lower than the top surface of the channel structure 110.

[0052] The isolation layer 120 is used to isolate adjacent protruding structures 112, and is also used to isolate the substrate 100 and a subsequent gate structure.

[0053] The material of the isolation layer 120 is an insulating material. In this embodiment, the material of the isolation layer 120 includes one or two of silicon oxide, silicon nitride, and silicon oxynitride.

[0054] The device gate structure 180 is used to control the opening or closing of the conductive channel.

[0055] In this embodiment, the device gate structure 180 includes a gate dielectric layer (not shown in the figure) and a gate electrode layer (not shown in the figure) located on the gate dielectric layer.

[0056] The gate dielectric layer is used to realize insulation between the gate electrode layer and the conductive channel. The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, Al2O3, silicon oxide and nitrogen-doped silicon oxide.

[0057] The gate electrode layer is used as an external electrode for connecting the device gate structure 180 to an external circuit.

[0058] In this embodiment, the device gate structure 180 is a metal gate structure, and the material of the gate electrode layer is metal.

[0059] The material of the gate electrode layer includes any one or more of TiAl, TiALC, TaAlN, TiAlN, MoN, TaCN, AlN, Ta, TiN, TaN, TaSiN, TiSiN, W, Co, Al, Cu, Ag, Au, Pt and Ni.

[0060] In this embodiment, the device gate structure 180 includes a transmission device gate 180g located in the transmission region 100PG, and a pull device gate structure 180p located in the pull-up region 100PU and the pull-down region 100PD. Along the extension direction of the device gate structure 180, the ends of the transmission device gate 180g and the pull device gate 180p are oppositely arranged, and a gate cut-off region 180c is arranged between the transmission device gate 180g and the pull device gate 180p, which spans a number of second channel structures 110(2) in the transmission region 100PG along a projection plane parallel to the substrate 100.

[0061] Along the extension direction of the device gate structure 180, the ends of the transmission device gate 180g and the pull device gate 180p are oppositely arranged, so as to realize the disconnection of the transmission device gate 180g and the pull device gate 180p in the gate cut-off region 180c.

[0062] In addition, along the projection plane parallel to the substrate 100, the gate cut-off region 180c spans a number of second channel structures 110(2) in the transmission region 100PG, so as to adjust the number of second channel structures below the gate cut-off region penetrated by the cut-off structure, and further adjust the effective channel width of the transmission region 100PG.

[0063] In this embodiment, taking the pull-up transistor, the pull-down transistor and the transmission gate transistor in the SRAM cell as an example, the protruding structure 115 is a fin, the channel structure 110 is an effective fin, and the device gate structure 180 covers part of the top and part of the sidewall of the effective fin.

[0064] In other embodiments, when the pull-up transistor, the pull-down transistor and the pass-gate transistor are all fin field effect transistors, the device gate structure is a gate structure layer suspended on a protrusion, and the gate structure layer includes one or more channel layers suspended at intervals.

[0065] The device gate structure 180 is in a plurality, and the device gate structures 180 are arranged at intervals along the extension direction of the channel structure 110, and the extension direction of the device gate structure 180 is perpendicular to the extension direction of the channel structure 110.

[0066] In this embodiment, the SRAM cell is taken as an example of a 6T SRAM cell.

[0067] In this embodiment, a gate sidewall 135 is further formed on the sidewall of the device gate structure 180.

[0068] The gate sidewall 135 is used to protect the sidewall of the device gate structure 180, and the gate sidewall 135 is also used to define the formation position of the source / drain doped region.

[0069] The material of the gate sidewall 135 can be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon oxycarbide, boron nitride and boron carbonitride, and the gate sidewall 135 can be a single-layer structure or a stacked structure. In this embodiment, the gate sidewall 135 is a single-layer structure, and the material of the gate sidewall 135 is silicon nitride.

[0070] In device operation, the source / drain doped region 140 is used to provide a carrier source. In this embodiment, the source / drain doped region 140 includes a stress layer doped with ions, and the stress layer is used to provide stress to the channel, thereby improving the carrier mobility of the channel.

[0071] Specifically, when an NMOS transistor is formed, the material of the source / drain doped region 140 is a stress layer doped with N-type ions, the material of the stress layer includes Si or SiC, and the stress layer provides a tensile stress effect to the channel region of the NMOS transistor, thereby facilitating the improvement of the carrier mobility of the NMOS transistor, wherein the N-type ions are P ions, As ions or Sb ions.

[0072] When a PMOS transistor is formed, the material of the source / drain doped region 140 is a stress layer doped with P-type ions, the material of the stress layer includes Si or SiGe, and the stress layer provides a compressive stress effect to the channel region of the PMOS transistor, thereby facilitating the improvement of the carrier mobility of the PMOS transistor, wherein the P-type ions are B ions, Ga ions or In ions.

[0073] In this embodiment, the number of protrusions 112 under the source-drain doped region 140 in the transfer region 100PG is the same as the number of protrusions 112 under the source-drain doped region 140 in the pull-down region 100PD. Accordingly, in the transfer region 100PG, the volume of the source-drain doped region 140 on both sides of the transfer device gate 180g is equivalent, thereby facilitating the increase of the stress in the source-drain doped region 140 in the transfer region 100PG.

[0074] It is to be noted that in this embodiment, in the first region I, the transfer device gate 180g shares the source-drain doped region 140 with the pull device gate 180p in the pull-down region 100PD; in the second region II, the transfer device gate 180g shares the source-drain doped region 140 with the pull device gate 180p in the pull-down region 100PD.

[0075] The cut-off structure 170 is located in the gate cut-off region 180c, for isolating the transfer gate 130g from the pull gate 130p.

[0076] The cut-off structure 170 penetrates the second channel structure 110(2) under the gate cut-off region 180c, thereby adjusting the number of the second channel structure 110(2) in the transfer region 180g through the cut-off structure 170, accordingly adjusting the number of channels included in the transfer gate transistor, and further adjusting the effective channel width of the transfer gate transistor, so as to make the effective channel width between the transfer gate transistor and the pull-down transistor, and the pull-up transistor different, and further adjusting the saturation current ratio between the transfer gate transistor and the pull-down transistor, and the pull-up transistor, accordingly adjusting the read margin and the write margin of the SRAM device.

[0077] The material of the cut-off structure 170 is a dielectric material. In this embodiment, the material of the cut-off structure 170 includes one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon carbon nitride, silicon carbon oxynitride, boron nitride, and boron carbon nitride. As an embodiment, the material of the cut-off structure 170 is silicon oxide.

[0078] In the embodiment, the sidewall of the cut-off structure 170 is flush with the sidewall of the device gate structure 180 along the extending direction. Specifically, in the forming process of the SRAM cell, before the device gate structure 180 is formed, a dummy gate structure is also formed on the isolation layer 120 and across the channel structure 110, which is used to occupy a space position for forming the device gate structure 180. In the process of gate cut-off processing of the dummy gate structure, the channel structure below the gate cut-off region 180c is cut off, thereby facilitating the simplification of the process flow, the improvement of the process compatibility and the process integration, and the saving of one mask. Correspondingly, the channel structure below the gate cut-off region 180c is cut off, the sidewall of the cut-off opening formed is flush with the sidewall of the dummy gate structure, and the sidewall of the cut-off structure 170 formed in the cut-off opening is flush with the sidewall of the device gate structure 180 along the extending direction.

[0079] In the embodiment, the number of the second channel structures 110(2) is two, and the number of the second channel structures 110(2) penetrated by the cut-off structure 170 is one, which are taken as examples for description. In other embodiments, the number of the second channel structures can be greater than two, and the number of the second channel structures penetrated by the cut-off structure can be one or more.

[0080] In the embodiment, the cut-off structure 170 also penetrates the partial thickness protrusion 112 below the gate cut-off region 180c, thereby increasing the depth of the cut-off structure 170 to improve the isolation effect of the cut-off structure 170, which is conducive to preventing the generation of leakage current at the bottom of the cut-off structure 170 and improving the performance of the SRAM cell.

[0081] In the embodiment, the SRAM cell further comprises an interlayer dielectric layer 150 located on the isolation layer 120 at the side of the device gate structure 180 and covering the source / drain doped region 140. Specifically, the interlayer dielectric layer 150 also covers the sidewall of the gate sidewall 135.

[0082] The interlayer dielectric layer 150 is used to isolate adjacent devices.

[0083] Therefore, the material of the interlayer dielectric layer 150 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. In the embodiment, the material of the interlayer dielectric layer 150 is silicon oxide.

[0084] In the embodiment, for the convenience of illustration and description, only the interlayer dielectric layer 150, the isolation layer 120, and the gate sidewall 135 are shown in the cross-sectional view.

[0085] In the embodiment, the SRAM cell further comprises: a first source / drain contact structure (not shown) located above and in contact with the source / drain doping regions 140 of the pull-down region 100PD and the pull-up region 100PU in the first region 100I; a second source / drain contact structure (not shown) located above and in contact with the source / drain doping regions 140 of the pull-down region 100PD and the pull-up region 100PU in the second region 100II, the first source / drain contact structure being spaced apart from the second source / drain contact structure; a first interconnection structure (not shown) connecting the source / drain doping regions 140 of the pull-up region 100PU in the first region 100I with the pull device gate 100p in the second region 100II; and a second interconnection structure (not shown) connecting the source / drain doping regions 140 of the pull-up region 100PU in the second region 100II with the pull device gate 100p in the first region 100I.

[0086] In the first region 100I, the source / drain doping regions 140 of the pull-down region 100PD and the pull-up region 100PU share the first source / drain contact structure. In the second region 100II, the source / drain doping regions 140 of the pull-down region 100PD and the pull-up region 100PU share the second source / drain contact structure.

[0087] The first interconnection structure is used to connect the source / drain doping regions 140 of the pull-up region 100PU in the first region 100I with the pull device gate 100p in the second region 100II. The second interconnection structure is used to connect the source / drain doping regions 140 of the pull-up region 100PU in the second region 100II with the pull device gate 100p in the first region 100I.

[0088] In the SRAM cell, the first pull-down transistor PD1 is connected to the first pull-up transistor PU1, and the second pull-down transistor PD2 is connected to the second pull-up transistor PU2.

[0089] Specifically, the source / drain doping regions 140 in the first pull-down transistor PD1 are connected to the source / drain doping regions 140 of the first pull-up transistor PU1 through the first source / drain contact structure, and the source / drain doping regions 140 in the second pull-down transistor PD2 are connected to the source / drain doping regions 140 of the second pull-up transistor PU2 through the second source / drain contact structure.

[0090] In the embodiment, the first source / drain contact structure and the second source / drain contact structure, the first interconnection structure, and the second interconnection structure are made of a conductive material, such as one or more of Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti, and TiN.

[0091] Correspondingly, the application also provides an SRAM memory device, comprising a storage array, the storage array comprising one or more array-arranged storage units, the storage unit being the SRAM unit provided by the embodiment of the application.

[0092] As can be known from the foregoing embodiment, the embodiment of the application adjusts the number of second channel structures of the transmission region by the cutting structure, correspondingly adjusts the number of channels included in the transmission gate transistor, further adjusts the effective channel width of the transmission gate transistor, makes the effective channel width of the transmission gate transistor and the pull-down transistor have a difference, and further adjusts the saturation current ratio between the transmission gate transistor and the pull-down transistor and the pull-up transistor, correspondingly flexibly adjusts the read margin and the write margin of the SRAM memory device.

[0093] Correspondingly, the application also provides a forming method of the SRAM unit. Figures 7 to 22 It is a structure schematic diagram corresponding to each step in the embodiment of the forming method of the SRAM unit.

[0094] The forming method of the SRAM unit in the embodiment will be described in detail below with reference to the drawings.

[0095] Reference Figures 7 to 8 , Figure 7 It is a top view, Figure 8 It is Figure 7 It is a sectional view along the a-a1 direction, a substrate 100 is provided, the substrate 100 comprising a storage unit region 100C, the storage unit region 100C comprising a first region 100I and a second region 100II which are symmetrically adjacent and connected, the first region 100I and the second region 100II both comprising a pull-up region 100PU, a pull-down region 100PD and a transmission region 100PG, which are respectively used for forming a pull-up transistor, a pull-down transistor and a transmission gate transistor; a plurality of discrete protruding structures 115 are formed on the substrate 100, the protruding structure 115 comprising a protruding part 112 and a channel structure 110 located on the protruding part 112, a plurality of protruding structures 115 are arranged in parallel and spaced apart; the channel structure 110 comprises a first channel structure 110(1) located in the pull-up region 100PU, and a plurality of second channel structures 110(2) extending along the arrangement direction of the transmission region 100PG and the pull-down region 100PD and located in the transmission region 100PG and the pull-down region 100PD; the number of the second channel structures 110(2) of the transmission region 100PG and the pull-down region 100PD is the same.

[0096] The substrate 100 is used for providing a process platform for the formation of a semiconductor structure.

[0097] In this embodiment, the material of the substrate 100 includes one or more of monocrystalline silicon, germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium arsenide. As an example, the substrate 100 is a silicon substrate, i.e., the material of the substrate 100 is monocrystalline silicon.

[0098] The storage unit region 100C is used to form storage units, the number of which is plural, and the plural storage units are arranged in a matrix on the substrate 100 to constitute a storage array. The storage array is used to form an SRAM memory device.

[0099] In this embodiment, the storage unit is an SRAM unit.

[0100] In this embodiment, the SRAM unit is taken as an example of a 6T SRAM unit for illustration.

[0101] Correspondingly, in this embodiment, the pull-up transistor includes a first pull-up transistor and a second pull-up transistor, which correspond to the pull-up region 100PU of the first region 100I and the pull-up region 100PU of the second region 100II, respectively; the pull-down transistor includes a first pull-down transistor and a second pull-down transistor, which correspond to the pull-down region 100PD of the first region 100I and the pull-down region 100PD of the second region 100II, respectively; and the transfer gate transistor includes a first transfer gate transistor and a second transfer gate transistor, which correspond to the transfer region 100PG of the first region 100I and the transfer region 100PG of the second region 100II, respectively.

[0102] In other embodiments, the SRAM unit can also be an 8T SRAM unit or other types of SRAM units.

[0103] The protruding portion 112 is used to support the channel structure 110. In this embodiment, the material of the protruding portion 112 includes one or more of monocrystalline silicon, germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium arsenide. As an example, the material of the protruding portion 112 is silicon.

[0104] In this embodiment, the protruding portion 112 and the substrate 100 are of an integrated structure.

[0105] The channel structure 110 is used to provide a conductive channel of a transistor.

[0106] In this embodiment, the material of the channel structure 110 includes one or more of monocrystalline silicon, germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium arsenide. As an example, the material of the channel structure 110 is the same as that of the substrate 100, and the material of the channel structure 110 is monocrystalline silicon.

[0107] In the embodiment, the number of the second channel structures 110(2) in the transfer region 100PG and the pull-down region 100PD is the same in the step of providing the substrate. The second channel structure 110(2) is an integrated structure extending along the arrangement direction of the transfer region 100PG and the pull-down region 100PD.

[0108] In the embodiment, the number of the second channel structures 110(2) is multiple, so as to adjust the effective channel width of the transfer transistor by removing part of the second channel structures 110(2) in the transfer region 100PG.

[0109] For simplicity of description, the number of the second channel structures 110(2) is two in the embodiment. In other embodiments, the number of the second channel structures can be more than two.

[0110] As an example, the protruding structure 115 is a fin, and the channel structure 110 is an effective fin for providing a conductive channel of a fin field effect transistor. The channel structure 110 and the protruding structure 112 are an integrated structure.

[0111] In other embodiments, other types of transistors can also be formed, such as a gate-all-around (GAA) transistor. Accordingly, the channel structure is a channel structure layer suspended on the protruding structure, and the channel structure layer includes one or more channel layers suspended at intervals.

[0112] In the step of providing the substrate, the channel structure is a channel structure layer, and a sacrificial layer is further formed between adjacent channel layers or between the bottom of the channel layer and the protruding structure. The sacrificial layer is used to occupy a space position for forming a device gate structure, and the sacrificial layer is also used to support the channel layer, thereby providing a process basis for forming the channel layer suspended at intervals.

[0113] For detailed description of the sacrificial layer, the embodiment will not be described here.

[0114] Continuing to refer to Figure 8 An isolation layer 120 is formed on the substrate 100 to surround the protruding structure 112, and the isolation layer 120 exposes the channel structure 110. The top surface of the isolation layer 120 is lower than the top surface of the channel structure 110.

[0115] The isolation layer 120 is used to isolate adjacent protruding structures 112, and the isolation layer 120 is also used to isolate the substrate 100 and the subsequent gate structure.

[0116] The material of the isolation layer 120 is an insulating material. In the embodiment, the material of the isolation layer 120 includes one or two of silicon oxide, silicon nitride, and silicon oxynitride.

[0117] Reference Figures 9 to 11 , Figure 9 is a top view, Figure 10 is Figure 9 is a sectional view along a-a1 direction, Figure 11 is Figure 9 is a sectional view along b-b1 direction, a plurality of gate structures 130 are formed on the isolation layer 120, the plurality of gate structures 130 are arranged in parallel and spaced apart, and the extending direction of the gate structure 130 is perpendicular to the extending direction of the channel structure 110; the gate structure 130 includes a preset gate structure 130d located in the transfer region 100PG and extending to the adjacent pull-up region 100PU and pull-down region 100PD.

[0118] In the embodiment, the gate structure 130 is located on the isolation layer 120 and covers part of the top and part of the sidewall of the fin 110.

[0119] The gate structure 130 can be a device gate structure or a dummy gate structure. In the embodiment, the gate structure 130 is taken as an example of a dummy gate structure, and the gate structure 130 is used to occupy a space position for forming a device gate structure.

[0120] Specifically, the gate structure 130 includes a dummy gate oxide layer (not shown in the figure) and a dummy gate layer (not shown in the figure) located on the dummy gate oxide layer.

[0121] In the embodiment, the gate structure 130 is a polysilicon gate structure or an amorphous silicon gate structure. The material of the dummy gate oxide layer can be silicon oxide or nitrogen-doped silicon oxide; and the material of the dummy gate layer is polysilicon or amorphous silicon.

[0122] The number of the gate structure 130 is multiple, and the plurality of gate structures 130 are arranged in parallel and spaced apart along the extending direction of the channel structure 110, and the extending direction of the gate structure 130 is perpendicular to the extending direction of the channel structure 110.

[0123] The gate structure 130 includes a preset gate structure 130d located in the transfer region 100PG and extending to the adjacent pull-up region 100PU and pull-down region 100PD, and the preset gate structure 130d is subsequently cut off to isolate the preset gate structure 130d between the transfer region 100PG and the adjacent pull-up region 100PU.

[0124] In the embodiment, the preset gate structure 130d extends along a direction perpendicular to the extending direction of the channel structure 110, and the preset gate structure 130d sequentially spans the transfer region 100PG, the pull-up region 100PU and the pull-down region 100PD.

[0125] In this embodiment, the SRAM cell is taken as an example of a 6T SRAM cell, and the SRAM cell includes a first region 100I and a second region 100II. The number of preset gate structures 130d is two.

[0126] In this embodiment, a gate sidewall 135 is further formed on the sidewall of the gate structure 130.

[0127] The gate sidewall 135 is used to protect the sidewall of the gate structure 130, and the gate sidewall 135 is also used to define the formation position of the source / drain doped region.

[0128] The material of the gate sidewall 135 can be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, or silicon oxycarbide, boron nitride, and boron carbonitride. The gate sidewall 135 can be a single-layer structure or a stacked structure. In this embodiment, the gate sidewall 135 is a single-layer structure, and the material of the gate sidewall 135 is silicon nitride.

[0129] Continuing to refer to Figures 9 to 11 The source / drain doped region 140 is formed in the channel structure 110 on both sides of the gate structure 130, and the number of protrusions 112 under the source / drain doped region 140 of the transfer region 100PG is the same as the number of protrusions 112 under the source / drain doped region 140 of the pull-down region 100PD.

[0130] In device operation, the source / drain doped region 140 is used to provide a carrier source. In this embodiment, the source / drain doped region 140 includes a stress layer doped with ions, and the stress layer is used to provide stress for the channel, thereby improving the carrier mobility of the channel.

[0131] Specifically, when an NMOS transistor is formed, the material of the source / drain doped region 140 is a stress layer doped with N-type ions, the material of the stress layer includes Si or SiC, and the stress layer provides a tensile stress effect for the channel region of the NMOS transistor, thereby facilitating the improvement of the carrier mobility of the NMOS transistor, wherein the N-type ions are P ions, As ions, or Sb ions.

[0132] When a PMOS transistor is formed, the material of the source / drain doped region 140 is a stress layer doped with P-type ions, the material of the stress layer includes Si or SiGe, and the stress layer provides a compressive stress effect for the channel region of the PMOS transistor, thereby facilitating the improvement of the carrier mobility of the PMOS transistor, wherein the P-type ions are B ions, Ga ions, or In ions.

[0133] In the embodiment, in the process of forming the gate structure 130, in the first region I or the second region II, the number of the channel structures 110 across which the preset gate structure 130d of the transfer region 100PG is arranged is the same as the number of the channel structures 110 across which the preset gate structure 130d of the pull-down region 100PD is arranged. Therefore, the number of the protrusions 112 under the source-drain doped region 140 of the transfer region 100PG is the same as the number of the protrusions 112 under the source-drain doped region 140 of the pull-down region 100PD.

[0134] Correspondingly, in the step of forming the source-drain doped region 140, in the transfer region 100PG, the volume of the source-drain doped region 140 on both sides of the preset gate structure 130d is equivalent, thereby facilitating the increase of the stress in the source-drain doped region 140 of the transfer region 100PG.

[0135] It should be noted that, in the first region I, the preset gate structure 130d of the transfer region 100PG and the preset gate structure 130d of the pull-down region 100PD share the source-drain doped region 140; in the second region II, the preset gate structure 130d of the transfer region 100PG and the preset gate structure 130d of the pull-down region 100PD share the source-drain doped region 140.

[0136] It should be further noted that, in combination with reference to Figure 12 , a sectional view based on Figure 11 is shown, in the embodiment, the forming method of the SRAM cell further comprises: after forming the source-drain doped region 140, forming an interlayer dielectric layer 150 on the isolation layer 120 on both sides of the gate structure 130, the interlayer dielectric layer 150 covering the source-drain doped region 140. Specifically, the interlayer dielectric layer 150 also covers the sidewall of the gate sidewall 135.

[0137] The interlayer dielectric layer 150 is used to isolate adjacent devices.

[0138] Therefore, the material of the interlayer dielectric layer 150 is an insulating material, for example, one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. In the embodiment, the material of the interlayer dielectric layer 150 is silicon oxide.

[0139] In the embodiment, for the convenience of illustration and description, only the interlayer dielectric layer 150, the isolation layer 120, and the gate sidewall 135 are shown in the sectional view.

[0140] Reference is made to Figures 13 to 15 , Figure 13 is a top view, Figure 14 is Figure 13a-a1 direction, Figure 15 for Figure 13 a-b1 direction, after forming the source-drain doped region 140, the gate structure 130 and the channel structure 110 under the gate structure 130 are cut off, the preset gate structure 130d between the pull-up region 100PU and the transfer region 100PG and extending above the part number of the second channel structure 110(2) in the transfer region 100PG, and the part number of the second channel structure 110(2) under the preset gate structure 130d are removed, the cut-off opening 160 is formed in the preset gate structure 130d and the second channel structure 110(2) in the transfer region 100PG, the remaining preset gate structure 130d in the transfer region 100PG is used as a transfer gate 130g, and the remaining preset gate structure 130d in the pull-up region 100PU and the pull-down region 100PD is used as a pull gate 130p.

[0141] The gate structure 130 is cut off, so that the gate structure 130 of the transfer region 100PG and the gate structure 130 of the pull-down region 100PD are separated.

[0142] The gate structure 130 of the transfer region 100PG and the gate structure 130 of the pull-down region 100PD are separated by the cut-off opening 160, and the cut-off opening 160 is also used to cut off the part number of the second channel structure 110(2) in the transfer region 100PG. The cut-off opening 160 is also used to provide a spatial position for forming a cut-off structure.

[0143] The preset gate structure 130d between the pull-up region 100PU and the transfer region 100PG and extending above the part number of the second channel structure 110(2) in the transfer region, and the part number of the second channel structure 110(2) under the preset gate structure 130d are removed, the cut-off opening 160 is formed in the second channel structure 110(2) in the transfer region 100PG, so as to adjust the number of the second channel structure 110(2) in the transfer region 100PG, correspondingly adjust the number of channels included in the transfer gate transistor, and further adjust the effective channel width of the transfer gate transistor, so that the effective channel width between the transfer gate transistor and the pull-down transistor and the pull-up transistor has a difference, and further adjust the saturation current ratio between the transfer gate transistor and the pull-down transistor and the pull-up transistor, and correspondingly adjust the read margin and the write margin of the SRAM device.

[0144] And, in the step of removing the part width preset gate structure 130d between the pull-up region 100PU and the transfer region 100PG and extending to the transfer region 100PG, part number of the second channel structure 110(2) under the preset gate structure 130d is removed, so that the number of the second channel structure 110(2) of the transfer region is adjusted by the process of gate cut, which is not only beneficial to improve the process compatibility and the process integration, but also beneficial to save the mask, thereby reducing the cost.

[0145] In the embodiment, the number of the second channel structure 110(2) is two, and the number of the second channel structure 110(2) penetrated by the cut opening 160 is one. In other embodiments, the number of the second channel structure can be greater than two, and the number of the second channel structure penetrated by the cut opening can be one or more.

[0146] In the embodiment, in the step of cutting the gate structure 130 and the channel structure under the gate structure 130, part thickness of the protruding portion 112 under the part width preset gate structure 130d is also removed, which is beneficial to prevent the leakage current at the bottom of the cut opening 160, thereby improving the performance of the SRAM cell.

[0147] In the embodiment, the step of forming the cut opening 160 includes: forming a gate cut groove (not shown) between the gate structure 130 of the pull-up region 100PU and the gate structure 130 of the transfer region 100PG, and exposing part number of the second channel structure 110(2) of the transfer region 100PG under the gate cut groove; removing the second channel structure 110(2) under the gate cut groove, and forming a channel cut groove (not shown) in the second channel structure 110(2), the channel cut groove and the gate cut groove constitute the cut opening 160.

[0148] Wherein, the gate cut groove is used to realize the cut of the gate structure 130, and the channel cut groove is used to realize the cut of the second channel structure 110(2).

[0149] Specifically, the step of forming the gate cut groove further includes: before forming the cut groove, forming a cut mask layer (not shown in the figure) on the gate structure 130, the cut mask layer has a mask opening (not shown in the figure) formed therein, the mask opening is located between the pull-up region 100PU and the transfer region 100PG and extends to the part width preset gate structure 130d above the transfer region 100PG; the preset gate structure 130d under the mask opening is removed by taking the cut mask layer as a mask to form the gate cut groove.

[0150] ReferenceFigures 16 to 18 , Figure 16 is a top view, Figure 17 is Figure 16 is a sectional view along a-a1 direction, Figure 18 is Figure 16 is a sectional view along b-b1 direction, the cut-off structure 170 is formed in the cut-off opening 160.

[0151] The cut-off structure 170 is used for isolation between the transfer gate 130g and the pull gate 130p.

[0152] The material of the cut-off structure 170 is a dielectric material. In the embodiment, the material of the cut-off structure 170 includes one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, boron nitride and boron carbonitride. As an embodiment, the material of the cut-off structure 170 is silicon oxide.

[0153] In the embodiment, the step of forming the cut-off structure 170 includes: filling a dielectric material layer (not shown in the figure) in the cut-off opening 160, the dielectric material layer is also formed on the gate structure 130; removing the dielectric material layer on the top of the gate structure 130, and the remaining dielectric material layer filled in the cut-off opening 160 is used as the cut-off structure 170.

[0154] In the embodiment, one or more of chemical vapor deposition process, atomic layer deposition process, flow chemical vapor deposition process, plasma enhanced chemical vapor deposition process and high aspect ratio deposition process are used to form the dielectric material layer.

[0155] In the embodiment, a chemical mechanical polishing process is used to remove the dielectric material layer on the top of the gate structure 130.

[0156] It should be noted that in the embodiment, the gate structure 130 is a dummy gate structure; therefore, it is necessary to refer to Figures 19 to 21 , Figure 19 is a top view, Figure 20 is Figure 19 is a sectional view along a-a1 direction, Figure 21 is Figure 19 is a sectional view along b-b1 direction, after the cut-off structure 170 is formed, the method for forming the SRAM cell further includes: removing the dummy gate structure to form a gate opening (not shown in the figure); forming a device gate structure 180 in the gate opening.

[0157] The device gate structure 180 is used for controlling the opening or closing of the conductive channel.

[0158] In this embodiment, the device gate structure 180 includes a gate dielectric layer (not shown in the figure) and a gate electrode layer (not shown in the figure) on the gate dielectric layer.

[0159] The gate dielectric layer is used to realize insulation between the gate electrode layer and the conductive channel. The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, Al2O3, silicon oxide, and nitrogen-doped silicon oxide.

[0160] The gate electrode layer is used as an external electrode for connecting the device gate structure 180 to an external circuit.

[0161] In this embodiment, the device gate structure 180 is a metal gate structure, and the material of the gate electrode layer is metal.

[0162] The material of the gate electrode layer includes any one or more of TiAl, TiALC, TaAlN, TiAlN, MoN, TaCN, AlN, Ta, TiN, TaN, TaSiN, TiSiN, W, Co, Al, Cu, Ag, Au, Pt, and Ni.

[0163] In this embodiment, the device gate structure 180 includes a transmission device gate 180g in the transmission region 100PG, and a pull device gate structure 180p in the pull-up region 100PU and the pull-down region 100PD. Along the extension direction of the device gate structure 180, the ends of the transmission device gate 180g and the pull device gate 180p are oppositely arranged, and a gate cut-off region is between the transmission device gate 180g and the pull device gate 180p, which spans a number of second channel structures 110(2) in the transmission region 100PG along a projection plane parallel to the substrate 100.

[0164] In this embodiment, the channel structure 110 is an effective fin, and the device gate structure 180 covers part of the top and part of the sidewall of the effective fin.

[0165] In other embodiments, when a fully-enclosed gate transistor is formed, the channel structure is a channel layer, and a sacrificial layer is further formed between adjacent channel layers or between the channel layer and the protruding portion; in the step of forming a gate opening, the channel layer and the sacrificial layer are exposed; the method for forming the SRAM cell further includes: after the gate opening is formed, before the device gate structure is formed in the gate opening, removing the sacrificial layer through the gate opening to form a through slot, which is surrounded by adjacent channel layers or by the channel layer and the protruding portion, and the through slot is in communication with the gate opening.

[0166] Accordingly, a device gate structure is formed in the gate opening and the via, the device gate structure surrounding the channel layer.

[0167] In this embodiment, reference is made to Figure 22 , a top view based on Figure 19 The forming method of the SRAM cell further comprises: in the first region 100I, forming a first source-drain contact structure (not labeled) above and in contact with the source-drain doped regions 140 of the pull-down region 100PD and the pull-up region 100PU; in the second region 100II, forming a second source-drain contact structure (not labeled) above and in contact with the source-drain doped regions 140 of the pull-down region 100PD and the pull-up region 100PU, the first source-drain contact structure being spaced apart from the second source-drain contact structure; forming a first interconnection structure (not labeled) connecting the source-drain doped regions 140 of the pull-up region 100PU of the first region 100I and the pull device gate 100p of the second region 100II; forming a second interconnection structure (not labeled) connecting the source-drain doped regions 140 of the pull-up region 100PU of the second region II and the pull device gate 100p of the first region II.

[0168] In the first region 100I, the source-drain doped regions 140 of the pull-down region 100PD and the pull-up region 100PU share the first source-drain contact structure. In the second region II, the source-drain doped regions 140 of the pull-down region 100PD and the pull-up region 100PU share the second source-drain contact structure.

[0169] The first interconnection structure is used to connect the source-drain doped regions 140 of the pull-up region 100PU of the first region 100I and the pull device gate 100p of the second region 100II. The second interconnection structure is used to connect the source-drain doped regions 140 of the pull-up region 100PU of the second region II and the pull device gate 100p of the first region II.

[0170] In the SRAM cell, the first pull-down transistor PD1 is connected to the first pull-up transistor PU1, and the second pull-down transistor PD2 is connected to the second pull-up transistor PU2. Specifically, the source-drain doped regions 140 in the first pull-down transistor PD1 are connected to the source-drain doped regions 140 of the first pull-up transistor PU1 through the first source-drain contact structure, and the source-drain doped regions 140 in the second pull-down transistor PD2 are connected to the source-drain doped regions 140 of the second pull-up transistor PU2 through the second source-drain contact structure.

[0171] In this embodiment, the material of the first source / drain contact structure and the second source / drain contact structure, the first interconnection structure and the second interconnection structure is a conductive material, for example, one or more of Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti and TiN.

[0172] Although the present application has been disclosed with reference to the above embodiments, the present application is not limited to the above embodiments. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of the present application should be defined by the scope of the claims.

Claims

1. An SRAM cell, characterized in that, include: The substrate includes a memory cell region, which includes a centrally symmetrical and adjacent first region and a second region. The first region and the second region each include a pull-up region, a pull-down region, and a transmission region, which are respectively used to form a pull-up transistor, a pull-down transistor, and a transmission gate transistor. Multiple protrusion structures are discretely disposed on the substrate. Each protrusion structure includes a protrusion portion and a channel structure located on the protrusion portion. The multiple protrusion structures are arranged in parallel and spaced apart. The channel structure includes a first channel structure located in the pull-up region and multiple second channel structures extending along the arrangement direction of the transmission region and the pull-down region and located in the transmission region and the pull-down region. An isolation layer is located on the substrate and surrounds the protrusion, exposing the channel structure; Multiple device gate structures are located on the isolation layer and span the channel structure. The multiple device gate structures are arranged in parallel and spaced apart. The extension direction of the device gate structures is perpendicular to the extension direction of the channel structure. The device gate structure includes a transmission device gate located in the transmission region and a pull-up device gate structure located in the pull-up region and the pull-down region. Along the extension direction of the device gate structure, the ends of the transmission device gate and the pull-up device gate are disposed opposite to each other, and there is a gate cut-off region between the transmission device gate and the pull-up device gate. On a projection plane parallel to the substrate, the gate cut-off region spans a portion of the transmission region of the second channel structure. The source / drain doped regions are located within the channel structures on both sides of the gate structure of the device, and the number of protrusions below the source / drain doped regions in the transport region is the same as the number of protrusions below the source / drain doped regions in the pull-down region. The cut-off structure extends along the extension direction of the device gate structure, is located between the gate of the transmission device and the gate of the pull device, and penetrates the second channel structure below the gate cut-off region.

2. The SRAM cell as described in claim 1, characterized in that, The sidewall of the cut-off structure is flush with the sidewall of the device gate structure along the extension direction.

3. The SRAM cell as described in claim 1, characterized in that, The cutting structure also extends through a portion of the thickness protrusion below the gate cutting region.

4. The SRAM cell as described in claim 1, characterized in that, The pull-up transistor includes a first pull-up transistor and a second pull-up transistor, which correspond to the pull-up regions located in the first region and the second region, respectively. The pull-down transistor includes a first pull-down transistor and a second pull-down transistor, which respectively correspond to the pull-down areas located in the first region and the second region. The transmission gate transistor includes a first transmission gate transistor and a second transmission gate transistor, which respectively correspond to the transmission regions located in the first region and the second region. Wherein, the first pull-down transistor and the first pull-up transistor share the gate structure of the pull-up device; the first pull-down transistor and the first transmission gate transistor share a portion of the second channel structure.

5. The SRAM cell as claimed in claim 1, characterized in that, The material of the severing structure includes one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, boron nitride, and boron carbonitride.

6. The SRAM cell as claimed in claim 1, characterized in that, The SRAM cell further includes an interlayer dielectric layer, located on the isolation layer on the side of the device gate structure and covering the source / drain doped regions.

7. The SRAM cell as claimed in claim 1, characterized in that, The protruding structure is a fin, and the channel structure is an effective fin; the device gate structure covers part of the top and part of the sidewall of the fin. Alternatively, the channel structure is a channel structure layer suspended on the protrusion, the channel structure layer including one or more channel layers suspended at intervals; the device gate structure surrounds the channel layer.

8. The SRAM cell as claimed in claim 1, characterized in that, The substrate material includes one or more of the following: single-crystal silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride; The material of the protrusion includes one or more of the following: single crystal silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride; The materials of the channel structure include one or more of the following: single-crystal silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride.

9. The SRAM cell as claimed in claim 1, characterized in that, The gate structure of the device includes a gate dielectric layer and a gate electrode layer located on the gate dielectric layer.

10. The SRAM cell as claimed in claim 9, characterized in that, The material of the gate dielectric layer includes one or more of the following: HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, Al2O3, silicon oxide, and nitrogen-doped silicon oxide; The material of the gate electrode layer includes any one or more of TiAl, TiALC, TaAlN, TiAlN, MoN, TaCN, AlN, Ta, TiN, TaN, TaSiN, TiSiN, W, Co, Al, Cu, Ag, Au, Pt, and Ni.

11. An SRAM memory device, characterized in that, The storage array includes one or more storage cells arranged in an array, wherein the storage cells are SRAM cells as described in any one of claims 1-10.

12. A method for forming an SRAM cell, characterized in that, include: A substrate is provided, the substrate including a memory cell region, the memory cell region including a centrally symmetrical and adjacent first region and a second region, each of the first region and the second region including a pull-up region, a pull-down region and a transmission region, respectively used to form a pull-up transistor, a pull-down transistor and a transmission gate transistor; a plurality of discrete bump structures are formed on the substrate, each bump structure including a bump portion and a channel structure located on the bump portion, the plurality of bump structures being arranged in parallel and spaced apart; the channel structure includes a first channel structure located in the pull-up region, and a plurality of second channel structures extending along the arrangement direction of the transmission region and the pull-down region and located in the transmission region and the pull-down region; the number of second channel structures in the transmission region and the pull-down region is the same; An isolation layer is formed on the substrate surrounding the protrusion, the isolation layer exposing the channel structure; Multiple gate structures are formed across the channel structure on the isolation layer, and the multiple gate structures are arranged in parallel and spaced apart. The extending direction of the gate structure is perpendicular to the extending direction of the channel structure. The gate structure includes a preset gate structure located in the transmission region and extending to adjacent pull-up and pull-down regions. Source and drain doped regions are formed in the channel structures on both sides of the gate structure, and the number of protrusions below the source and drain doped regions in the transport region is the same as the number of protrusions below the source and drain doped regions in the pull-down region. After forming the source and drain doped regions, the gate structure and the channel structure below the gate structure are cut off. A portion of the preset width gate structure located between the pull-up region and the transport region and extending to the transport region along the extension direction of the gate structure is removed, as well as the second channel structure below the portion of the preset width gate structure. Cut-off openings are formed in the preset gate structure and in the second channel structure of the transport region. The remaining preset gate structure in the transport region is used as the transport gate, and the remaining preset gate structure in the pull-up region and the pull-down region is used as the pull gate. A cutting structure is formed within the cutting opening.

13. The method for forming an SRAM cell as described in claim 12, characterized in that, In the cutting process, a portion of the thickness of the protrusion below the pre-defined gate structure of a certain width is also removed.

14. The method for forming an SRAM cell as described in claim 12, characterized in that, The method for forming the SRAM cell further includes: after forming the source and drain doped regions, before performing the cut-off process, forming an interlayer dielectric layer on the isolation layers on both sides of the gate structure.

15. The method for forming an SRAM cell as described in claim 12, characterized in that, The step of forming the cut-off opening includes: forming a gate cut-off trench located between the gate structure of the pull-up region and the gate structure of the transmission region, exposing a portion of a second channel structure of the transmission region below the gate cut-off trench; removing the second channel structure below the gate cut-off trench, forming a channel cut-off trench within the second channel structure, the channel cut-off trench and the gate cut-off trench constituting the cut-off opening.

16. The method for forming an SRAM cell as described in claim 15, characterized in that, The step of forming the gate cut-off groove further includes: before forming the gate cut-off groove, forming a cut-off mask layer on the gate structure, wherein a mask opening is formed in the cut-off mask layer, and the mask opening is located between the pull-up region and the transmission region, and above a portion of the gate structure extending to the transmission region. Using the cutting mask layer as a mask, the preset gate structure below the mask opening is removed to form the gate cutting groove.

17. The method for forming an SRAM cell as described in claim 12, characterized in that, In the step of providing a substrate, the protrusion structure is a fin and the channel structure is an effective fin; or, the channel structure is a channel structure layer suspended on the protrusion, the channel structure layer including one or more channel layers spaced apart and suspended.

18. The method for forming an SRAM cell as described in claim 17, characterized in that, The gate structure is a pseudo-gate structure; The channel structure is an effective fin; After forming the cut-off structure, the method for forming the SRAM cell further includes: removing the dummy gate structure to form a gate opening; forming a device gate structure within the gate opening, the device gate structure covering a portion of the top and a portion of the sidewalls of the effective fin; or, In the step of providing a substrate, the channel structure is a channel structure layer, and a sacrificial layer is formed between adjacent channel layers or between the bottom of the channel layer and the protrusion; the method of forming the SRAM cell further includes: removing the pseudo-gate structure to form a gate opening, exposing the channel layer and the sacrificial layer; removing the sacrificial layer through the gate opening to form a through-slot, the through-slot being surrounded by adjacent channel layers or between the channel layer and the protrusion, the through-slot being connected to the gate opening; and forming a device gate structure within the gate opening and the through-slot, the device gate structure surrounding the channel layer.

19. The method for forming an SRAM cell as described in claim 12, characterized in that, The step of forming the cut-off structure includes: filling the cut-off opening with a dielectric material layer, the dielectric material layer also being formed on the gate structure; The dielectric material layer located on top of the gate structure is removed, and the remaining dielectric material layer filling the cut-off opening is used as the cut-off structure.

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