Semiconductor structure and method of manufacturing the same, memory, memory system

Abstract

This disclosure provides a semiconductor structure and its manufacturing method, as well as a memory. The semiconductor structure includes: a first semiconductor layer, an isolation structure, and a second semiconductor layer stacked sequentially; at least one first device, a portion of which is located in the first semiconductor layer; and at least one second device, a portion of which is located in the second semiconductor layer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor structure and its manufacturing method, a memory, and a memory system. Background Technology

[0002] As a typical non-volatile semiconductor memory, NAND (Not-And) flash memory has become a mainstream product in the memory market due to its high storage density, controllable production costs, suitable erase and programmable speeds, and retention characteristics. However, semiconductor memory still faces many challenges. Summary of the Invention

[0003] In view of the above, embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, a memory, and a memory system.

[0004] According to one aspect of this disclosure, a semiconductor structure is provided, comprising:

[0005] A first semiconductor layer, an isolation structure, and a second semiconductor layer are stacked sequentially.

[0006] At least one first device, wherein a portion of the structure of the first device is located in the first semiconductor layer;

[0007] At least one second device, wherein a portion of the structure of the second device is located in the second semiconductor layer.

[0008] In the above scheme, the operating voltage of the first device is higher than that of the second device.

[0009] In the above scheme, the semiconductor structure further includes:

[0010] A connection structure is located on one side of the first device and the second device and extends through the second semiconductor layer, the isolation structure and the first semiconductor layer, and the connection structure is electrically connected to the first device.

[0011] In the above scheme, the isolation structure includes gas isolation materials and / or solid isolation materials.

[0012] In the above scheme, the isolation structure includes gas isolation material and solid isolation material; wherein, the isolation structure at the orthographic projection of the first device and the second device onto the plane where the isolation structure is located includes gas isolation material.

[0013] In the above scheme, the semiconductor structure further includes:

[0014] A first insulating layer covers the surface of the first semiconductor layer away from the isolation structure;

[0015] The first device includes: a first doped region, a first gate structure, and a first interconnect structure electrically connected to both the first gate structure and the first doped region. The first doped region is located in the first semiconductor layer, and the first gate structure and the first interconnect structure are both located in the first insulating layer at positions corresponding to the first doped region.

[0016] In the above scheme, the semiconductor structure further includes:

[0017] A second insulating layer covers the surface of the second semiconductor layer away from the isolation structure;

[0018] The second device includes: a second doped region, a second gate structure, and a second interconnect structure electrically connected to both the second gate structure and the second doped region. The second doped region is located in the second semiconductor layer, and the second gate structure and the second interconnect structure are both located in the second insulating layer at positions corresponding to the second doped region.

[0019] According to another aspect of this disclosure, a memory is provided, comprising: a memory array and peripheral circuitry coupled to the memory array; wherein the peripheral circuitry comprises any of the semiconductor structures described above.

[0020] According to another aspect of this disclosure, a storage system is provided, comprising: one or more of the aforementioned memories; and

[0021] A memory controller, which is coupled to the memory and controls the memory.

[0022] According to another aspect of this disclosure, a method for manufacturing a semiconductor structure is provided, the method comprising:

[0023] A substrate structure is provided, the substrate structure including a first surface and a second surface disposed opposite to each other, wherein at least one first device is formed on the first surface;

[0024] Thinning the substrate structure from the second surface;

[0025] A second semiconductor layer is formed on the thinned second surface;

[0026] At least one second device is formed in the second semiconductor layer;

[0027] An isolation structure is formed between the first semiconductor and the second semiconductor.

[0028] In the above scheme, forming an isolation structure includes:

[0029] Before forming the second semiconductor layer, a sacrificial layer is formed on the thinned second surface; after forming the second semiconductor layer, the sacrificial layer is removed to form the isolation structure.

[0030] The formation of a second semiconductor layer on the thinned second surface includes:

[0031] The second semiconductor layer is formed on the sacrificial layer by an epitaxial process.

[0032] In the above scheme, forming an isolation structure includes:

[0033] An isolation material is filled at the location where the sacrificial layer is removed to form an isolation structure; the isolation material includes gaseous isolation material and / or solid isolation material.

[0034] In the above scheme, the etching selectivity ratio of the material of the sacrificial layer is different from that of the substrate structure and the second semiconductor layer.

[0035] In the above scheme, the substrate structure includes a stacked substrate and a first semiconductor layer, and the surface of the substrate away from the first semiconductor layer is the second surface of the substrate structure; the first semiconductor layer is formed by an epitaxial process;

[0036] The thinning of the substrate structure from the second surface includes:

[0037] The substrate is removed by an etching process, with the etching stopping at the surface of the first semiconductor layer.

[0038] In the above scheme, forming the first device includes: forming a first doped region in the first semiconductor layer; forming a first insulating layer on the surface of the first semiconductor layer away from the substrate; and forming a first gate structure corresponding to the first doped region and a first interconnect structure electrically connected to both the first gate structure and the first doped region in the first insulating layer.

[0039] In the above scheme, forming the second device includes: forming a second doped region in the second semiconductor layer; forming a second insulating layer on the surface of the second semiconductor layer away from the substrate structure; and forming a second gate structure corresponding to the second doped region and a second interconnect structure electrically connected to both the second gate structure and the second doped region in the second insulating layer.

[0040] In the above scheme, the method further includes: forming a connection structure on one side of the first device and the second device, penetrating the second semiconductor layer, the isolation structure and the substrate structure, wherein the connection structure is electrically connected to the first device.

[0041] In the above scheme, forming the connection structure includes:

[0042] A via is formed that penetrates the second insulating layer, the second semiconductor layer, the isolation structure, the first semiconductor layer, and extends into the first insulating layer;

[0043] The through-hole is filled with conductive material to form a connection structure, which is electrically connected to the first interconnect structure.

[0044] The method in the above scheme further includes:

[0045] Before thinning the substrate structure from the second surface, a carrier is formed on the surface of the first device away from the second surface.

[0046] This disclosure provides a semiconductor structure and its manufacturing method, a memory, and a memory system. In various embodiments of this disclosure, a first device and a second device are respectively located on opposite sides of a sacrificial layer. An isolation structure is formed by removing the sacrificial layer, separating the first device and the second device. In other words, an isolation structure is provided between the first device and the second device in this disclosure to prevent crosstalk between them. Compared to using semiconductor materials to isolate the first and second devices, the isolation structure offers superior isolation performance. Furthermore, a thinner isolation structure provides better isolation and favorable process conditions for the subsequent formation of interconnect structures, reducing the complexity of the interconnect structure's fabrication process. Attached Figure Description

[0047] Figure 1 This is a schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure;

[0048] Figure 2a This is a schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present disclosure;

[0049] Figure 2b This is a schematic diagram of an exemplary solid-state drive with a memory system according to an embodiment of the present disclosure;

[0050] Figure 3 A partial cross-sectional schematic diagram of the peripheral circuitry of a memory provided in an embodiment of this disclosure;

[0051] Figure 4 A schematic flowchart illustrating a method for manufacturing a semiconductor structure according to an embodiment of this disclosure;

[0052] Figures 5-16 This is a cross-sectional schematic diagram of the manufacturing process of a semiconductor structure provided in an embodiment of the present disclosure. Detailed Implementation

[0053] To make the technical solutions and advantages of the embodiments of this disclosure clearer, the technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary implementation methods of this disclosure are shown in the accompanying drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the implementation methods set forth herein. Rather, these implementation methods are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.

[0054] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0055] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0056] Furthermore, for ease of description, spatial relative terms such as “on,” “above,” “above,” “upper,” “above,” “upper,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0057] In embodiments of this disclosure, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include various semiconductor materials, such as silicon, silicon germanium, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0058] In embodiments of this disclosure, the term "layer" refers to a portion of material including a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers. For example, an interconnect layer may include one or more conductor and contact sublayers (where interconnect lines and / or via contacts are formed), and one or more dielectric sublayers.

[0059] In the embodiments of this disclosure, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0060] Figure 1 A block diagram of an exemplary system 100 having memory according to some aspects of this disclosure is shown. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 1 As shown, system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memories 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 108 may be configured to send data to or receive data from the memory 104.

[0061] According to some embodiments, memory controller 106 is coupled to memory 104 and host 108 and is configured to control memory 104. Memory controller 106 can manage data stored in memory 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, memory controller 106 is designed to operate in high duty cycle environments, such as SSDs or embedded multimedia cards (eMMCs), which are used as data storage in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays.

[0062] The memory controller 106 and one or more memories 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. Figure 2a In one example shown, the memory controller 106 and a single memory 104 can be integrated into the memory card 202. The memory card 202 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 can also include a connection between the memory card 202 and a host computer (e.g., Figure 1 The host 108) is coupled to the memory card connector 204. In such a... Figure 2b In another example shown, the memory controller 106 and multiple memories 104 can be integrated into the SSD 206. The SSD 206 may also include components for connecting the SSD 206 to a host computer (e.g., ...). Figure 1 The SSD connector 208 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0063] In some embodiments, memory 104 may include a three-dimensional NAND flash memory. Three-dimensional NAND flash memory stacks memory cells in a direction perpendicular to the substrate, enabling the formation of more memory cells in a smaller area. Compared to traditional two-dimensional memory, it has a larger storage capacity and is a major development direction in the current memory field.

[0064] With the development of 3D NAND flash memory technology, the number of layers in 3D NAND stacking is constantly increasing, and the storage section is continuously improving. Correspondingly, improvements in the peripheral circuitry to adapt to the storage section have placed higher demands on reducing the area of ​​the peripheral circuitry. How to reduce the area of ​​the peripheral circuitry has attracted widespread attention. The memory 104 may include a memory array and peripheral circuitry coupled to the memory array. The following explanation will continue using a 3D NAND flash memory array as an example. Figure 3 A partial cross-sectional schematic diagram of the peripheral circuitry of a memory provided in an embodiment of this disclosure is shown. For example... Figure 3As shown, the peripheral circuit can include low-voltage / ultra-low-voltage (LV / LLV) devices and high-voltage (HV) devices, classified according to their operating voltage. The low-voltage / ultra-low-voltage (LV / LLV) devices and high-voltage (HV) devices are placed on both sides of the wafer, and the embedded circuits are brought out through through-silicon via (TSV) technology. It can be understood that the different circuits of the peripheral circuit are split and redistributed, and the usable area of ​​the peripheral circuit is increased by using a three-dimensional integration method. Figure 3 The LV / LLV device 301 and the HV device 302 are respectively formed on the front and back sides of the substrate 300. Compared with the LV / LLV device 301 and the HV device 302 being disposed on one side of the substrate 300, the three-dimensional structure in which the LV / LLV device 302 and the HV device 301 are respectively disposed on the front and back sides of the substrate 300 is more conducive to reducing the area occupied by the peripheral circuit.

[0065] However, the method of forming LV / LLV devices 302 and HV devices 301 on both sides of substrate 300 has two problems. First, a sufficiently thick substrate must be reserved between LV / LLV devices 302 and HV devices 301 to prevent crosstalk between them. In other words, the distance between LV / LLV devices 302 and HV devices 301 along the substrate thickness direction is large. At this time, a sufficiently thick substrate makes it difficult to form the subsequent connection structure 303. That is to say, it is difficult to electrically lead HV devices 301 from one side of the substrate to the other side. Second, during the substrate thinning process, a barrier layer cannot be formed, resulting in poor uniformity of the thinned substrate, which makes it difficult to meet the depth of field (DOF) window of photolithography in subsequent processes such as TSV process.

[0066] Based on this, in order to solve one or more of the above problems, the present disclosure provides a method for fabricating a semiconductor structure, which can effectively reduce the mutual interference between the first device and the second device, and also reduce the difficulty of electrically leading out the first device. Figure 4 This is a schematic flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure. Figure 4 As shown, the method for fabricating a semiconductor structure provided in this embodiment includes the following steps:

[0067] S100: Provide a substrate structure, the substrate structure including a first surface and a second surface disposed opposite to each other, wherein at least one first device is formed on the first surface;

[0068] S200: Thinning the substrate structure from the second surface;

[0069] S300: A second semiconductor layer is formed on the thinned second surface;

[0070] S400: At least one second device is formed in the second semiconductor layer;

[0071] S500: An isolation structure is formed between the first semiconductor layer and the second semiconductor layer.

[0072] It should be understood that Figure 4 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 4 The steps shown can be adjusted in order according to actual needs. Figures 5 to 16 This disclosure provides a cross-sectional schematic diagram of the fabrication process of a semiconductor structure. It should be noted that... Figures 5 to 16 This is a schematic diagram illustrating the complete manufacturing process of a semiconductor structure. Unmarked parts in some of the accompanying drawings can be shared. The following section combines... Figure 4 , Figures 5 to 16 The method for fabricating the semiconductor structure provided in the embodiments of this disclosure will be described in detail.

[0073] In step S100, the first device is formed on the first surface of the substrate structure.

[0074] In some specific embodiments, the substrate structure may include a stacked substrate and a first semiconductor layer. The first semiconductor layer may be an epitaxial layer formed on the substrate by an epitaxial process. The surface of the first semiconductor layer away from the substrate is a first surface of the substrate structure, and the surface of the substrate away from the first semiconductor layer is a second surface of the substrate structure. The thickness of the first semiconductor layer relative to the substrate can be easily controlled by controlling the epitaxial process; for example, the thickness of the first semiconductor layer is less than the thickness of the substrate. The substrate may include a single-element semiconductor material substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.); the first semiconductor layer may include a single-element semiconductor material substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.). In some specific examples, both the substrate and the first semiconductor layer are made of silicon; preferably, the doping concentration of the silicon in the substrate is different from the doping concentration of the silicon in the first semiconductor layer. It is understood that having a different doping concentration of silicon in the substrate than in the first semiconductor layer can facilitate etching in subsequent processes.

[0075] In some embodiments, a first device is formed on a first surface of the substrate structure, including:

[0076] A first doped region is formed in the first semiconductor layer; a first insulating layer is formed on the surface of the first semiconductor layer away from the substrate; a first gate structure corresponding to the first doped region and a first interconnect structure electrically connected to the first gate structure and the first doped region are formed in the first insulating layer.

[0077] The following will combine Figures 5 to 6 The formation process of the first device is explained in detail.

[0078] like Figure 5 As shown, a first doped region 503 is formed in the first semiconductor layer 502 of the substrate structure 50.

[0079] In some specific embodiments, the methods for forming the first doped region 503 include, but are not limited to, doping processes and diffusion processes.

[0080] For example, a P-well or N-well is formed in the first semiconductor layer 502 by diffusion, and then the source and drain are formed in the P-well or N-well by ion implantation.

[0081] Next, as Figure 6 As shown, a first gate structure 504 is formed on the surface of the first semiconductor layer away from the substrate in the corresponding first doped region 503. Then, a first insulating layer 506 is formed to cover the first gate structure 504. Next, a first interconnect structure 505 connected to the first gate structure and the first doped region is formed in the first insulating layer 506.

[0082] In some embodiments, such as Figure 6 As shown, the method further includes forming an interconnect layer 505' in the first insulating layer 506, wherein all the first interconnect structures 505 are connected to the interconnect layer 505', and subsequently the interconnect structures are electrically connected to the first interconnect structure 505 of the first device through the interconnect layer 505'.

[0083] In some specific embodiments, the first gate structure 504 may include a gate oxide layer located on the surface of the first semiconductor layer away from the substrate in the first doped region 503, and a gate located on the gate oxide layer. The first gate structure 504 may also include protective sidewalls located on both sides of the gate.

[0084] The gate material includes metallic materials or semiconductor conductive materials, such as copper (Cu), cobalt (Co), tungsten (W), molybdenum (Mo), doped silicon, polycrystalline silicon, or any combination thereof.

[0085] In some specific embodiments, the method for forming the first insulating layer 506 includes one or more of photolithography, deposition such as chemical vapor deposition, physical vapor deposition, and etching.

[0086] In some specific embodiments, the methods for forming the first gate structure 504 include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), etc. In some specific embodiments, the material of the first insulating layer 506 includes silicon oxide (SiO2), silicon nitride, etc.

[0087] In some specific embodiments, the first insulating layer includes a first sub-insulating layer, a second sub-insulating layer, and a third sub-insulating layer; the method of forming the first interconnect structure 505 and the interconnect layer 505' includes: forming a first sub-insulating layer covering the first gate structure; forming a first groove penetrating the first sub-insulating layer and respectively connected to the first gate structure and the first doped region; filling the first groove with conductive material to form the first interconnect structure 505; forming a second sub-insulating layer on the first sub-insulating layer; forming an interconnect layer 505' connected to the first interconnect structure 505 in the second sub-insulating layer; and forming a third sub-insulating layer on the second sub-insulating layer.

[0088] In some specific embodiments, the material of the first interconnect structure 505 includes metals, such as copper (Cu), cobalt (Co), tungsten (W), molybdenum (Mo), etc.

[0089] In step S200, the main task is to thin the substrate structure.

[0090] In some embodiments, a carrier is formed on the surface of the first insulating layer away from the first semiconductor layer before the substrate structure is thinned from the second surface.

[0091] Next, in some embodiments, thinning the substrate structure from the second surface includes:

[0092] The substrate is removed by an etching process, with the etching stopping at the surface of the first semiconductor layer.

[0093] The following will combine Figures 7 to 9 The process of thinning the substrate structure is explained in detail. For example... Figure 7 As shown, a carrier 507 is formed on the surface of the first insulating layer away from the first semiconductor layer.

[0094] In some specific embodiments, the material of the carrier 507 includes silicon (Si), germanium (Ge), etc.

[0095] In some specific embodiments, the substrate silicon can be bonded to the surface of the first semiconductor layer by bonding.

[0096] Then, the semiconductor structure after forming the carrier 507 is inverted, with the carrier 507 positioned at the bottom, as shown below. Figure 8 As shown.

[0097] Understandably, when the substrate structure is subsequently thinned, the carrier 507 serves as a supporting plane to protect the first device formed, so as to prevent damage to the first device during the thinning of the substrate structure.

[0098] Next, as Figure 9 As shown, the semiconductor structure under the carrier 507 is thinned, and the substrate 501 is removed by an etching process. The etching stops at the surface of the first semiconductor layer 502.

[0099] In some specific embodiments, the etching processes used include dry etching and wet etching.

[0100] For example, the substrate 501 is removed by wet etching, and the etching stops at the surface of the first semiconductor layer 502.

[0101] It is understandable that when the doping concentration of the first semiconductor layer silicon 502 is different from that of the substrate silicon 501, their etching selectivity ratios are different. By utilizing wet etching and the difference in etching selectivity ratios between the two, the substrate 501 can be removed quickly. Compared with direct chemical mechanical polishing of thicker substrates, this method takes less time and avoids the problem of poor thickness uniformity of the processed substrate structure.

[0102] Furthermore, wet etching can easily deposit the first device on a very thin first semiconductor layer, which is more advantageous for controlling the thickness of the carrier on which the first device is located compared to the first device being formed directly in the substrate.

[0103] In step S300, the second semiconductor layer is mainly formed.

[0104] In some embodiments, a sacrificial layer is formed on the thinned second surface before the second semiconductor layer is formed.

[0105] like Figure 10 As shown, a sacrificial layer 508 is formed by sequentially stacking on the thinned second surface.

[0106] In some specific embodiments, the methods for forming the sacrificial layer 508 include, but are not limited to, chemical vapor deposition, physical vapor deposition, etc.

[0107] Next, in some embodiments, the second semiconductor layer is formed on the sacrificial layer. Methods for forming the second semiconductor layer 509 include, but are not limited to, epitaxial growth, chemical vapor deposition, and physical vapor deposition. Preferably, the second semiconductor layer 509 is formed on the sacrificial layer by an epitaxial process.

[0108] In some specific embodiments, the material of the second semiconductor layer 509 includes silicon (Si), germanium (Ge), etc.

[0109] In some embodiments, the material of the sacrificial layer has a different etching selectivity than both the materials of the substrate structure and the second semiconductor layer. Here, the material of the sacrificial layer 508 has a different etching selectivity than both the materials of the substrate structure 50 and the second semiconductor layer 509, thus facilitating the separate removal of the sacrificial layer 508 while the materials of the substrate structure 50 and the second semiconductor layer 509 remain. In some specific embodiments, the material of the sacrificial layer 508 includes, but is not limited to, silicon germanium (SiGe).

[0110] It should be noted that the sacrificial layer here, such as silicon germanium (SiGe), is a crystal with a fixed lattice constant and crystal orientation. Its lattice constant and crystal orientation are well matched with the subsequent second semiconductor, such as single crystal silicon. It can provide a growth surface and support surface for the epitaxial growth of the subsequent second semiconductor layer, and at the same time, it also increases the uniformity of the wafer thickness.

[0111] In step S400, the second device is mainly formed in the second semiconductor layer.

[0112] Here, the operating voltage of the second device is different from that of the first device.

[0113] In some embodiments, forming the second device includes: forming a second doped region in the second semiconductor layer; forming a second insulating layer on the surface of the second semiconductor layer away from the sacrificial layer; and forming a second gate structure corresponding to the second doped region and a second interconnect structure electrically connected to both the second gate structure and the second doped region in the second insulating layer.

[0114] The following will combine Figures 11 to 12 The formation process of the second device is explained in detail.

[0115] like Figure 11 As shown, a second doped region 510 is formed in the second semiconductor layer 509.

[0116] In some specific embodiments, the methods for forming the second doped region 510 include, but are not limited to, doping processes and diffusion processes.

[0117] For example, a P-well or N-well is formed in the second semiconductor layer 509 by diffusion, and then the source and drain are formed in the P-well or N-well by ion implantation.

[0118] Next, as Figure 12 As shown, a second gate structure 511 is formed on the surface of the corresponding second doped region 510 away from the sacrificial layer. Then, a second insulating layer 512 is formed to cover the second gate structure 511. Next, a second interconnect structure 513 connected to the second gate structure 511 and the second doped region 510 is formed in the second insulating layer 512.

[0119] In some embodiments, such as Figure 12 As shown, the method further includes forming an interconnect layer in the second insulating layer 512, and the second interconnect structures 513 are all connected to the interconnect layer, and are subsequently connected to electrical signals through the interconnect layer.

[0120] In some specific embodiments, the second gate structure 511 may include a gate oxide layer located on the surface of the second semiconductor layer away from the first semiconductor layer in the second doped region 510, and a gate located on the gate oxide layer. The second gate structure 511 may also include protective sidewalls located on both sides of the gate.

[0121] The gate material includes metallic materials or semiconductor conductive materials, such as copper (Cu), cobalt (Co), tungsten (W), molybdenum (Mo), doped silicon, polycrystalline silicon, or any combination thereof.

[0122] Here, the composition, materials, and formation method of the second insulating layer 512 are similar to those of the first insulating layer, and will not be described again here.

[0123] Here, the composition, materials and formation method of the second gate structure 511 are similar to those of the first gate structure, and will not be repeated here.

[0124] Here, the composition, materials, and formation method of the second interconnect structure are similar to those of the first interconnect structure, and will not be repeated here.

[0125] In some embodiments, the operating voltage of the first device is higher than that of the second device.

[0126] Understandably, the peripheral circuitry is divided and redistributed according to the operating voltage of the devices, and then placed on different planes and stacked in a three-dimensional manner. This facilitates the supply of voltage to devices on different planes. Because a storage structure will be formed near the second device, and subsequent processes will involve ion implantation and activation of the semiconductor, placing the first device with the higher operating voltage on the side away from the storage structure allows it to better withstand the high voltage applied during ion implantation and activation.

[0127] In step S500, the isolation structure is mainly formed.

[0128] In some embodiments, an isolation structure is formed, including:

[0129] An isolation material is filled at the location where the sacrificial layer is removed to form an isolation structure; the isolation material includes gaseous isolation material and / or solid isolation material.

[0130] like Figure 13 As shown, a groove 514 is formed, and the groove 514 penetrates at least through the sacrificial layer 508.

[0131] In some specific embodiments, the method for removing the sacrificial layer includes, but is not limited to, wet etching.

[0132] For example, a groove 514 is formed through the second insulating layer 512, the second semiconductor layer 509 and the sacrificial layer 508 by dry etching, and then the sacrificial layer 508 is removed by wet etching to form an isolation structure 515.

[0133] The etching selectivity of the sacrificial silicon germanium (SiGe) layer is different from that of the silicon first semiconductor layer 502 and the silicon second semiconductor layer 509. The sacrificial silicon germanium (SiGe) layer can be easily removed without damaging the silicon first semiconductor layer 502 and the silicon second semiconductor layer 509.

[0134] At this time, the isolation structure 515 formed by removing the sacrificial layer 508 is filled with air. In some specific embodiments, the gaseous isolation material filled in the isolation structure 515 includes, but is not limited to, inert gas and nitrogen.

[0135] In some specific embodiments, the isolation structure 515 formed by removing the sacrificial layer 508 may be filled with a solid isolation material, including but not limited to insulating materials such as silicon oxide and silicon nitride.

[0136] In some specific embodiments, the method for filling the isolation structure 515 with insulating material includes, but is not limited to, atomic layer deposition (ALD).

[0137] In some embodiments, the isolation structure includes a gas-based isolation material and a solid-based isolation material; wherein the isolation structure at the orthographic projection of the first device and the second device onto the plane of the isolation structure includes a gas-based isolation material.

[0138] For example, the isolation structure 515 formed after removing the sacrificial layer 508 can be filled with insulating silicon oxide using atomic layer deposition. For instance, only a portion around the formed groove 514 can be filled, while the remaining portion, such as the portion of the first and second devices projected onto the plane of the isolation structure, can be filled with air. Figure 14 As shown; or, at the location where the sacrificial layer 508 is removed, a layer of solid insulating material 515' is formed, and the remaining space is filled with gas insulating material, such as... Figure 15 As shown.

[0139] For example, such as Figure 13 As shown, the entire isolation structure is filled with gaseous material; as Figure 16 As shown, the entire isolation structure is filled with solid material.

[0140] It is understandable that the conductivity of inert gases and insulating materials is lower than that of silicon, a semiconductor material, which can effectively prevent crosstalk between the first and second devices during operation. By setting up an isolation structure, the distance between the first and second devices can be reduced. The reduction in distance reduces the process difficulty for through-silicon vias in subsequent process steps, and facilitates optical alignment and etching.

[0141] Meanwhile, the semiconductor structure where the first device and the second device are located is more uniform in thickness through the deposition of the sacrificial layer and the second semiconductor layer. This further reduces the difficulty of the through-silicon via in subsequent process steps, and the uniformity of the semiconductor structure thickness meets the depth of field (DOF) window of photolithography.

[0142] Furthermore, the isolation material filled between the isolation structures 515 can be used as a support to provide a support platform for the second device, thereby maintaining the stability of the entire semiconductor structure.

[0143] Next, the main focus is on forming a connection structure, through which the electrical connection of the first device is achieved.

[0144] In some embodiments, a connection structure is formed on one side of the first device and the second device, penetrating the second semiconductor layer, the isolation structure, and the substrate structure, and the connection structure is electrically connected to the first device.

[0145] Specifically, a via is formed that penetrates the second insulating layer, the second semiconductor layer, the isolation structure, the first semiconductor layer, and extends into the first insulating layer;

[0146] The through-hole is filled with conductive material to form a connection structure, which is electrically connected to the first interconnect structure.

[0147] The via formed here, penetrating the second insulating layer, the second semiconductor layer, the isolation structure, and the first semiconductor layer, and extending into the first insulating layer, can be a through-silicon via (TSV). The isolation structure reduces the difficulty of implementing the TSV process.

[0148] In some specific embodiments, the through holes required to form the connection structure can be formed simultaneously with the removal of the grooves formed during the removal of the sacrificial process.

[0149] In some specific embodiments, the methods for forming the vias required for the connection structure include, but are not limited to, dry etching and wet etching.

[0150] For example, a via is formed through the second semiconductor layer, the isolation structure, and the substrate structure by dry etching. Here, the substrate structure refers to the first semiconductor layer after the substrate is removed. The via extends into the first insulating layer where the first device is located. Then, the sacrificial layer is removed by wet etching through the via.

[0151] Next, as Figure 16 As shown, conductive material is filled into the through hole 515 to form a connection structure 516, which is electrically connected to the first interconnect structure 505.

[0152] In some specific embodiments, the methods for forming the connection structure include, but are not limited to, chemical vapor deposition, physical vapor deposition, atomic layer deposition, etc.

[0153] In some specific embodiments, the material of the connection structure 516 includes metals, such as copper (Cu), cobalt (Co), tungsten (W), molybdenum (Mo), etc.

[0154] It is understandable that the circuit formed by the embedded first device is brought out through the connection structure to realize the electrical connection of the first device.

[0155] In some embodiments, a memory array is formed on the surface of the second insulating layer away from the first device, wherein, in some embodiments, the memory includes a three-dimensional NAND type memory.

[0156] It is understood that the peripheral circuit, composed of the first and second devices, is connected to the storage structure and is used to control the storage structure to realize data writing, reading, refreshing, etc.

[0157] According to another aspect of this disclosure, embodiments of this disclosure further provide a semiconductor structure, including:

[0158] A first semiconductor layer, an isolation structure, and a second semiconductor layer are stacked sequentially.

[0159] At least one first device, wherein a portion of the structure of the first device is located in the first semiconductor layer;

[0160] At least one second device, wherein a portion of the structure of the second device is located in the second semiconductor layer.

[0161] In the above scheme, the semiconductor structure further includes:

[0162] A connection structure is located on one side of the first device and the second device and extends through the second semiconductor layer, the isolation structure and the first semiconductor layer, and the connection structure is electrically connected to the first device.

[0163] In the above scheme, the operating voltage of the first device is higher than that of the second device.

[0164] In the above scheme, the isolation structure includes gas isolation materials and / or solid isolation materials.

[0165] In the above scheme, the isolation structure includes gas isolation material and solid isolation material; wherein, the isolation structure at the orthographic projection of the first device and the second device onto the plane where the isolation structure is located includes gas isolation material.

[0166] In the above scheme, the semiconductor structure further includes:

[0167] A first insulating layer covers the surface of the first semiconductor layer away from the isolation structure;

[0168] The first device includes: a first doped region, a first gate structure, and a first interconnect structure electrically connected to both the first gate structure and the first doped region. The first doped region is located in the first semiconductor layer, and the first gate structure and the first interconnect structure are both located in the first insulating layer at positions corresponding to the first doped region.

[0169] In the above scheme, the semiconductor structure further includes:

[0170] A second insulating layer covers the surface of the second semiconductor layer away from the isolation structure;

[0171] The second device includes: a second doped region, a second gate structure, and a second interconnect structure electrically connected to both the second gate structure and the second doped region. The second doped region is located in the second semiconductor layer, and the second gate structure and the second interconnect structure are both located in the second insulating layer at positions corresponding to the second doped region.

[0172] According to another aspect of this disclosure, embodiments of this disclosure also provide a memory, including:

[0173] A memory array and peripheral circuitry coupled to the memory array; wherein the peripheral circuitry comprises any of the aforementioned semiconductor structures.

[0174] In some embodiments, the memory includes a three-dimensional NAND-type memory.

[0175] This disclosure also provides a memory system, the memory system comprising:

[0176] One or more memories as described in any of the above embodiments; and

[0177] A memory controller, which is coupled to the memory and controls the memory.

[0178] Here, the specific structure and composition of the memory system can be referred to the foregoing. Figure 1 , Figure 2a , Figure 2b The relevant structure and composition of the memory system are described below. For the sake of brevity, they will not be elaborated here.

[0179] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative; for example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. Furthermore, the various components shown or discussed may be coupled or directly coupled to each other.

[0180] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0181] This disclosure provides specific embodiments, but its scope of protection is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed herein should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: A first semiconductor layer, an isolation structure, and a second semiconductor layer are stacked sequentially. At least one first device, wherein a portion of the structure of the first device is located in the first semiconductor layer; The first device includes a first doped region, a first gate structure, and a first interconnect structure electrically connected to both the first gate structure and the first doped region, wherein the first doped region is located in the first semiconductor layer; At least one second device, wherein a portion of the structure of the second device is located in the second semiconductor layer.

2. The semiconductor structure according to claim 1, characterized in that, The operating voltage of the first device is higher than that of the second device.

3. The semiconductor structure according to claim 2, characterized in that, The semiconductor structure also includes: A connection structure is located on one side of the first device and the second device and extends through the second semiconductor layer, the isolation structure and the first semiconductor layer, and the connection structure is electrically connected to the first device.

4. The semiconductor structure according to claim 1, characterized in that, The isolation structure includes gas-insulating materials and / or solid-insulating materials.

5. The semiconductor structure according to claim 4, characterized in that, The isolation structure includes a gas-based isolation material and a solid-based isolation material; wherein, the isolation structure at the orthographic projection of the first device and the second device onto the plane of the isolation structure includes a gas-based isolation material.

6. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure also includes: A first insulating layer covers the surface of the first semiconductor layer away from the isolation structure; The first gate structure and the first interconnect structure are both located in the first insulating layer at positions corresponding to the first doped region.

7. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure also includes: A second insulating layer covers the surface of the second semiconductor layer away from the isolation structure; The second device includes: a second doped region, a second gate structure, and a second interconnect structure electrically connected to both the second gate structure and the second doped region. The second doped region is located in the second semiconductor layer, and the second gate structure and the second interconnect structure are both located in the second insulating layer at positions corresponding to the second doped region.

8. A memory, characterized in that, include: A memory array and peripheral circuitry coupled to the memory array; wherein the peripheral circuitry comprises a semiconductor structure as described in any one of claims 1 to 7.

9. A memory system, characterized in that, include: One or more memories as described in claim 8; as well as A memory controller, which is coupled to the memory and controls the memory.

10. A method for manufacturing a semiconductor structure, characterized in that, include: A substrate structure is provided, the substrate structure including a first surface and a second surface disposed opposite to each other, wherein at least one first device is formed on the first surface; Thinning the substrate structure from the second surface; A second semiconductor layer is formed on the thinned second surface; At least one second device is formed in the second semiconductor layer; An isolation structure is formed between the substrate structure and the second semiconductor layer.

11. The method for manufacturing a semiconductor structure according to claim 10, characterized in that, Forming the isolation structure includes: Before forming the second semiconductor layer, a sacrificial layer is formed on the thinned second surface; after forming the second semiconductor layer, the sacrificial layer is removed to form the isolation structure. The formation of a second semiconductor layer on the thinned second surface includes: The second semiconductor layer is formed on the sacrificial layer by an epitaxial process.

12. The method for manufacturing a semiconductor structure according to claim 11, characterized in that, The formation of the isolation structure includes: An isolation material is filled at the location where the sacrificial layer is removed to form an isolation structure; the isolation material includes gaseous isolation material and / or solid isolation material.

13. The method for manufacturing a semiconductor structure according to claim 11, characterized in that, The material of the sacrificial layer has a different etching selectivity than the materials of the substrate structure and the second semiconductor layer.

14. The method for manufacturing a semiconductor structure according to claim 10, characterized in that, The substrate structure includes a stacked substrate and a first semiconductor layer, wherein the surface of the substrate away from the first semiconductor layer is the second surface of the substrate structure. The first semiconductor layer is formed by an epitaxial process; The thinning of the substrate structure from the second surface includes: The substrate is removed by an etching process, with the etching stopping at the surface of the first semiconductor layer.

15. The method for manufacturing a semiconductor structure according to claim 14, characterized in that, Forming the first device includes: A first doped region is formed in the first semiconductor layer; a first insulating layer is formed on the surface of the first semiconductor layer away from the substrate; a first gate structure corresponding to the first doped region and a first interconnect structure electrically connected to the first gate structure and the first doped region are formed in the first insulating layer.

16. The method for manufacturing a semiconductor structure according to claim 15, characterized in that, Forming the second device includes: A second doped region is formed in the second semiconductor layer; a second insulating layer is formed on the surface of the second semiconductor layer away from the substrate structure; a second gate structure corresponding to the second doped region and a second interconnect structure electrically connected to the second gate structure and the second doped region are formed in the first insulating layer.

17. The method for manufacturing a semiconductor structure according to claim 10, characterized in that, The method further includes: On one side of the first device and the second device, a connection structure is formed that penetrates the second semiconductor layer, the isolation structure, and the substrate structure, and the connection structure is electrically connected to the first device.

18. The method for manufacturing a semiconductor structure according to claim 16, characterized in that, A connection structure is formed, through which the electrical connection of the first device is realized; The connection structure includes: A via is formed that penetrates the second insulating layer, the second semiconductor layer, the isolation structure, the first semiconductor layer, and extends into the first insulating layer; The through-hole is filled with conductive material to form a connection structure, which is electrically connected to the first interconnect structure.

19. The method for manufacturing a semiconductor structure according to claim 10, characterized in that, The method further includes: Before thinning the substrate structure from the second surface, a carrier is formed on the surface of the first device away from the second surface.

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