Mcu chip and switching method of working mode thereof

Abstract

The application discloses an MCU chip and a switching method of working modes of the MCU chip, which comprises a first LDO circuit, a second LDO circuit and a switching circuit. The first LDO circuit and the second LDO circuit supply power to the MCU chip, and the switching circuit switches between the first LDO circuit and the second LDO circuit, so that the MCU chip works in different modes. The switching circuit comprises a copy controllable circuit and a copy circuit. According to the MCU chip, the copy controllable circuit copies the output current of the first LDO circuit to output a first copy current, the copy circuit copies the first copy current to output a second copy current to the second LDO circuit, the second LDO circuit establishes an internal loop based on the second copy current, and the current flow between the switching circuit and the first LDO circuit and the second LDO circuit is cut off, so that the output voltage drop caused by the transient change of the load when the first LDO circuit and the second LDO circuit are switched is avoided.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and in particular to an MCU chip and a method for switching its operating modes. Background Technology

[0002] For large, highly integrated MCU chips, the need for low power consumption is becoming increasingly important. To address this need, the chip often needs to enter a low-power mode when no computation is required, in which case only a power supply sufficient to maintain register data is needed. During normal operation, the chip is powered by an LDO (linear regulator) circuit with relatively high quiescent current and good transient response; however, when entering low-power mode, the voltage is maintained by a low-power LDO circuit, which typically has a quiescent current of only nA to about 1uA and has poor transient response.

[0003] Large, highly integrated MCU chips can have significant leakage current at high temperatures. If the power supply is switched directly when switching between low-power and low-power modes, the output voltage of the low-power LDO circuit may be pulled down by the load momentarily. In severe cases, this can lead to incorrect transmission of digital logic within the MCU chip. Furthermore, due to the poor transient response of low-power capacitorless LDO circuits, this voltage drop may take a long time to recover.

[0004] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide an MCU chip and a method for switching its operating modes, which can achieve a smooth switching between an LDO circuit with high static current and good transient response capability and a low-power LDO circuit when switching operating modes.

[0006] To achieve the above objectives, embodiments of the present invention provide an MCU chip, including: a first LDO circuit, a second LDO circuit, and a switching circuit. The first LDO circuit and the second LDO circuit are used to supply power to the internal components of the MCU chip, and the switching circuit is used to switch between the first LDO circuit and the second LDO circuit so that the MCU chip can operate in different modes.

[0007] The switching circuit includes: a copy controllable circuit and a copy circuit.

[0008] The copy controllable circuit is used to copy the output current of the first LDO circuit and output the first copied current.

[0009] The replication circuit is connected to the replication controllable circuit and is used to replicate the first replication current and output the second replication current to the second LDO circuit. The second LDO circuit establishes an internal loop based on the second replication current.

[0010] The controllable replication circuit is used to cut off the current flow between the switching circuit and the first and second LDO circuits after the second LDO circuit establishes an internal loop, and the operating mode of the MCU chip is switched from the mode powered by the first LDO circuit to the mode powered by the second LDO circuit.

[0011] In one or more embodiments of the present invention, the controllable replication circuit includes a switching unit and a replication current unit. The switching unit is connected to a first LDO circuit, and the replication current unit is connected to the switching unit and the replication circuit. When both the switching unit and the replication current unit are turned on, the replication current unit replicates the output current of the first LDO circuit and outputs a first replication current.

[0012] In one or more embodiments of the present invention, the switching unit includes a first switch, a first terminal of the first switch being connected to the gate of the output power transistor of the first LDO circuit, and a second terminal of the first switch being connected to a replica current unit.

[0013] In one or more embodiments of the present invention, the replication current unit includes a second switch and a second MOS transistor; the gate of the second MOS transistor is connected to the second terminal of the second switch and the switching unit, the source of the second MOS transistor is connected to the first terminal of the second switch and the power supply voltage, and the drain of the second MOS transistor is connected to the replication circuit.

[0014] In one or more embodiments of the present invention, the MCU chip further includes a delay control circuit, which is used to delay turning off the output power transistor of the first LDO circuit.

[0015] In one or more embodiments of the present invention, the delay control circuit includes a delay unit, an inverter, and an eighth MOS transistor. The delay unit is connected to the input terminal of the inverter, the output terminal of the inverter is connected to the gate of the eighth MOS transistor, the drain of the eighth MOS transistor is connected to the gate of the output power transistor of the first LDO circuit, and the source of the eighth MOS transistor is connected to the power supply voltage.

[0016] In one or more embodiments of the present invention, the replication circuit includes a third MOS transistor and a fourth MOS transistor. The gate and drain of the third MOS transistor are connected and connected to the replication controllable circuit. The source of the third MOS transistor and the source of the fourth MOS transistor are connected to ground voltage. The drain of the fourth MOS transistor is connected to the output terminal of the second LDO circuit.

[0017] In one or more embodiments of the present invention, the MCU chip further includes a selection circuit, which is used to connect the output terminal of the second LDO circuit and the load inside the MCU chip after the current between the second LDO circuit and the switching circuit is cut off.

[0018] In one or more embodiments of the present invention, the MCU chip further includes a current comparison circuit, which is used to compare the output current of the first LDO circuit with a reference current and control the selection circuit according to the comparison result.

[0019] In one or more embodiments of the present invention, the current comparison circuit includes a fifth MOSFET, a sixth MOSFET, and a seventh MOSFET. The gate of the fifth MOSFET is connected to the gate of the output power transistor of the first LDO circuit. The source of the fifth MOSFET is connected to the power supply voltage. The drain of the fifth MOSFET is connected to the drain of the sixth MOSFET and is connected to a selection circuit. The gate of the sixth MOSFET is connected to the gate of the seventh MOSFET. The gate and drain of the seventh MOSFET are connected. The source of the seventh MOSFET and the source of the sixth MOSFET are connected to ground voltage. The drain of the seventh MOSFET is used to receive a reference current.

[0020] This invention also discloses a method for switching the operating mode of an MCU chip, comprising:

[0021] Switching from normal operating mode to low power mode:

[0022] Power is supplied to the MCU chip through the first LDO circuit;

[0023] The copy controllable circuit is activated to receive the output current of the first LDO circuit and copy the output of the first copy current.

[0024] The first replication current is replicated by the replication circuit, and the second replication current is output to the second LDO circuit.

[0025] The second LDO circuit establishes an internal loop based on the second replicated current. After the output current of the second LDO circuit completes the replication of the output current of the first LDO circuit, the current flow between the first LDO circuit and the second LDO circuit is cut off, and the second LDO circuit supplies power to the MCU chip.

[0026] In one or more embodiments of the present invention, the method for switching the working mode further includes:

[0027] Switching from low-power mode to normal operating mode:

[0028] Power is supplied to the MCU chip through the second LDO circuit;

[0029] The output current of the first LDO circuit is compared with the reference current by a current comparison circuit. Based on the comparison result, the selection circuit is controlled to disconnect the connection between the second LDO circuit and the load, and the first LDO circuit supplies power to the MCU chip.

[0030] Compared with the prior art, according to the MCU chip and its operating mode switching method according to the embodiments of the present invention, the MCU chip copies the output current of the first LDO circuit through a copy controllable circuit to output a first copied current, and copies the first copied current through a copy circuit to output a second copied current to the second LDO circuit. The second LDO circuit establishes an internal loop based on the second copied current. After the copy controllable circuit establishes the internal loop in the second LDO circuit, the current flow between the switching circuit and the first LDO circuit and the second LDO circuit is cut off. The operating mode of the MCU chip switches from the mode powered by the first LDO circuit to the mode powered by the second LDO circuit, thereby avoiding the output voltage drop caused by the transient change of the load when switching between the first LDO circuit and the second LDO circuit. It ensures that the MCU chip has extremely low static power consumption in low power mode, without the need to increase the current of the second LDO circuit to improve its transient response capability. During the LDO circuit switching process, the real-time load is sensed, and the establishment of the second LDO circuit loop is helped by the dummy load, which solves the problem of poor transient response of the low power capacitorless second LDO circuit. At the same time, the switching method is simple to implement, and there is no power consumption when not switching. Attached Figure Description

[0031] Figure 1 This is a system schematic diagram of an MCU chip according to Embodiment 1 of the present invention.

[0032] Figure 2 This is a signal timing diagram for switching the operating mode of an MCU chip according to Embodiment 1 of the present invention.

[0033] Figure 3 This is a partial circuit schematic diagram of an MCU chip according to Embodiment 1 of the present invention.

[0034] Figure 4 This is a timing diagram of the signal entering low-power mode according to Embodiment 1 of the present invention.

[0035] Figure 5 This is a circuit diagram of a current comparator according to Embodiment 1 of the present invention.

[0036] Figure 6 This is a timing diagram of the signal exiting low-power mode according to Embodiment 1 of the present invention.

[0037] Figure 7 This is a flowchart of a method for switching the operating mode of an MCU chip according to Embodiment 1 of the present invention. Detailed Implementation

[0038] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings, but it should be understood that the scope of protection of the present invention is not limited to the specific embodiments.

[0039] Unless otherwise expressly stated, throughout the specification and claims, the term "comprising" or its variations such as "including" or "comprises" shall be understood to include the stated elements or components without excluding other elements or other components.

[0040] like Figure 1 As shown, an MCU chip includes: a first LDO circuit LDO_CORE, a second LDO circuit LDO_LP, a switching circuit 10, a current comparison circuit 20, a selection circuit Power Selector, and a load inside the MCU chip.

[0041] The first LDO circuit, LDO_CORE, is used to maintain the normal operation of the MCU chip. The second LDO circuit, LDO_LP, is used to maintain the internal logic of the MCU chip when it enters low-power mode. Its quiescent current for biasing is generally low, and its output voltage is designed to be slightly lower than the output voltage of the first LDO circuit, LDO_CORE, thereby reducing leakage current of the MCU chip in low-power mode. The load refers to other circuits inside the MCU chip, including digital loads.

[0042] In this embodiment, the output terminal Output1 of the first LDO circuit LDO_CORE is connected to the first selection input terminal of the selection circuit PowerSelector, the output terminal Output2 of the second LDO circuit LDO_LP is connected to the switching device S of the selection circuit PowerSelector, the switching device S is connected to the second selection input terminal of the selection circuit PowerSelector, and the output terminal Output of the selection circuit PowerSelector is connected to the load Load.

[0043] like Figure 2 and Figure 1As shown, the first LDO circuit LDO_CORE is controlled to turn on and off by the low-power mode enable signal Lpmo (Low power mode on). In normal operation, the low-power mode enable signal Lpmo is low, and the first LDO circuit LDO_CORE is turned on to supply power to the load Load. In low-power mode, the low-power mode enable signal Lpmo is high, and the first LDO circuit LDO_CORE is turned off. The output voltage of the first LDO circuit LDO_CORE drops. When the output voltage of the second LDO circuit LDO_LP is higher than the output voltage of the first LDO circuit LDO_CORE, the selection circuit PowerSelector closes the switching device S (i.e., the higher voltage selects the higher voltage), and the second LDO circuit LDO_LP supplies power to the load Load. At this time, the current Iq of the MCU chip's power supply section is also low, resulting in lower overall power consumption of the MCU chip.

[0044] like Figure 3 As shown, the first LDO circuit LDO_CORE includes amplifier A1, output power transistor M1, first resistor R1, and second resistor R2. The first input terminal of amplifier A1 is connected to the reference voltage Vref, the output terminal of amplifier A1 is connected to the gate of output power transistor M1, the source of output power transistor M1 is connected to the power supply voltage VDD, the first end of the first resistor R1 is connected to the drain of output power transistor M1, the second end of the first resistor R1 is connected to the first end of the second resistor R2 and the second input terminal of amplifier A1, and the second end of the second resistor R2 is connected to ground voltage VSS. The drain of output power transistor M1 is the output terminal Output1 of the first LDO circuit LDO_CORE. In this embodiment, the first LDO circuit LDO_CORE is a simplified circuit diagram. The structure of the second LDO circuit LDO_LP can be the same as that of the first LDO circuit LDO_CORE. In other embodiments, the first LDO circuit LDO_CORE and the second LDO circuit LDO_LP can also be LDO circuits with other structures.

[0045] like Figure 3 As shown, the MCU chip also includes a delay control circuit 30, which is used to receive a low-power mode enable signal Lpmo to delay and turn off the output power transistor M1 of the first LDO circuit LDO_CORE.

[0046] Specifically, the delay control circuit 30 includes a delay unit, an inverter INV, and an eighth MOS transistor MP.

[0047] The first terminal of the delay unit receives the low-power mode enable signal Lpmo, and the second terminal is connected to the input terminal of the inverter INV. The output terminal of the inverter INV is connected to the gate of the eighth MOSFET MP, the source of the eighth MOSFET MP is connected to the source of the output power transistor M1, and the drain of the eighth MOSFET MP is connected to the gate of the output power transistor M1. The low-power mode enable signal Lpmo is output as a control signal VGM to control the eighth MOSFET MP via the delay unit and the inverter INV.

[0048] like Figure 3 As shown, the switching circuit 10 includes a copy controllable circuit 11 and a copy circuit 12 connected together.

[0049] When the MCU chip switches from normal operating mode to low-power mode, the copy controllable circuit 11 copies the output current of the first LDO circuit LDO_CORE and outputs the first copied current; the copy circuit 12 copies the first copied current and outputs the second copied current to the output terminal Output2 of the second LDO circuit LDO_LP. The second LDO circuit LDO_LP establishes an internal loop based on the second copied current (establishing an internal loop means that all nodes inside the second LDO circuit LDO_LP are stable in a state that allows the second LDO circuit LDO_LP to output the final desired voltage and provide the final desired current). After the second LDO circuit LDO_LP establishes an internal loop based on the second copied current, the copy controllable circuit 11 cuts off the current flow between the switching circuit 10 and the first LDO circuit LDO_CORE and the second LDO circuit LDO_LP. At this time, after the current between the second LDO circuit LDO_LP and the first LDO circuit LDO_CORE is cut off, it supplies power to the load Load, and the operating mode of the MCU chip also switches from the mode powered by the first LDO circuit to the mode powered by the second LDO circuit.

[0050] In this embodiment, the controllable replication circuit 11 includes a switching unit 111 and a replication current unit 112. The switching unit 111 is connected to the first LDO circuit LDO_CORE, and the replication current unit 112 is connected to both the switching unit 111 and the replication circuit 12. When both the switching unit 111 and the replication current unit 112 are turned on, the replication current unit 112 replicates the output current of the first LDO circuit LDO_CORE and outputs a first replication current.

[0051] Specifically, the switching unit 111 includes a first switch S1. The first terminal of the first switch S1 is connected to the gate of the output power transistor M1 of the first LDO circuit LDO_CORE, and the second terminal of the first switch S1 is connected to the replication current unit 112.

[0052] The replication current unit 112 includes a second switch S2 and a second MOSFET M2. The gate of the second MOSFET M2 is connected to the second terminal of the second switch S2 and the second terminal of the first switch S1 of the switching unit 111. The source of the second MOSFET M2 is connected to the first terminal of the second switch S2 and the power supply voltage VDD. The drain of the second MOSFET M2 is connected to the replication circuit 12.

[0053] The replication circuit 12 includes a third MOSFET M3 and a fourth MOSFET M4. The gate and drain of the third MOSFET M3 are connected and are also connected to the drain of the second MOSFET M2 in the replication controllable circuit 11. The sources of the third MOSFET M3 and the fourth MOSFET M4 are connected to ground voltage VSS, and the drain of the fourth MOSFET M4 is connected to the output terminal Output2 of the second LDO circuit LDO_LP.

[0054] like Figure 4 and Figure 3 As shown, when the low-power mode enable signal Lpmo is high, the second switch S2 switches from closed to open. Due to the delay effect of the delay unit, the control signal VGM does not immediately flip to a low level. During this delay period, the control signal VGM remains high, the eighth MOSFET MP remains off, the output power transistor M1 is normally on, and the first LDO circuit LDO_CORE is in normal output mode.

[0055] During the delay period, the first switch S1 is closed (i.e., switch unit 111 is in the on state). The output current of the first LDO circuit LDO_CORE is replicated to the output terminal Output2 of the second LDO circuit LDO_LP through the second MOSFET M2, the third MOSFET M3, and the fourth MOSFET M4 to establish the internal loop of the second LDO circuit LDO_LP (the control signal G_LP at the gate of the output power transistor of the second LDO circuit LDO_LP gradually decreases until the output power transistor of the second LDO circuit LDO_LP is fully turned on). When switch S2 is opened, the second MOSFET M2 is turned on, which means that the current replication unit 112 is in the on state.

[0056] After the delay ends, the control signal VGM flips to a low level under the action of the inverter INV. At this time, the eighth MOSFET MP is in the on state, and the output power transistor M1 is in the off state, causing the first LDO circuit LDO_CORE to turn off. At the same time as the control signal VGM flips to a low level, the first switch S1 is opened, which cuts off the current flow between the replication current unit 112 and the first LDO circuit LDO_CORE. The current on the second MOSFET M2, the third MOSFET M3, and the fourth MOSFET M4 will continue for a period of time. When the current on the second MOSFET M2, the third MOSFET M3, and the fourth MOSFET M4 is less than the current output at the output terminal Output2 of the second LDO circuit LDO_LP, the selection circuit Power Selector closes the switch S, so that the second LDO circuit LDO_LP supplies power to the load Load.

[0057] While the Power Selector circuit closes the switching device S, it also closes the second switch S2 to turn off the second MOS transistor M2 (i.e., the replication current unit 112 is in a non-on state), thereby cutting off the current flow between the replication circuit 12 and the second LDO circuit LDO_LP (i.e., cutting off the connection between the output terminal Output2 of the second LDO circuit LDO_LP and the dummy load, which is equivalent to the load formed by the switching circuit 10).

[0058] During this switching process, because the second LDO circuit LDO_LP has established an internal loop in advance through the output current of the first LDO circuit LDO_CORE, the output current of the second LDO circuit LDO_LP will not fluctuate due to the switching of the selection circuit PowerSelector. That is, the output current of the second LDO circuit LDO_LP does not experience a large transient change due to the load switching. This prevents the output voltage of the second LDO circuit LDO_LP from being instantly pulled down by the switched load. It also prevents the selection circuit PowerSelector from having a delay in responding to the control switching device S, which could lead to the selection circuit PowerSelector not closing the switching device S after the first LDO circuit LDO_CORE is turned off. As a result, due to the large load Load, the output voltage of the selection circuit PowerSelector is pulled down to a lower value by the load Load, thus avoiding the risk of digital logic errors in the MCU chip.

[0059] like Figure 1 As shown, the current comparison circuit 20 is used to compare the output current of the first LDO circuit LDO_CORE with the reference current and control the selection circuit Power Selector based on the comparison result.

[0060] like Figure 5 As shown, the current comparison circuit 20 includes a fifth MOSFET M5, a sixth MOSFET M6, and a seventh MOSFET M7.

[0061] The gate of the fifth MOSFET M5 is connected to the gate of the output power transistor M1 of the first LDO circuit LDO_CORE. The source of the fifth MOSFET M5 is connected to the power supply voltage VDD. The drain of the fifth MOSFET M5 is connected to the drain of the sixth MOSFET M6 to form node A, which is connected to the power selector circuit. The gate of the sixth MOSFET M6 is connected to the gate of the seventh MOSFET M7. The gate and drain of the seventh MOSFET M7 are connected. The source of the seventh MOSFET M7 and the source of the sixth MOSFET M6 are connected to the ground voltage VSS. The drain of the seventh MOSFET M7 is used to receive the reference current Ibias.

[0062] like Figure 5 and Figure 6 As shown, when exiting low-power mode, the first LDO circuit LDO_CORE is turned on (i.e., the low-power mode enable signal Lpmo toggles to a low level, the control signal VGM toggles to a high level, the eighth MOSFET MP is in the off state, and the gate voltage VM of the output power transistor M1 of the first LDO circuit gradually decreases). The current I1 on the output power transistor M1 gradually increases. The fifth MOSFET M5 replicates the current I1 on the output power transistor M1, and the current mirror composed of the sixth MOSFET M6 and the seventh MOSFET M7 replicates the reference current Ibias. The current I1 on the output power transistor M1 is compared with the reference current Ibias. If the current I1 on the output power transistor M1 is greater than the reference current Ibias, the Power Selector circuit disconnects the switching device S, and the MCU chip is powered by the first LDO circuit LDO_CORE and operates normally. The current comparison circuit 20 can be turned off after the switching device S is disconnected to reduce static power consumption.

[0063] like Figure 7 As shown, this embodiment also discloses a method for switching the operating mode of an MCU chip, including:

[0064] Switching from normal operating mode to low power mode:

[0065] Power is supplied to the MCU chip through the first LDO circuit;

[0066] Enable the copy controllable circuit 11 to receive the output current of the first LDO circuit LDO_CORE and copy the output of the first copy current.

[0067] The first replication current is replicated by the replication circuit 12, and the second replication current is output to the output terminal Output2 of the second LDO circuit LDO_LP.

[0068] The second LDO circuit LDO_LP establishes an internal loop based on the second replicated current. After the output current of the second LDO circuit LDO_LP completes the replication of the output current of the first LDO circuit LDO_CORE, the current flow between the first LDO circuit LDO_CORE and the second LDO circuit LDO_LP is cut off, and the second LDO circuit LDO_LP supplies power to the MCU chip.

[0069] In this embodiment, when the current flow between the replication circuit 12 and the second LDO circuit LDO_LP is cut off, the power selector selects to connect the output terminal of the second LDO circuit LDO_LP to the load Load inside the MCU chip, thereby supplying power to the load Load.

[0070] Switching from low-power mode to normal operating mode:

[0071] Power is supplied to the MCU chip through the second LDO circuit;

[0072] The first LDO circuit LDO_CORE is turned on. The current comparison circuit 20 compares the output current of the first LDO circuit LDO_CORE with the reference current Ibias. Based on the comparison result, the power selector circuit disconnects the connection between the second LDO circuit LDO_LP and the load Load. That is, when the output current of the first LDO circuit LDO_CORE is greater than the reference current Ibias, the power selector circuit disconnects the switching device S to disconnect the connection between the second LDO circuit LDO_LP and the load Load, and the first LDO circuit LDO_CORE supplies power to the load Load inside the MCU chip.

[0073] The foregoing description of specific exemplary embodiments of the invention is for illustrative and explanatory purposes. These descriptions are not intended to limit the invention to the precise forms disclosed, and it will be apparent that many changes and variations can be made in accordance with the foregoing teachings. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application, thereby enabling those skilled in the art to implement and utilize various different exemplary embodiments of the invention, as well as various different choices and variations. The scope of the invention is intended to be defined by the claims and their equivalents.

Claims

1. An MCU chip, characterized in that, include: The system comprises a first LDO circuit, a second LDO circuit, and a switching circuit. The first and second LDO circuits supply power to the internal components of the MCU chip. The switching circuit switches between the first and second LDO circuits, allowing the MCU chip to operate in different modes. The switching circuit includes: A copy controllable circuit is used to copy the output current of the first LDO circuit and output a first copied current. as well as The replication circuit, connected to the replication controllable circuit, is used to replicate the first replication current and output the second replication current to the second LDO circuit. The second LDO circuit establishes an internal loop based on the second replication current. Establishing an internal loop means that all nodes inside the second LDO circuit are stabilized in a state that enables the second LDO circuit to output the final desired voltage and provide the final desired current. The controllable replication circuit is used to cut off the current flow between the switching circuit and the first and second LDO circuits after the second LDO circuit establishes an internal loop. The operating mode of the MCU chip is switched from the mode powered by the first LDO circuit to the mode powered by the second LDO circuit. The first LDO circuit is used to maintain the normal operation of the MCU chip, and the second LDO circuit is used to maintain the low power mode of the MCU chip.

2. The MCU chip as described in claim 1, characterized in that, The controllable replication circuit includes a switching unit and a replication current unit. The switching unit is connected to the first LDO circuit, and the replication current unit is connected to both the switching unit and the replication circuit. When both the switching unit and the replication current unit are turned on, the replication current unit replicates the output current of the first LDO circuit and outputs the first replication current.

3. The MCU chip as described in claim 2, characterized in that, The switching unit includes a first switch, the first end of which is connected to the gate of the output power transistor of the first LDO circuit, and the second end of which is connected to the replication current unit.

4. The MCU chip as described in claim 2, characterized in that, The replication current unit includes a second switch and a second MOS transistor; the gate of the second MOS transistor is connected to the second terminal of the second switch and the switching unit, the source of the second MOS transistor is connected to the first terminal of the second switch and the power supply voltage, and the drain of the second MOS transistor is connected to the replication circuit.

5. The MCU chip as described in claim 1, characterized in that, The MCU chip also includes a delay control circuit, which is used to delay and turn off the output power transistor of the first LDO circuit.

6. The MCU chip as described in claim 5, characterized in that, The delay control circuit includes a delay unit, an inverter, and an eighth MOS transistor. The delay unit is connected to the input terminal of the inverter, the output terminal of the inverter is connected to the gate of the eighth MOS transistor, the drain of the eighth MOS transistor is connected to the gate of the output power transistor of the first LDO circuit, and the source of the eighth MOS transistor is connected to the power supply voltage.

7. The MCU chip as described in claim 1, characterized in that, The replication circuit includes a third MOS transistor and a fourth MOS transistor. The gate and drain of the third MOS transistor are connected and connected to the replication controllable circuit. The source of the third MOS transistor and the source of the fourth MOS transistor are connected to ground voltage. The drain of the fourth MOS transistor is connected to the output terminal of the second LDO circuit.

8. The MCU chip as described in claim 1, characterized in that, The MCU chip also includes a selection circuit, which is used to connect the output of the second LDO circuit and the load inside the MCU chip after the current between the second LDO circuit and the switching circuit is cut off.

9. The MCU chip as described in claim 8, characterized in that, The MCU chip also includes a current comparison circuit, which is used to compare the output current of the first LDO circuit with the reference current and control the selection circuit according to the comparison result.

10. The MCU chip as described in claim 9, characterized in that, The current comparison circuit includes a fifth MOSFET, a sixth MOSFET, and a seventh MOSFET. The gate of the fifth MOSFET is connected to the gate of the output power transistor of the first LDO circuit. The source of the fifth MOSFET is connected to the power supply voltage. The drain of the fifth MOSFET is connected to the drain of the sixth MOSFET and is connected to the selection circuit. The gate of the sixth MOSFET is connected to the gate of the seventh MOSFET. The gate and drain of the seventh MOSFET are connected. The source of the seventh MOSFET and the source of the sixth MOSFET are connected to ground voltage. The drain of the seventh MOSFET is used to receive the reference current.

11. A method for switching operating modes of an MCU chip, characterized in that, include: Switching from normal operating mode to low power mode: The first LDO circuit supplies power to the MCU chip and maintains the normal operation of the MCU chip. The copy controllable circuit is activated to receive the output current of the first LDO circuit and copy the output of the first copy current. The first replication current is replicated by the replication circuit, and the second replication current is output to the second LDO circuit. The second LDO circuit establishes an internal loop based on the second replicated current. After the output current of the second LDO circuit completes the replication of the output current of the first LDO circuit, the current flow between the first LDO circuit and the second LDO circuit is cut off. The second LDO circuit supplies power to the MCU chip and maintains the low-power mode of the MCU chip. Establishing an internal loop means that all nodes inside the second LDO circuit are stabilized in a state that enables the second LDO circuit to output the final desired voltage and provide the final desired current.

12. The method for switching operating modes of an MCU chip as described in claim 11, characterized in that, The method for switching working modes also includes: Switching from low-power mode to normal operating mode: Power is supplied to the MCU chip through the second LDO circuit; The output current of the first LDO circuit is compared with the reference current by a current comparison circuit. Based on the comparison result, the selection circuit is controlled to disconnect the connection between the second LDO circuit and the load, and the first LDO circuit supplies power to the MCU chip.

Images