Electronic devices for accessing memory and methods for writing data

Abstract

This application discloses an electronic device for accessing memory and a method for writing data. The electronic device includes a processing unit, a bus, and a memory controller. The processing unit includes a bus interface control circuit, which generates a first write instruction based on a memory access instruction via the bus interface control circuit. The memory access instruction includes a first memory address and a target value, and the first write instruction includes the first memory address and the target value. The bus is coupled to the bus interface control circuit and is used to generate a second write instruction based on the first write instruction. The second write instruction includes a second memory address and the target value. The memory controller is coupled to the bus and is used to write the target value into the memory based on the second memory address.

Description

Technical Field

[0001] This invention application relates to electronic devices, and more particularly to electronic devices for accessing memory and methods for writing data. Background Technology

[0002] The memset function in C (see: https: / / github.com / gcc-mirror / gcc / blob / master / libgcc / memset.c) is mainly used by the central processing unit (CPU) to uniformly set a block of memory, such as clearing a block of memory (e.g., writing the value 0 to all of that block of memory).

[0003] To implement the memset function, a typical CPU uses the following method: storing a fixed value in memory and repeatedly executing the function until the required number is reached. This method consumes a significant amount of CPU time to move data. Even when writing the same data, the CPU still needs to execute multiple lines of code repeatedly (consuming considerable memory or program space) to complete the process. Without burst write functionality or with a limited burst write length, the system takes even longer.

[0004] In C, similar functions to memset include strset and strnset. Furthermore, other languages ​​(such as Python and TCL) also have corresponding functions, and the CPU or system encounters the same problem when executing these functions. Summary of the Invention

[0005] In view of the shortcomings of the prior art, one object of the present invention is to provide an electronic device and a data writing method to improve the shortcomings of the prior art.

[0006] An embodiment of the present invention provides an electronic device for accessing memory, comprising a processing unit, a bus, and a memory controller. The processing unit includes a bus interface control circuit, which generates a first write instruction based on a memory access instruction via the bus interface control circuit. The memory access instruction includes a first memory address and a target value, and the first write instruction includes the first memory address and the target value. The bus is coupled to the bus interface control circuit and is used to generate a second write instruction based on the first write instruction. The second write instruction includes a second memory address and the target value. The memory controller is coupled to the bus and is used to write the target value into the memory based on the second memory address.

[0007] Another embodiment of the present invention provides a data writing method for writing data to memory, comprising: generating a first write instruction through a bus interface control circuit according to a memory access instruction, wherein the memory access instruction includes a first memory address and a target value, and the first write instruction includes the first memory address and the target value; generating a second write instruction according to the first write instruction, wherein the second write instruction includes a second memory address and the target value; and writing the target value to the memory according to the second memory address.

[0008] Another embodiment of the present invention provides an electronic device for accessing memory, comprising a processing unit, a bus, and a memory controller. The processing unit includes a computing circuit and a bus interface control circuit. The computing circuit generates a first write instruction via the bus interface control circuit based on a memory access instruction. The memory access instruction includes a first memory address and a target value, while the first write instruction includes a second memory address and the target value. The bus is coupled to the bus interface control circuit and is used to generate a second write instruction based on the first write instruction. The second write instruction includes the second memory address and the target value. The memory controller is coupled to the bus and is used to write the target value into the memory based on the second memory address.

[0009] The features, practical operation, and effects of this invention will be described in detail below with reference to the accompanying drawings. Attached Figure Description

[0010] Figure 1 This is a functional block diagram of an embodiment of the electronic device of the present invention;

[0011] Figure 2 This is a functional block diagram of another embodiment of the electronic device of the present invention;

[0012] Figure 3 This is a flowchart of an embodiment of the data writing method of the present invention;

[0013] Figure 4 This is the detailed process of step S330;

[0014] Figure 5 This is the detailed process of step S360;

[0015] Figure 6 This is a flowchart of another embodiment of the data writing method of the present invention;

[0016] Figure 7 This is the detailed process of step S660;

[0017] Figure 8 This is a functional block diagram of another embodiment of the electronic device of the present invention;

[0018] Figure 9This is a flowchart of another embodiment of the data writing method of the present invention; and

[0019] Figure 10 This is the detailed process of step S940.

[0020] Symbol Explanation

[0021] 100, 200, 800: Electronic devices

[0022] 110, 210, 810: Processing Units

[0023] 120, 220, 820: Bus or bus

[0024] 130, 230, 830: Memory controller

[0025] 135, 235, 835: Memory

[0026] 140, 240, 840: Peripheral Interface

[0027] 112, 212, 812: Cache

[0028] 114, 214, 814: Bus interface control circuit

[0029] 116, 216, 816: Main interface write circuit

[0030] 118, 218, 818: Main interface reading circuit

[0031] 211, 811: Address Mapping Control Unit

[0032] WI1: First write command

[0033] WI2: Second write command

[0034] 805: Computational Circuits

[0035] S310, S320, S330, S340, S350, S360, S370, S380, S410, S420, S430, S510, S520, S610, S620, S630, S640, S650, S660, S670, S680, S710, S720, S730, S740, S910, S920, S930, S940, S950, S960, S970, S980, S1010, S1020, S1030: Steps Detailed Implementation

[0036] The technical terms used in the following description are based on the customary terms in this technical field. If this specification provides explanations or definitions for certain terms, the explanations or definitions in this specification shall prevail.

[0037] This invention discloses an electronic device for accessing memory and a data writing method. Since some components of the electronic device of this invention may be known individually, details of known components will be omitted in the following description without affecting the full disclosure and implementability of the invention. Furthermore, part or all of the data writing method of this invention can be in software and / or hardware form and can be executed by the electronic device of this invention or its equivalent. Without affecting the full disclosure and implementability of the method invention, the following description of the method invention will focus on the steps rather than the hardware.

[0038] Figure 1 This is a functional block diagram of an embodiment of the electronic device of the present invention. The electronic device 100 includes a processing unit 110, a bus (or interconnect) 120, a memory controller 130, memory 135, and a peripheral interface 140. The processing unit 110 includes a cache 112 and a bus interface control circuit 114. The bus interface control circuit 114 includes a main interface write circuit 116 and a main interface read circuit 118.

[0039] Figure 2 This is a functional block diagram of another embodiment of the electronic device of the present invention. The electronic device 200 includes a processing unit 210, a bus (or bus) 220, a memory controller 230, memory 235, and a peripheral interface 240. The processing unit 210 includes an address mapping control unit 211, a cache 212, and a bus interface control circuit 214. The bus interface control circuit 214 includes a main interface write circuit 216 and a main interface read circuit 218.

[0040] Processing unit 110 and processing unit 210 can be circuits or electronic components with program execution capabilities, such as central processing unit, microprocessor, microprocessor unit, digital signal processor, application-specific integrated circuit (ASIC), or equivalent circuits thereof.

[0041] Processing unit 110 (or 210) controls or operates bus 120 (or 220) via bus interface control circuit 114 (or 214). Master interface write circuit 116 (or 216) is primarily used to perform write operations on slave devices (e.g., memory), while master interface read circuit 118 (or 218) is primarily used to perform read operations on slave devices. Peripheral interface 140 (or 240) can be a Universal Serial Bus (USB) or a Universal Asynchronous Receiver / Transmitter (UART).

[0042] The address mapping control unit 211 stores the mapping between physical addresses and virtual addresses of memory, which can be accessed by the processing unit 210, the bus 220, and the memory controller 230.

[0043] Figure 3 This is a flowchart illustrating one embodiment of the data writing method of the present invention. Please refer to the following description as well. Figures 1-3 .

[0044] Step S310: Processing unit 110 (or 210) generates a first write instruction WI1 through bus interface control circuit 114 (or 214) based on memory access instructions (e.g., based on the filled cache contents, i.e., machine code compiled by the compiler). The first write instruction WI1 contains a first memory address and a target value. Taking the RISC-V ("RISC" stands for reduced instruction set computer) architecture as an example, the memory access instruction is, for example, "MEMSET rd,rs1,rs2", and one example format is shown below:

[0045]

[0046] Where "rd" represents the destination address of the MEMSET operation, "rs1" represents the number of MEMSET operations (or length information), "rs2" represents a fixed value for the MEMSET operation, "imm" is used to support different data types or width definitions (the default value is 0, where 0 represents 1 byte wide, 1 represents 2 bytes wide, 2 represents 4 bytes wide, 8 represents 8 bytes wide, 9 represents 16 bytes wide, and so on), "opt" is an optional field (it can have a value or not), and "OP code" represents the operation code (in this example, "OP code" = 0x3f means that the memory access instruction is an extended instruction of processing unit 110 (or 210)).

[0047] When the processing unit 110 (or 210) executes the memory access instruction, the processing unit 110 (or 210) converts the information contained in the memory access instruction into an instruction on the bus 120 (or 220). More specifically, the processing unit 110 (or 210) generates a first write instruction WI1 (i.e., an instruction on the bus 120 (or 220)) through the bus interface control circuit 114 according to the memory access instruction, and the first write instruction WI1 contains a first memory address (i.e., the value of "rd"), length information (i.e., the value of "rs1"), and a target value (i.e., the value of "rs2").

[0048] Taking bus 120 (or 220) as an Advanced eXtensible Interface (AXI) as an example, when processing unit 110 (or 210) executes the memory access instruction, the first write instruction WI1 generated by processing unit 110 (or 210) through bus interface control circuit 114 (or 214) includes awaddr (destination address, i.e., the value of "rd"), awlen (burst length, i.e., the value of "rs1"), awsize (the value of "imm"), awvalid (equal to 1), wdata (target value, i.e., the value of "rs2"), wstrb (mask bit of each byte) and ID. Among them, wdata, wstrb and ID belong to the WChannel information of AXI. In some embodiments, bus interface control circuit 114 (or 214) can specify the user extension signal of AXI instruction (e.g., awuser[0]) to a special value (e.g., 1) to indicate that the first write instruction WI1 is an instruction related to the memset function. For details about AXI, please refer to: https: / / en.wikipedia.org / wiki / Advanced_eXtensible_Interface.

[0049] Step S320: Bus 120 (or 220) determines whether the number N_WI2 of the generated second write instructions WI2 is equal to the length information. More specifically, after receiving the first write instruction WI1, bus 120 (or 220) first stores the length information (i.e., the value of "rs1"). The result of step S320 is yes, indicating that bus 120 (or 220) has completed the first write instruction WI1 (i.e., completed the operation equivalent to the memset, strset, or strnset functions); the result of step S320 is no, indicating that bus 120 (or 220) has not completed the first write instruction WI1. The second write instruction WI2 will be described in detail below.

[0050] Step S330: Bus 120 (or 220) generates a second write instruction WI2 based on the first write instruction WI1. The second write instruction WI2 contains the second memory address and the target value. Details of step S330 will be provided later. Figure 4 As detailed below. After the second write instruction WI2 is generated, bus 120 (or 220) transmits the second write instruction WI2 to memory controller 130 (or 230).

[0051] Step S340: Bus 120 (or 220) updates the number N_WI2 of the generated second write instruction WI2, for example, by incrementing N_WI2 by 1.

[0052] Step S350: Bus 120 (or 220) determines whether the first write instruction WI1 is a string-related instruction. If the first write instruction WI1 is a string-related instruction (e.g., corresponding to the strset or strnset function), the result of step S350 is yes (proceed to step S360); otherwise, it is no (proceed to step S370).

[0053] Step S360: Bus 120 (or 220) determines whether the end of the string has been reached. If bus 120 (or 220) has processed to the end of the string (i.e., the processing of the string has been completed), the result of step S360 is yes (proceed to step S380), otherwise it is no (proceed to step S370).

[0054] Step S370: Memory controller 130 (or 230) writes the target value to memory 135 (or 235) according to the second memory address. In some embodiments, memory controller 130 (or 230) writes the target value to the second memory address. After step S370 is completed, the process returns to step S320.

[0055] Step S380: Bus 120 (or 220) stops writing the target value to memory 135 (or 235) (i.e., stops generating the second write instruction WI2). In other words, bus 120 (or 220) has completed the operation equivalent to the memset, strset, or strnset functions.

[0056] exist Figure 3 In the process, if the length information (i.e., the value of "rs1") is greater than the maximum burst length that the memory controller 130 (or 230) can accept, the bus 120 (220) will split a second write instruction WI2 into multiple transmissions and record the source, destination address and number of the current transmission so that the transmission can continue next time.

[0057] Please see Figure 4 , Figure 4 This is a detailed process of step S330, which includes the following sub-steps.

[0058] Step S410: Bus 120 (or 220) determines whether it needs to query the address mapping control unit 211. If the result of step S410 is no, bus 120 executes step S430; if the result of step S410 is yes, bus 220 executes step S420. Because Figure 1 The embodiment does not include an address mapping control unit, so bus 120 does not need to query the address mapping control unit. Figure 2In one embodiment, whenever the address processed by the bus 220 (i.e., the first memory address) exceeds a default address range (e.g., 4KB) of the address mapping control unit 211, the bus 220 needs to request an address translation from the address mapping control unit 211 to obtain the destination address (i.e., to translate the virtual address into a physical address).

[0059] Step S420: Bus 220 accesses the address mapping control unit 211 based on the first memory address to obtain the physical address, and generates a second memory address based on the physical address and the number N_WI2 of the generated second write instructions WI2. More specifically, the first memory address is a virtual address, and the address mapping control unit 211 records the physical address corresponding to the first memory address. After obtaining the physical address, bus 220 offsets the physical address by the number N_WI2 to generate the second memory address. The second write instruction WI2 contains the second memory address and the target value.

[0060] Step S430: Bus 120 updates the second memory address based on the first memory address and the number of second write instructions WI2 generated. More specifically, the first memory address is a physical address, and the address after offset N_WI2 from the first memory address is the current physical address (i.e., the second memory address). The second write instruction WI2 contains the second memory address and the target value.

[0061] Please see Figure 5 , Figure 5 This is a detailed process of step S360, which includes the following sub-steps.

[0062] Step S510: Bus 120 (or 220) controls memory controller 130 (or 230) to access memory 135 (or 235) to read a portion of a string (the portion being, for example, the end of the string).

[0063] Step S520: Bus 120 (or 220) determines whether this part of the string contains a string end marker (e.g., "0"). If the result of step S520 is yes, then the result of step S360 is yes; otherwise, the result of S360 is no.

[0064] Figure 6 This is a flowchart illustrating another embodiment of the data writing method of the present invention. Please refer to the following description as well. Figures 1-2 and Figure 6 The operational details of steps S610, S640, and S650 are similar to or the same as those of steps S310, S350, and S360, respectively, and will not be repeated here.

[0065] Step S620: Bus 120 (or 220) generates a second write instruction WI2 based on the first write instruction WI1. The second write instruction WI2 includes a second memory address, a target value, and length information. In some embodiments, the second write instruction WI2 may be equal to the first write instruction WI1 (in other words, the second memory address is equal to the first memory address). After the second write instruction WI2 is generated, bus 120 (or 220) transmits the second write instruction WI2 to memory controller 130 (or 230).

[0066] Step S630: The memory controller 130 (or 230) determines whether the number of writes N_TR of the target value is equal to the length information. More specifically, after receiving the second write instruction WI2, the memory controller 130 (or 230) first stores the length information (i.e., the value of "rs1"). The result of step S630 is yes, indicating that the memory controller 130 (or 230) has completed the second write instruction WI2 (i.e., completed the operation equivalent to the memset function, strset function, or strnset function); the result of step S630 is no, indicating that the memory controller 130 (or 230) has not completed the second write instruction WI2.

[0067] Step S660: Memory controller 130 (or 230) writes the target value to memory 135 (or 235) according to the second memory address. Details of step S660 will be provided later. Figure 7 The details are as follows.

[0068] Step S670: Memory controller 130 (or 230) updates the write count N_TR of the target value, for example, by incrementing N_TR by 1.

[0069] Step S680: Memory controller 130 (or 230) stops writing the target value to memory 135 (or 235). That is, memory controller 130 (or 230) has completed an operation equivalent to the memset, strset, or strnset functions.

[0070] Please see Figure 7 , Figure 7 This is a detailed process of step S660, which includes the following sub-steps.

[0071] Step S710: Memory controller 130 (or 230) determines whether it is necessary to query address mapping control unit 211. If the result of step S710 is no, memory controller 130 executes steps S730 and S740; if the result of step S710 is yes, memory controller 230 executes steps S720 and S740.

[0072] Step S720: The memory controller 230 obtains the physical address from the address mapping control unit 211 based on the second memory address, and generates a third memory address based on the physical address and the number of writes N_TR. More specifically, the second memory address is a virtual address, and the address mapping control unit 211 records the physical address corresponding to the second memory address. After obtaining the physical address, the memory controller 230 offsets the physical address by the number of writes N_TR to generate the third memory address.

[0073] Step S730: The memory controller 130 generates a third memory address based on the second memory address and the number of writes N_TR. More specifically, the second memory address is a physical address, and the address after the second memory address offset by the number of writes N_TR is the current physical address (i.e., the third memory address).

[0074] Step S740: Memory controller 130 (or 230) writes the target value to the third memory address of memory 135 (or 235).

[0075] In the above embodiments, the response timing of bus 120 (or 220) or memory controller 130 (or 230) is as follows: (1) responding to processing unit 110 (or 210) upon receiving the first write instruction WI1 (or the second write instruction WI2); or (2) responding after all write operations are completed. The response methods include (but are not limited to) sending a response and / or interrupting the transmission.

[0076] In summary, using a bus or memory controller to implement operations related to continuous memory writes (including but not limited to the memset, strset, and strnset functions in C) has the following advantages: (1) fewer instructions need to be processed by the processing unit; (2) shorter processing unit execution time; and (3) avoids prolonged occupation of the bandwidth between the processing unit and the bus (i.e., Figure 3 (in embodiments) or the bandwidth between the processing unit and the memory controller (i.e., Figure 6 (Examples provided). In other words, this invention discloses an apparatus and method for accelerating continuous memory writes on a bus or memory controller by extending the instructions of the processing unit and the communication protocol. This invention reduces the time spent on the processing unit, improves code efficiency, reduces the amount of code (i.e., occupies less program space), and significantly reduces transactions between the processing unit and the bus (i.e., allows the processing unit to transfer more data via the bus).

[0077] Figure 8This is a functional block diagram of another embodiment of the electronic device of the present invention. The electronic device 800 includes a processing unit 810, a bus (or bus) 820, a memory controller 830, memory 835, and a peripheral interface 840. The processing unit 810 includes a computing circuit 805, an address mapping control unit 811, a cache 812, and a bus interface control circuit 814. The bus interface control circuit 814 includes a main interface write circuit 816 and a main interface read circuit 818. The computing circuit 805 can be an engine of the processing unit 810 or a co-processor. The functions of the address mapping control unit 811, cache 812, bus interface control circuit 814, main interface write circuit 816, and main interface read circuit 818 are similar to or the same as those of the address mapping control unit 811, cache 812, bus interface control circuit 814, main interface write circuit 816, and main interface read circuit 818, respectively, and therefore will not be described again.

[0078] Figure 9 This is a flowchart of another embodiment of the data writing method of the present invention. Figure 10 This is the detailed process for step S940. Please refer to the following explanation as well. Figures 8-10 .

[0079] Step S910: The calculation circuit 805 determines whether the number N_WI1 of the generated first write instructions WI1 is equal to the length information. Step S910 is similar to step S320; please refer to the description of step S320.

[0080] Step S920: The computing circuit 805 determines whether the memory access instruction is a string-related instruction. Step S920 is similar to step S350; please refer to the description of step S350.

[0081] Step S930: The calculation circuit 805 determines whether the end of the string has been reached. Step S930 is similar to step S360; please refer to the description of step S360. Figure 5 .

[0082] Step S940: The calculation circuit 805 generates a first write instruction WI1 through the bus interface control circuit 814 based on the memory access instruction. The memory access instruction includes a first memory address and a target value, and the first write instruction includes a second memory address and a target value. Details of step S940 will be provided later. Figure 10 The details are as follows.

[0083] Step S950: The calculation circuit 805 updates the number N_WI1 of the first write instructions WI1 that have been generated, for example, by incrementing N_WI1 by 1.

[0084] Step S960: Bus 820 generates a second write instruction WI2 based on the first write instruction WI1, wherein the second write instruction WI2 contains a second memory address. In some embodiments, bus 820 may not process the first write instruction WI1 and directly transmit the first write instruction WI1 to memory controller 830; in other words, the second write instruction WI2 is equal to the first write instruction WI1.

[0085] Step S970: The memory controller 830 writes the target value to memory 835 according to the second memory address. Step S970 is similar to step S370; please refer to the description of step S370.

[0086] Step S980: The calculation circuit 805 stops writing the target value to memory 835 (i.e., stops generating the first write instruction WI1). Step S980 is similar to step S380; please refer to the description of step S380.

[0087] Step S1010: The calculation circuit 805 determines whether it is necessary to query the address mapping control unit 811. If the result of step S1010 is no, the calculation circuit 805 executes step S1030; if the result of step S1010 is yes, the calculation circuit 805 executes step S1020. Step S1010 is similar to step S410; please refer to the description of step S410.

[0088] Step S1020: The calculation circuit 805 obtains the physical address based on the first memory address access address mapping control unit 811, and generates a second memory address based on the physical address and the number N_WI1 of the generated first write instructions. Step S1020 is similar to step S420; please refer to the description of step S420.

[0089] Step S1030: The calculation circuit 805 updates the second memory address based on the first memory address and the number N_WI1 of the generated first write instructions WI1. Step S1030 is similar to step S430; please refer to the description of step S430.

[0090] exist Figures 8-10 In this embodiment, the processing unit 810 uses an engine or coprocessor to perform operations related to the memset, strset, or strnset functions. In this way, other engines or coprocessors of the processing unit 810 can perform other tasks, so the processing unit 810's working time will not be consumed in large quantities.

[0091] Although the embodiments disclosed above use C language as an example, this is not a limitation of the present invention. Those skilled in the art can appropriately apply the present invention to other types of programming languages ​​(such as Python, TCL, etc.) based on the disclosure of the present invention.

[0092] Although the embodiments disclosed above use AXI as an example, this is not a limitation of the present invention. Those skilled in the art can appropriately apply the present invention to other types of buses (such as AMBA (Advanced Micro-controller Bus Architecture), APB (Advanced Peripheral Bus), or AHB (Advanced High-performance Bus)) based on the disclosure of the present invention.

[0093] Although the embodiments disclosed above use RISC-V as an example, this is not a limitation of the present invention. Those skilled in the art can appropriately apply the present invention to other types of architectures (such as CISC, MIPS, ARM, RISC) based on the disclosure of the present invention.

[0094] Since those skilled in the art can understand the implementation details and variations of the method invention through the disclosure of the apparatus in this invention, repeated descriptions are omitted here to avoid redundancy, without affecting the disclosure requirements and implementability of the method invention. Please note that the shapes, sizes, and proportions of the components in the illustrations disclosed above are merely illustrative and intended to help those skilled in the art understand the purpose of this invention, and are not intended to limit the invention. Furthermore, in some embodiments, the order of the steps mentioned in the flowcharts disclosed above can be adjusted according to actual operation, and they can even be performed simultaneously or partially simultaneously.

[0095] While the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention. Those skilled in the art can make changes to the technical features of the present invention based on the explicit or implicit content of the present invention. All such changes may fall within the scope of patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be determined by the scope defined in the claims of this application.

Claims

1. An electronic device for accessing memory, characterized in that, The electronic device includes: The processing unit includes a bus interface control circuit. The processing unit generates a first write instruction through the bus interface control circuit according to a memory access instruction. The memory access instruction includes a first memory address and a target value. The first write instruction includes the first memory address, the target value, and length information. A bus, coupled to the bus interface control circuit, is used to receive the first write instruction and continuously generate one or more second write instructions according to the length information in the first write instruction until the number of second write instructions generated is equal to the length information, wherein each second write instruction contains a second memory address and the target value, and the bus updates the second memory address according to the first memory address and the number of second write instructions generated; as well as A memory controller, coupled to the bus, is used to write the target value into the memory according to the second memory address in each of the second write instructions.

2. The electronic device as claimed in claim 1, characterized in that, The processing unit further includes an address mapping control unit, and the bus further accesses the address mapping control unit according to the first memory address to obtain a physical address, and generates a second memory address according to the physical address and the number of physical addresses.

3. The electronic device as claimed in claim 1, characterized in that... The memory controller continuously writes the target value into the memory until the number of writes equals the length information.

4. The electronic device as claimed in claim 3, characterized in that, The memory controller generates a third memory address based on the second memory address and the number of writes, and writes the target value to the third memory address.

5. The electronic device as claimed in claim 3, characterized in that, The processing unit further includes an address mapping control unit. The memory controller accesses the address mapping control unit according to the second memory address to obtain a physical address, generates a third memory address according to the physical address and the number of writes, and writes the target value to the third memory address.

6. The electronic device as claimed in claim 1, characterized in that, The first write instruction pertains to a string, wherein the bus or the memory controller accesses the memory to read a portion of the string, and when the portion contains a string end marker, the bus stops generating the second write instruction, or the memory controller stops writing the target value into the memory.

7. A data writing method for writing data to memory, characterized in that, The data writing method includes: A first write instruction is generated by the bus interface control circuit according to the memory access instruction, wherein the memory access instruction includes a first memory address and a target value, and the first write instruction includes the first memory address, the target value, and length information; Based on the length information in the first write instruction, one or more second write instructions are continuously generated until the number of generated second write instructions equals the length information, wherein each of the second write instructions includes a second memory address and the target value, and the second memory address is updated according to the first memory address and the number of generated second write instructions; and The target value is written to the memory according to the second memory address in each of the second write instructions.

8. An electronic device for accessing memory, characterized in that, The electronic device includes: The processing unit includes a computing circuit and a bus interface control circuit. The computing circuit generates a first write instruction through the bus interface control circuit according to a memory access instruction. The memory access instruction includes a first memory address and a target value. The first write instruction includes a second memory address, the target value, and length information. A bus, coupled to the bus interface control circuit, is used to receive the first write instruction and continuously generate one or more second write instructions according to the length information in the first write instruction until the number of second write instructions generated is equal to the length information, wherein each second write instruction contains the second memory address and the target value, and the bus updates the second memory address according to the first memory address and the number of second write instructions generated; as well as A memory controller, coupled to the bus, is used to write the target value into the memory according to the second memory address in each of the second write instructions.

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