A frame synchronization-based GPU drawing instruction cache design method

Abstract

The application discloses a GPU drawing instruction buffer design method based on frame synchronization, which comprises a FIRST_BRAM memory, a SECOND_BRAM memory, a THIRD_BRAM memory and a read-write controller, adopts a three-level cache architecture, solves the problem of disorder of a frame of drawing instruction caused by the inconsistency of the sending rate of CPU sending drawing instruction and the reading rate of GPU reading drawing instruction, and guarantees the integrity of each frame of drawing instruction; the read-write controller is used to generate the read-write address signals and control signals of the FIRST_BRAM memory, the SECOND_BRAM memory and the THIRD_BRAM memory; and the application can output the graphic primitive drawing instruction and the character drawing instruction in parallel, thereby improving the GPU drawing efficiency.

Description

Technical Field

[0001] This invention belongs to the field of graphics rendering technology, specifically relating to a design method for a GPU graphics instruction cache. Background Technology

[0002] During graphics rendering, the CPU typically sends rendering commands, and the GPU receives and executes these commands. However, because the rates at which the CPU sends and the GPU reads rendering commands are inconsistent, this can lead to errors in the rendering commands within a single frame.

[0003] Therefore, designing a GPU drawing instruction buffer that can guarantee the complete output of drawing instructions for each frame is a prerequisite for correct graphics rendering. Summary of the Invention

[0004] To overcome the shortcomings of existing technologies, this invention provides a frame-synchronized GPU drawing instruction buffer design method, including FIRST_BRAM memory, SECOND_BRAM memory, THIRD_BRAM memory, and a read / write controller. Employing a three-level cache architecture, it solves the problem of inconsistent drawing instruction sending rates between the CPU and GPU, which leads to errors in drawing instructions within a single frame, thus ensuring the integrity of each frame's drawing instructions. The read / write controller generates read / write address signals and control signals for the FIRST_BRAM memory, SECOND_BRAM memory, and THIRD_BRAM memory. This invention can output primitive drawing instructions and character drawing instructions in parallel, improving GPU rendering efficiency.

[0005] The technical solution adopted by this invention to solve its technical problem includes the following steps:

[0006] Step 1: The cache system architecture includes FIRST_BRAM memory, SECOND_BRAM memory, THIRD_BRAM memory, and a read / write controller, adopting a three-level cache architecture;

[0007] The FIRST_BRAM memory stores drawing instructions sent by the CPU. When the FIRST_BRAM memory receives the end-of-frame flag, it continuously reads out a frame of drawing instructions stored in it and writes them into the SECOND_BRAM memory.

[0008] When the SECOND_BRAM memory receives the frame start drawing flag, the CPU continuously reads a frame of drawing instructions from the SECOND_BRAM memory. Based on different drawing instruction command words, the drawing instructions are divided into character drawing instructions and primitive drawing instructions and written into the THIRD_BRAM memory.

[0009] The THIRD_BRAM memory is divided into two parts, which store primitive drawing instructions and character drawing instructions respectively. The THIRD_BRAM memory reads primitive drawing instructions and character drawing instructions in parallel, and parallel drawing improves the GPU drawing efficiency.

[0010] The read / write controller generates read / write address signals and control signals for the FIRST_BRAM, SECOND_BRAM, and THIRD_BRAM memories;

[0011] Step 2: The clock for both read and write operations of the FIRST_BRAM memory is CPU_CLK; the drawing instructions sent by the CPU are stored starting from address 0 of the FIRST_BRAM memory for each frame. When the CPU_WR_EN signal is valid, the drawing instructions are stored in the FIRST_BRAM memory, and the bram1_wr_addr signal is incremented by 1.

[0012] When the end-of-frame flag signal is received, it indicates that a frame of drawing instructions has been sent. At this time, the bram1_wr_addr signal is cleared, the bram1_rd_addr signal is cleared, and the bram1_rd_en signal is valid.

[0013] After reading one frame of drawing instructions from the FIRST_BRAM memory continuously per CPU_CLK clock cycle, the bram1_rd_en signal becomes invalid; when the bram1_rd_en signal becomes valid, the drawing instructions are read from the FIRST_BRAM memory, and the bram1_rd_addr signal is incremented by 1.

[0014] Step 3: The clock for both ends of the SECOND_BRAM memory read and write is CPU_CLK; the drawing instructions read from the FIRST_BRAM memory are stored in the SECOND_BRAM memory according to the bram2_wr_en and bram2_wr_addr signals generated by the read / write controller;

[0015] When a frame start drawing flag signal is received, it indicates that the GPU will begin drawing a new frame. `bram2_rd_en` is active, and `bram2_rd_addr` is cleared. After reading one frame of drawing instructions from the SECOND_BRAM memory every CPU_CLK clock cycle, the `bram2_rd_en` signal becomes inactive. When the `bram2_rd_en` signal is active, drawing instructions are read from the SECOND_BRAM memory, and the `bram2_rd_addr` signal is incremented by 1.

[0016] Step 4: The THIRD_BRAM memory is divided into two parts, which store primitive drawing instructions and character drawing instructions respectively; the primitive drawing instructions include line drawing instructions, hollow circle drawing instructions, filled circle drawing instructions, and arc drawing instructions; the character drawing instructions include string drawing instructions.

[0017] The drawing instructions read from the SECOND_BRAM memory are divided into character drawing instructions and primitive drawing instructions based on different drawing instruction command words;

[0018] Step 5: The write clock for the THIRD_BRAM memory is CPU_CLK, and the read clock is GPU_CLK; the primitive drawing instructions and character drawing instructions read from the SECOND_BRAM memory are stored in the corresponding parts of the THIRD_BRAM memory according to the bram3_wr_en and bram3_wr_addr signals generated by the read / write controller.

[0019] When the frame start drawing flag signal is received, the bram3_rd_addr signal is cleared to zero; when the GPU_RD_EN signal is received, the bram3_rd_addr signal is incremented by 1, primitive drawing instructions and character drawing instructions are read in parallel from the THIRD_BRAM memory and sent to the GPU for drawing; the GPU reads primitive drawing instructions and character drawing instructions in parallel, which enables parallel drawing and thus improves drawing efficiency.

[0020] Step 6: The read / write controller can monitor the usage depth of the FIRST_BRAM memory; when the CPU sends a frame of drawing instructions abnormally, causing the number of drawing instructions in a frame to exceed the maximum depth of the FIRST_BRAM memory, it can generate a memory overflow flag signal and send it to the CPU for fault reporting.

[0021] The beneficial effects of this invention are as follows:

[0022] 1. The system architecture of this invention has low complexity, making it easy to implement in hardware;

[0023] 2. This invention adopts a three-level cache architecture design to ensure the integrity of each frame of drawing instructions;

[0024] 3. This invention can output primitive drawing instructions and character drawing instructions in parallel, thereby improving GPU rendering efficiency;

[0025] 4. This invention can monitor the usage depth of the internal memory and report overflow faults to the CPU. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the GPU graphics instruction cache architecture of the present invention. Detailed Implementation

[0027] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0028] The purpose of this invention is to provide a design method for a GPU drawing instruction buffer based on frame synchronization, which solves the problem of inconsistent drawing instruction rates between the CPU and the GPU, leading to disordered drawing instructions within a single frame.

[0029] A design method for a GPU drawing instruction buffer based on frame synchronization includes the following steps:

[0030] Step 1: The cache system architecture includes FIRST_BRAM memory, SECOND_BRAM memory, THIRD_BRAM memory and read / write controller. It adopts a three-level cache architecture, which solves the problem of inconsistent drawing instruction sending rates between the CPU and the GPU, resulting in the disorder of a frame of drawing instructions, and ensures the integrity of each frame of drawing instructions.

[0031] The FIRST_BRAM memory stores drawing instructions sent by the CPU. When the FIRST_BRAM memory receives the end-of-frame flag, it continuously reads out a frame of drawing instructions stored in it and writes them into the SECOND_BRAM memory.

[0032] When the SECOND_BRAM memory receives the frame start drawing flag, the CPU continuously reads a frame of drawing instructions from the SECOND_BRAM memory. Based on different drawing instruction command words, the drawing instructions are divided into character drawing instructions and primitive drawing instructions and written into the THIRD_BRAM memory.

[0033] The THIRD_BRAM memory is divided into two parts, which store primitive drawing instructions and character drawing instructions respectively. The THIRD_BRAM memory reads primitive drawing instructions and character drawing instructions in parallel, and parallel drawing improves the GPU drawing efficiency.

[0034] The read / write controller generates read / write address signals and control signals for the FIRST_BRAM, SECOND_BRAM, and THIRD_BRAM memories;

[0035] Step 2: The clock for both read and write operations of the FIRST_BRAM memory is CPU_CLK; the drawing instructions sent by the CPU are stored starting from address 0 of the FIRST_BRAM memory for each frame. When the CPU_WR_EN signal is valid, the drawing instructions are stored in the FIRST_BRAM memory, and the bram1_wr_addr signal is incremented by 1.

[0036] When the end-of-frame flag signal is received, it indicates that a frame of drawing instructions has been sent. At this time, the bram1_wr_addr signal is cleared, the bram1_rd_addr signal is cleared, and the bram1_rd_en signal is valid.

[0037] After reading one frame of drawing instructions from the FIRST_BRAM memory continuously per CPU_CLK clock cycle, the bram1_rd_en signal becomes invalid; when the bram1_rd_en signal becomes valid, the drawing instructions are read from the FIRST_BRAM memory, and the bram1_rd_addr signal is incremented by 1.

[0038] Step 3: The clock for both ends of the SECOND_BRAM memory read and write is CPU_CLK; the drawing instructions read from the FIRST_BRAM memory are stored in the SECOND_BRAM memory according to the bram2_wr_en and bram2_wr_addr signals generated by the read / write controller;

[0039] When a frame start drawing flag signal is received, it indicates that the GPU will begin drawing a new frame. `bram2_rd_en` is active, and `bram2_rd_addr` is cleared. After reading one frame of drawing instructions from the SECOND_BRAM memory every CPU_CLK clock cycle, the `bram2_rd_en` signal becomes inactive. When the `bram2_rd_en` signal is active, drawing instructions are read from the SECOND_BRAM memory, and the `bram2_rd_addr` signal is incremented by 1.

[0040] Step 4: The THIRD_BRAM memory is divided into two parts, which store primitive drawing instructions and character drawing instructions respectively; the primitive drawing instructions include line drawing instructions, hollow circle drawing instructions, filled circle drawing instructions, and arc drawing instructions; the character drawing instructions include string drawing instructions.

[0041] The drawing instructions read from the SECOND_BRAM memory are divided into character drawing instructions and primitive drawing instructions based on different drawing instruction command words;

[0042] Step 5: The write clock for the THIRD_BRAM memory is CPU_CLK, and the read clock is GPU_CLK; the primitive drawing instructions and character drawing instructions read from the SECOND_BRAM memory are stored in the corresponding parts of the THIRD_BRAM memory according to the bram3_wr_en and bram3_wr_addr signals generated by the read / write controller.

[0043] When the frame start drawing flag signal is received, the bram3_rd_addr signal is cleared to zero; when the GPU_RD_EN signal is received, the bram3_rd_addr signal is incremented by 1, primitive drawing instructions and character drawing instructions are read in parallel from the THIRD_BRAM memory and sent to the GPU for drawing; the GPU reads primitive drawing instructions and character drawing instructions in parallel, which enables parallel drawing and thus improves drawing efficiency.

[0044] Step 6: The read / write controller can monitor the usage depth of the FIRST_BRAM memory; when the CPU sends a frame of drawing instructions abnormally, causing the number of drawing instructions in a frame to exceed the maximum depth of the FIRST_BRAM memory, it can generate a memory overflow flag signal and send it to the CPU for fault reporting. Specific implementation examples:

[0046] 1. GPU graphics instruction buffer design architecture as follows Figure 1 As shown, it includes FIRST_BRAM memory, SECOND_BRAM memory, THIRD_BRAM memory, and read / write controller.

[0047] 2. The internal cache design adopts a three-level cache architecture, which solves the problem of inconsistent drawing instruction sending rates between the CPU and the GPU, which leads to the disorder of drawing instructions in a single frame.

[0048] 3. The clock for both read and write operations on the FIRST_BRAM memory is CPU_CLK. Each frame of drawing instructions sent by the CPU is stored starting at address 0 of the FIRST_BRAM memory. When the CPU_WR_EN signal is valid, the drawing instructions are stored in the FIRST_BRAM memory, and the bram1_wr_addr signal is incremented by 1. When the end-of-frame flag signal is received, it indicates that a frame of drawing instructions has been sent. At this moment, the bram1_wr_addr and bram1_rd_addr signals are cleared, and the bram1_rd_en signal is valid. After continuously reading a frame of drawing instructions from the FIRST_BRAM memory each cycle using CPU_CLK as the clock, the bram1_rd_en signal is deactivated. When the bram1_rd_en signal is valid, the drawing instructions are read from the FIRST_BRAM memory, and the bram1_rd_addr signal is incremented by 1.

[0049] 4. The clock for both read and write operations on the SECOND_BRAM memory is CPU_CLK. Drawing instructions read from the FIRST_BRAM memory are stored in the SECOND_BRAM memory according to the bram2_wr_en and bram2_wr_addr signals generated by the read / write controller. When a frame start drawing flag signal is received, it indicates that the GPU will begin drawing a new frame; bram2_rd_en is active, and the bram2_rd_addr signal is cleared. After continuously reading one frame of drawing instructions from the SECOND_BRAM memory per CPU_CLK clock cycle, the bram2_rd_en signal is deactivated. When the bram2_rd_en signal is active, drawing instructions are read from the SECOND_BRAM memory, and the bram2_rd_addr signal is incremented by 1.

[0050] 5. The THIRD_BRAM memory is divided into two parts, storing primitive drawing instructions and character drawing instructions respectively. Primitive drawing instructions include line drawing instructions, hollow circle drawing instructions, filled circle drawing instructions, and arc drawing instructions, while character drawing instructions include string drawing instructions. The drawing instructions read from the SECOND_BRAM memory are categorized into character drawing instructions and primitive drawing instructions based on different drawing instruction command words.

[0051] 6. The write clock for the THIRD_BRAM memory is CPU_CLK, and the read clock is GPU_CLK. Primitive drawing instructions and character drawing instructions read from the SECOND_BRAM memory are stored in their respective portions of the THIRD_BRAM memory according to the bram3_wr_en and bram3_wr_addr signals generated by the read / write controller. When the frame start drawing flag signal is received, the bram3_rd_addr signal is cleared to zero. When the GPU_RD_EN signal is received, the bram3_rd_addr signal is incremented by 1, and primitive drawing instructions and character drawing instructions are read in parallel from the THIRD_BRAM memory and sent to the GPU for drawing. The GPU's parallel reading of primitive drawing instructions and character drawing instructions enables parallel drawing, thereby improving drawing efficiency.

[0052] 7. Due to the inconsistency between the CPU's drawing instruction sending rate and the GPU's drawing instruction reading rate, when the CPU's drawing instruction sending rate is fast and the GPU's drawing instruction reading rate is slow, a frame of drawing instructions stored in the SECOND_BRAM memory may be overwritten by a new frame of drawing instructions read from the FIRST_BRAM memory before it is read and written to the THIRD_BRAM memory, thus discarding a frame of drawing instructions. Conversely, when the CPU's drawing instruction sending rate is slow and the GPU's drawing instruction reading rate is fast, a frame of drawing instructions stored in the SECOND_BRAM memory may be read twice and written to the THIRD_BRAM memory, thus repeatedly reading a frame of drawing instructions. Since the clocks for both read and write operations of the SECOND_BRAM memory are synchronized, read-write conflicts can be avoided. Therefore, the three-level cache architecture proposed in this paper can guarantee the integrity of each frame of drawing instructions.

[0053] 8. The read / write controller generates read / write address signals and control signals for the FIRST_BRAM, SECOND_BRAM, and THIRD_BRAM memories.

[0054] 9. The read / write controller can monitor the usage depth of the FIRST_BRAM memory. When the CPU sends a frame of drawing instructions abnormally, causing the number of drawing instructions in a frame to exceed the maximum depth of the FIRST_BRAM memory, it can generate a memory overflow flag signal and send it to the CPU for fault reporting.

Claims

1. A design method for a GPU drawing instruction buffer based on frame synchronization, characterized in that, Includes the following steps: Step 1: The cache system architecture includes FIRST_BRAM memory, SECOND_BRAM memory, THIRD_BRAM memory, and a read / write controller, adopting a three-level cache architecture; The FIRST_BRAM memory stores drawing instructions sent by the CPU. When the FIRST_BRAM memory receives the end-of-frame flag, it continuously reads out a frame of drawing instructions stored in it and writes them into the SECOND_BRAM memory. When the SECOND_BRAM memory receives the frame start drawing flag, the CPU continuously reads a frame of drawing instructions from the SECOND_BRAM memory. Based on different drawing instruction command words, the drawing instructions are divided into character drawing instructions and primitive drawing instructions and written into the THIRD_BRAM memory. The THIRD_BRAM memory is divided into two parts, which store primitive drawing instructions and character drawing instructions respectively. The THIRD_BRAM memory reads primitive drawing instructions and character drawing instructions in parallel, and parallel drawing improves the GPU drawing efficiency. The read / write controller generates read / write address signals and control signals for the FIRST_BRAM, SECOND_BRAM, and THIRD_BRAM memories; Step 2: The clock for both read and write operations of the FIRST_BRAM memory is CPU_CLK; the drawing instructions sent by the CPU are stored starting from address 0 of the FIRST_BRAM memory for each frame. When the CPU_WR_EN signal is valid, the drawing instructions are stored in the FIRST_BRAM memory, and the bram1_wr_addr signal is incremented by 1. When the end-of-frame flag signal is received, it indicates that a frame of drawing instructions has been sent. At this time, the bram1_wr_addr signal is cleared, the bram1_rd_addr signal is cleared, and the bram1_rd_en signal is valid. After reading one frame of drawing instructions from the FIRST_BRAM memory continuously per CPU_CLK clock cycle, the bram1_rd_en signal becomes invalid; when the bram1_rd_en signal becomes valid, the drawing instructions are read from the FIRST_BRAM memory, and the bram1_rd_addr signal is incremented by 1. Step 3: The clock for both ends of the SECOND_BRAM memory read and write is CPU_CLK; the drawing instructions read from the FIRST_BRAM memory are stored in the SECOND_BRAM memory according to the bram2_wr_en and bram2_wr_addr signals generated by the read / write controller; When a frame start drawing flag signal is received, it indicates that the GPU will begin drawing a new frame. `bram2_rd_en` is active, and `bram2_rd_addr` is cleared. After reading one frame of drawing instructions from the SECOND_BRAM memory every CPU_CLK clock cycle, the `bram2_rd_en` signal becomes inactive. When the `bram2_rd_en` signal is active, drawing instructions are read from the SECOND_BRAM memory, and the `bram2_rd_addr` signal is incremented by 1. Step 4: The THIRD_BRAM memory is divided into two parts, which store primitive drawing instructions and character drawing instructions respectively; the primitive drawing instructions include line drawing instructions, hollow circle drawing instructions, filled circle drawing instructions, and arc drawing instructions; the character drawing instructions include string drawing instructions. The drawing instructions read from the SECOND_BRAM memory are divided into character drawing instructions and primitive drawing instructions based on different drawing instruction command words; Step 5: The write clock for the THIRD_BRAM memory is CPU_CLK, and the read clock is GPU_CLK; the primitive drawing instructions and character drawing instructions read from the SECOND_BRAM memory are stored in the corresponding parts of the THIRD_BRAM memory according to the bram3_wr_en and bram3_wr_addr signals generated by the read / write controller. When the frame start drawing flag signal is received, the bram3_rd_addr signal is cleared to zero; when the GPU_RD_EN signal is received, the bram3_rd_addr signal is incremented by 1, primitive drawing instructions and character drawing instructions are read in parallel from the THIRD_BRAM memory and sent to the GPU for drawing; the GPU reads primitive drawing instructions and character drawing instructions in parallel, which enables parallel drawing and thus improves drawing efficiency. Step 6: The read / write controller can monitor the usage depth of the FIRST_BRAM memory; when the CPU sends a frame of drawing instructions abnormally, causing the number of drawing instructions in a frame to exceed the maximum depth of the FIRST_BRAM memory, it can generate a memory overflow flag signal and send it to the CPU for fault reporting.

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