Method and apparatus for forming a dicing lane, computer readable storage medium

Abstract

The present application relates to a method for forming a cutting path, which is used for forming a cutting path defining a cutting track in cutting of a wafer, the method comprising: obtaining a layout paper of a plurality of chips on a wafer, the layout paper comprising layout information of the plurality of chips on the wafer, the layout information defining a plurality of rows of chips arranged at intervals along a first direction, each row of chips comprising at least one chip arranged at intervals along a second direction, the second direction being perpendicular to the first direction; reading the layout information in the layout paper; forming a plurality of first inner cutting paths extending along the second direction, the first inner cutting paths being located between each two adjacent rows of chips and extending to opposite ends of the wafer; and forming a plurality of second inner cutting paths extending along the first direction, the second inner cutting paths being located between adjacent chips of each row. The method for forming a cutting path provided by the present application automatically forms the cutting path by reading the layout information of the plurality of chips on the wafer in the layout paper, thereby reducing manual operation.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and in particular to a method and apparatus for forming dicing channels, and a computer-readable storage medium. Background Technology

[0002] In semiconductor chip packaging, wafers need to be diced to obtain individual chips. Before dicing, dicing lines need to be drawn between adjacent chips on the wafer so that the laser can cut the wafer along these lines during laser dicing. Currently, the dicing lines are fabricated manually based on a blueprint showing the arrangement of multiple chips on the wafer, which is inefficient. Summary of the Invention

[0003] In view of the shortcomings of the prior art, the purpose of this application is to provide a method for forming dicing channels, an apparatus for forming dicing channels, and a computer-readable storage medium, which can automatically form dicing channels according to drawings, thereby reducing manual operation and improving the efficiency of wafer dicing.

[0004] A method for forming dicing channels, used to form dicing channels that define the dicing trajectory in the dicing of a wafer, wherein a plurality of chips are grown on the wafer, the method comprising: acquiring a layout drawing of the plurality of chips on the wafer, the layout drawing including layout information of the plurality of chips on the wafer, the layout information including chip layout information defining a layout in which the plurality of chips are arranged in multiple rows, wherein the multiple rows of chips are spaced apart along a first direction, each row of chips including at least one chip spaced apart along a second direction, the second direction being perpendicular to the first direction; reading the layout information in the layout drawing; forming a plurality of first inner dicing channels extending along the second direction according to the read layout information, the first inner dicing channels being located between each adjacent two rows of chips and extending to opposite ends of the wafer; and forming a plurality of second inner dicing channels extending along the first direction according to the read layout information, the second inner dicing channels being located between adjacent chips in each row.

[0005] The above-mentioned method for forming dicing channels automatically forms a first inner dicing channel between every two adjacent rows of chips and a second inner dicing channel between every row of adjacent chips by reading the arrangement information of the multiple chips in the arrangement drawing on the wafer.

[0006] Optionally, before forming the plurality of first inner dicing channels extending along the second direction, the method further includes: acquiring the coordinate information of the plurality of chips, including: establishing a Cartesian coordinate system on the surface of the wafer with a preset position on the surface where the plurality of chips are arranged as the origin, the second direction as the horizontal axis, and the first direction as the vertical axis; acquiring the coordinate values ​​of the endpoints of each chip in the Cartesian coordinate system, wherein the coordinate values ​​of the endpoints include the horizontal coordinate value and the vertical coordinate value of the endpoints, and the endpoints are the endpoints of the orthographic projection of each chip onto the wafer. The formation of the plurality of first inner dicing channels extending along the second direction; and the formation of the plurality of second inner dicing channels extending along the first direction, includes: forming the plurality of first inner dicing channels extending along the second direction based on the read arrangement information and the coordinate information of the plurality of chips; and forming the plurality of second inner dicing channels extending along the first direction based on the read arrangement information and the coordinate information of the plurality of chips.

[0007] Optionally, the method further includes: forming a first edge dicing channel extending along a second direction to opposite ends of the wafer based on the read arrangement information and the coordinate information of the plurality of chips, wherein the first edge dicing channel is located on opposite sides of the plurality of rows of chips in a first direction.

[0008] Optionally, the method further includes: forming a plurality of second edge cutting channels extending along a first direction based on the read arrangement information and the coordinate information of the plurality of chips, wherein each second edge cutting channel is located on opposite sides of each row of chips in the second direction.

[0009] Optionally, the arrangement information further includes the spacing between two adjacent chips. The step of forming multiple first inner cleaving channels extending along a second direction based on the read arrangement information and the coordinate information of the multiple chips includes: forming a first inner cleaving channel extending along a second direction between each pair of adjacent rows of chips based on the read arrangement information and the coordinate information of the multiple chips; wherein forming a first inner cleaving channel extending along a second direction between each pair of adjacent rows of chips further includes: selecting a first chip and a second chip respectively included in two adjacent rows of chips in a first direction, wherein the ordinate value of the endpoint of the first chip is greater than the ordinate value of the endpoint of the second chip, the first side of the first chip is close to the second side of the second chip, and the first chip and the second chip are any two chips adjacent in the first direction among the two adjacent rows of chips; based on the first side... The coordinates of the first starting point of the first inner dicing channel are determined by using the coordinates of the endpoints of the first edge and the distance between the first chip and the second chip. The x-coordinate of the first starting point is equal to the x-coordinate of the endpoints on the first edge, and the y-coordinate of the first starting point is equal to the y-coordinate of the endpoints on the first edge minus half the distance between the first chip and the second chip. Alternatively, the coordinates of the first starting point of the first inner dicing channel are determined by using the coordinates of the endpoints on the second edge and the distance between the first chip and the second chip. The x-coordinate of the first starting point is equal to the x-coordinate of the endpoints on the second edge, and the y-coordinate of the first starting point is equal to the y-coordinate of the endpoints on the second edge plus half the distance between the first chip and the second chip. The first inner dicing channel is formed by extending from the first starting point along the second direction to the opposite ends of the wafer.

[0010] Optionally, the arrangement information further includes the spacing between two adjacent chips. The step of forming multiple second inner cutting channels extending along the first direction based on the read arrangement information and the coordinate information of the multiple chips includes: forming a second inner cutting channel extending along the first direction between every two adjacent chips in the second direction based on the read arrangement information and the coordinate information of the multiple chips; wherein forming a second inner cutting channel extending along the first direction between every two adjacent chips in the second direction further includes: selecting a third chip and a fourth chip that are adjacent in the second direction, wherein the abscissa value of the endpoint of the third chip is less than the abscissa value of the endpoint of the fourth chip, the third side of the third chip is close to the fourth side of the fourth chip, and the third chip and the fourth chip are any two chips facing each other in the second direction; based on the coordinate information of the endpoints on the third side... The coordinates of the second starting point of the second inner dicing channel are determined based on the coordinate values ​​and the distance between the third and fourth chips. The ordinate of the second starting point is equal to the ordinate of the endpoint on the third side, and the abscissa of the second starting point is equal to the abscissa of the endpoint on the third side plus half the distance between the third and fourth chips. Alternatively, the coordinates of the second starting point of the second inner dicing channel are determined based on the coordinates of the endpoint on the fourth side and the distance between the third and fourth chips. The ordinate of the second starting point is equal to the ordinate of the endpoint on the fourth side, and the abscissa of the second starting point is equal to the abscissa of the endpoint on the fourth side minus half the distance between the third and fourth chips. The second inner dicing channel is formed by extending from the second starting point along the first direction to the opposite ends of the wafer.

[0011] Optionally, when it is determined that at least one of the plurality of second inner dicing channels passes through at least one chip, and the ordinate value of the endpoint on the fifth side of the at least one chip is less than the ordinate value of the second starting point of the at least one second inner dicing channel, a first target portion of the at least one second inner dicing channel is removed to form at least one final second inner dicing channel. The first target portion of the at least one second inner dicing channel is the portion of the at least one second inner dicing channel whose ordinate value is less than the ordinate value of the first inner dicing channel located between the second starting point of the at least one second inner dicing channel and the fifth side. The fifth side is the side of the at least one chip closest to the second starting point of the at least one second inner dicing channel. Alternatively, when it is determined that at least one of the plurality of second inner dicing channels passes through at least one chip, and the ordinate value of the endpoint on the fifth side of the at least one chip is greater than the ordinate value of the second starting point of the at least one second inner dicing channel, the second target portion of the at least one second inner dicing channel is removed to form at least one final second inner dicing channel. The second target portion of the at least one second inner dicing channel is the portion of the at least one second inner dicing channel whose ordinate value is greater than the ordinate value of the first inner dicing channel located between the second starting point of the at least one second inner dicing channel and the fifth side. The fifth side is the side of the at least one chip that is close to the second starting point of the at least one second inner dicing channel.

[0012] Optionally, forming a first edge dicing path extending along a second direction to opposite ends of the wafer based on the read arrangement information and the coordinate information of the plurality of chips includes: determining a first row of edge chips and a second row of edge chips located at opposite edges, wherein the ordinate value of the endpoint of the first row of edge chips is greater than the ordinate value of the second row of edge chips; determining the coordinate value of a third starting point of a first sub-edge dicing path of the first edge dicing path based on the coordinate value of the endpoint of a first target chip in the first row of edge chips away from the wafer center, wherein the first target chip is any chip in the first row of edge chips, the abscissa value of the third starting point is equal to the abscissa value of the endpoint of the first target chip away from the wafer center, and the ordinate value of the third starting point is greater than the coordinate value of the first sub-edge dicing path of the first edge dicing path. The ordinate value of the endpoint of a target chip away from the wafer center is used to form the first sub-edge dicing channel by extending from the third starting point along the second direction to the opposite ends of the wafer. Based on the coordinate value of the endpoint of the second target chip in the second row of edge chips away from the wafer center, the coordinate value of the fourth starting point of the second sub-edge dicing channel of the first edge dicing channel is determined. The second target chip is any chip in the second row of edge chips. The abscissa value of the fourth starting point is equal to the abscissa value of the endpoint of the second target chip away from the wafer center, and the ordinate value of the fourth starting point is less than the ordinate value of the endpoint of the second target chip away from the wafer center. The second sub-edge dicing channel is formed by extending from the fourth starting point along the second direction to the opposite ends of the wafer.

[0013] Optionally, forming multiple second edge dicing channels extending along the first direction based on the read arrangement information and the coordinate information of the multiple chips includes: determining first edge chips and second edge chips on opposite sides of each row of chips in the second direction, wherein the abscissa value of the endpoint of the first edge chip is less than the abscissa value of the endpoint of the second edge chip; determining the coordinate value of the fifth starting point of the third sub-edge dicing channel of the second edge dicing channel based on the coordinate value of the endpoint of the first edge chip near the wafer edge, wherein the ordinate value of the fifth starting point is equal to the ordinate value of the endpoint of the first edge chip near the wafer edge, and the abscissa value of the fifth starting point is less than the abscissa value of the second edge chip. The horizontal coordinate value of the endpoint of the first edge chip near the wafer edge is used to form the third sub-edge dicing channel by extending from the fifth starting point along the first direction to both ends of the wafer. Based on the coordinate value of the endpoint of the second edge chip near the wafer edge, the coordinate value of the sixth starting point of the fourth sub-edge dicing channel of the second edge dicing channel is determined. The vertical coordinate value of the sixth starting point is equal to the vertical coordinate value of the endpoint of the second edge chip near the wafer edge, and the horizontal coordinate value of the sixth starting point is greater than the horizontal coordinate value of the endpoint of the second edge chip near the wafer edge. The fourth sub-edge dicing channel is formed by extending from the sixth starting point along the first direction to both ends of the wafer.

[0014] Optionally, the method further includes: when it is determined that at least one of the plurality of third sub-edge dicing channels passes through at least one chip, and the ordinate value of the endpoint of the sixth side of the at least one chip is less than the ordinate value of the fifth starting point of the at least one third sub-edge dicing channel, removing a third target portion of the at least one third sub-edge dicing channel to form at least one final third sub-edge dicing channel, wherein the third target portion is the portion of the at least one third sub-edge dicing channel whose ordinate value is less than the ordinate value of the first starting point of a first inner dicing channel located between the fifth starting point of the at least one third sub-edge dicing channel and the sixth side, and the sixth side is the portion of the at least one chip adjacent to the at least one third sub-edge dicing channel. The edge of the fifth starting point; or, when it is determined that at least one of the plurality of third sub-edge cut channels passes through at least one chip, and the ordinate value of the endpoint of the sixth side of the at least one chip is greater than the ordinate value of the fifth starting point of the at least one third sub-edge cut channel, the fourth target portion of the at least one third sub-edge cut channel is removed to form at least one final third sub-edge cut channel, the fourth target portion being the portion of the at least one third sub-edge cut channel whose ordinate value is greater than the ordinate value of the first inner cut channel located between the fifth starting point of the at least one third sub-edge cut channel and the sixth side, the sixth side being the edge of the at least one chip close to the fifth starting point of the at least one third sub-edge cut channel.

[0015] Optionally, the method further includes the steps of: generating a layout drawing of the plurality of chips on the wafer, including: obtaining the length and width of the chips, the radius of the wafer, and the spacing between adjacent chips; determining the number of chips in the first row, and setting the first row of chips from any end of the wafer along a second direction, wherein the spacing between adjacent chips in the first row is equal, and the opposite ends of the first row of chips in the second direction are located at opposite ends of the wafer, wherein the distance between the side of the first row of chips away from the center of the wafer and the center of the wafer is greater than the difference between the wafer radius and the width of the chips; determining the number of chips in the second row, and setting the second row of chips along the second direction on the side of the first row of chips closer to the center of the wafer, wherein the spacing between adjacent chips in the second row is equal to the spacing between adjacent chips in the first row, and equal to the spacing between the second row of chips and the first row of chips; and setting up to the Nth row of chips, wherein the alignment direction of each chip in each row is the same, and the number of chips in each row is the maximum number of chips that can be set in each row.

[0016] Optionally, determining the number of chips in the second row includes: when the length direction of the chips in the second row is parallel to the second direction, according to the first formula. The number of chips in the second row, X2, is calculated, where X2 is the integer part of X1. Here, R is the wafer radius, P is the number of chips in the first row, L is the chip length, W is the chip width, and G is the spacing between adjacent chips. When the length direction of the chips in the second row is parallel to the first direction, according to the second formula... The number of chips in the second row is calculated to be X4, where X4 is the integer part of X3, R is the wafer radius, P is the number of chips in the first row, L is the chip length, W is the chip width, and G is the spacing between adjacent chips.

[0017] Based on the same inventive concept, this application also provides a cutting channel forming apparatus, which includes a memory and a processor. The memory stores a computer program, which is used by the processor to execute the aforementioned cutting channel forming method.

[0018] Based on the same inventive concept, this application also provides a computer-readable storage medium storing a computer program for executing the aforementioned method of forming a cutting channel upon being invoked. Attached Figure Description

[0019] Figure 1 A flowchart illustrating a method for forming a cutting path as provided in an embodiment of this application;

[0020] Figure 2 This is a schematic diagram of the arrangement of multiple chips on a wafer provided in an embodiment of this application;

[0021] Figure 3 A schematic diagram showing the positions of the first and second inner dicing channels on the wafer, provided for embodiments of this application.

[0022] Figure 4 A schematic diagram of a planar rectangular coordinate system established on a wafer, provided for an embodiment of this application;

[0023] Figure 5 A flowchart illustrating a method for forming a first inner cutting channel as provided in an embodiment of this application;

[0024] Figure 6 A schematic diagram showing the position of the first inner dicing channel on the wafer, provided for an embodiment of this application;

[0025] Figure 7 A flowchart illustrating the method for forming a second inner cutting channel as provided in an embodiment of this application;

[0026] Figure 8 A schematic diagram showing the position of the formed second inner dicing channel on the wafer, provided for an embodiment of this application;

[0027] Figure 9 A schematic diagram showing the position of the second inner dicing channel on the wafer when it passes through at least one chip, as provided in an embodiment of this application.

[0028] Figure 10 A schematic diagram showing the position of the final second inner dicing channel on the wafer, provided for an embodiment of this application;

[0029] Figure 11 A schematic diagram showing the position of the second inner dicing channel on the wafer when the second inner dicing channel passes through at least one chip, as provided in another embodiment of this application;

[0030] Figure 12 A schematic diagram showing the position of the final second inner dicing channel on the wafer, provided for another embodiment of this application;

[0031] Figure 13 A flowchart illustrating a method for forming a first edge cutting path as provided in an embodiment of this application;

[0032] Figure 14 A schematic diagram showing the position of the first edge dicing channel formed on the wafer, provided for an embodiment of this application;

[0033] Figure 15 A flowchart illustrating the method for forming a second edge cutting path provided in an embodiment of this application;

[0034] Figure 16 A schematic diagram showing the position of the formed second edge dicing channel on the wafer, provided for an embodiment of this application;

[0035] Figure 17 A schematic diagram showing the position of the third sub-edge dicing channel on the wafer when the third sub-edge dicing channel passes through at least one chip, as provided in the embodiments of this application.

[0036] Figure 18 A schematic diagram showing the position of the final third sub-edge dicing channel on the wafer, provided for embodiments of this application;

[0037] Figure 19 A flowchart for generating a layout drawing of multiple chips on a wafer, provided for embodiments of this application;

[0038] Figure 20 This is a structural block diagram of the cutting channel forming apparatus provided in an embodiment of this application.

[0039] Explanation of reference numerals in the attached figures:

[0040] 10 - Chip; 20 - Wafer; 30 - First inner dicing track; 40 - Second inner dicing track; o - Origin; 11 - First chip; 12 - Second chip; 111 - First edge; 121 - Second edge; a - Endpoint of the first edge; b - Endpoint of the second edge; c - First starting point; 13 - Third chip; 14 - Fourth chip; 131 - Third edge; 141 - Fourth edge; d - Endpoint of the third edge; e - Endpoint of the fourth edge; f - Second starting point; 151 - Fifth edge; g, k - Two endpoints of the fifth edge; 41 - First target portion; 42 - Second target portion; 51 - First sub-edge dicing track; 52 - Second sub-edge dicing track; 60 - First row of edge chips; 70 - Second row of edge chips Chip; 16-First target chip; 17-Second target chip; 81-Third sub-edge dicing track; 82-Fourth sub-edge dicing track; m-Endpoint of the first target chip away from the wafer center; t-Endpoint of the second target chip away from the wafer center; q1-Third starting point; q2-Fourth starting point; 18-First edge chip; 19-Second edge chip; 181-Sixth side; 811-Third target portion; v-Endpoint of the first edge chip near the wafer edge; w-Endpoint of the second edge chip near the wafer edge; z1-Fifth starting point; z2-Sixth starting point; j, u-Two endpoints of the sixth side; 200-Dice forming apparatus; 201-Memory; 202-Processor. Detailed Implementation

[0041] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of this application.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0043] In the description of this application, the terms "first," "second," "third," "fourth," "fifth," "sixth," and "seventh" are used to distinguish different objects, not to describe a specific order. In addition, the terms "upper," "lower," "inner," and "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0044] Please refer to the following: Figures 1 to 3 , Figure 1 A flowchart illustrating a method for forming a cutting path according to an embodiment of this application. Figure 2 This is a schematic diagram showing the arrangement of multiple chips 10 on a wafer 20 according to an embodiment of this application. Figure 3 This is a schematic diagram showing the positions of the first inner dicing channel 30 and the second inner dicing channel 40 formed on the wafer 20, as provided in an embodiment of this application. The method for forming the dicing channels is used to form dicing channels that define the cutting trajectory during the cutting of the wafer 20, so that when the wafer 20 is cut using laser or infrared light, it can be cut along the dicing channels. Figure 1 As shown, the method for forming the cutting channel includes the following steps:

[0045] S101: Obtain a layout drawing of multiple chips 10 on the wafer 20. The layout drawing includes the arrangement information of the multiple chips 10 on the wafer 20. The arrangement information includes the layout information of the chips 10, which defines a layout in which the multiple chips 10 are arranged in multiple rows. The multiple rows of chips are spaced apart along a first direction, and each row includes at least one chip 10 spaced apart along a second direction, which is perpendicular to the first direction. Figure 2 As shown. The layout drawing is an electronic file.

[0046] S102: Read the layout information from the layout drawing.

[0047] S103: Based on the read arrangement information, a plurality of first inner dicing channels 30 extending along the second direction are formed. The first inner dicing channels 30 are located between each pair of adjacent rows of chips and extend to the opposite ends of the wafer 20, as shown in the figure. Figure 3 As shown.

[0048] S104: Based on the read arrangement information, a plurality of second inner cutting channels 40 extending along the first direction are formed. The second inner cutting channels 40 are located between adjacent chips 10 in each row, as shown in the figure. Figure 3 As shown.

[0049] The method for forming dicing channels provided in this application embodiment automatically forms a first inner dicing channel 30 located between every two adjacent rows of chips and a second inner dicing channel 40 located between adjacent chips 10 in each row by reading the arrangement information of the arrangement drawing of the plurality of chips 10 on the wafer 20.

[0050] In some embodiments, before forming the plurality of first inner dicing channels 30 extending along the second direction, the method for forming the dicing channels further includes: obtaining coordinate information of the plurality of chips 10, including: establishing a Cartesian coordinate system on the surface of the wafer 20 with a preset position on the surface of the wafer 20 where the plurality of chips 10 are arranged as the origin, the second direction as the horizontal axis, and the first direction as the vertical axis; obtaining the coordinate values ​​of the endpoints of each chip 10 in the Cartesian coordinate system, wherein the coordinate values ​​of the endpoints include the horizontal coordinate value and the vertical coordinate value of the endpoints, and the endpoints are the endpoints of the orthographic projection of each chip 10 onto the wafer 20.

[0051] For example, please refer to Figure 4 , Figure 4 This is a schematic diagram of a planar Cartesian coordinate system established on the surface of the wafer 20 where the chips 10 are arranged, as provided in an embodiment of this application. Figure 4 As shown, in this embodiment, a Cartesian coordinate system is established with the wafer center as the origin o, the x-axis as the horizontal axis and the y-axis as the vertical axis. The second direction is the x-axis direction and the first direction is the y-axis direction.

[0052] In some embodiments, the coordinate values ​​of the endpoints of each chip 10 in the Cartesian coordinate system can be obtained based on the arrangement information. The arrangement information also includes the fact that the chip 10 is a cuboid, the length and width of the chip 10, the number of chips in each row, the distance between each row of chips and the center of the wafer, the spacing between adjacent chips 10, and the alignment of adjacent chips 10. The length and width of the chip 10 are the length and width of the orthographic projection of the chip 10 on the wafer 20. The distances of the endpoints of each chip 10 to the horizontal axis and the vertical axis of the coordinate system are calculated based on the arrangement information, and the relative positions of the endpoints of each chip 10 to the origin of the Cartesian coordinate system are obtained based on the arrangement information, thereby obtaining the coordinate values ​​of the endpoints of each chip 10.

[0053] In some embodiments, forming a plurality of first inner cleaving channels 30 extending along a second direction and forming a plurality of second inner cleaving channels 40 extending along a first direction includes: forming a plurality of first inner cleaving channels 30 extending along a second direction based on the read arrangement information and the coordinate information of the plurality of chips 10; and forming a plurality of second inner cleaving channels 40 extending along a first direction based on the read arrangement information and the coordinate information of the plurality of chips 10.

[0054] The formation of multiple first inner dicing channels 30 and multiple second inner dicing channels 40 refers to obtaining the coordinate information of the multiple first inner dicing channels 30 and multiple second inner dicing channels 40 on the wafer 20. Since the coordinate information includes multiple coordinate points forming corresponding trajectories on the wafer 20, forming multiple first inner dicing channels 30 and multiple second inner dicing channels 40 is equivalent to determining multiple dicing channels to be cut on the wafer 20. Furthermore, the cutting equipment can locate the corresponding multiple first inner dicing channels on the wafer 20 according to the coordinate information of the multiple first inner dicing channels 30, to perform positioning and cutting along the multiple first inner dicing channels 30, and locate multiple second inner dicing channels 40 on the wafer 20 according to the coordinate information of the multiple second inner dicing channels 40, to perform positioning and cutting along the multiple second inner dicing channels 40.

[0055] In some embodiments, forming a plurality of first inner cleaving channels 30 extending along a second direction includes: forming a plurality of first inner cleaving channels 30 extending along a second direction according to the read arrangement information and the coordinate information of the plurality of chips 10. Specifically, according to the read arrangement information and the coordinate information of the plurality of chips 10, a plurality of first inner cleaving channels 30 extending along a second direction are formed between each two adjacent rows of chips.

[0056] Please see Figure 5 , Figure 5 A flowchart illustrating a method for forming the first inner cutting channel 30 provided in an embodiment of this application. Figure 5 As shown, forming a first inner cleavage 30 extending along a second direction between every two adjacent rows of chips includes the following steps:

[0057] S1031: Select two adjacent rows of chips, including a first chip and a second chip respectively in a first direction, wherein the ordinate value of the endpoint of the first chip is greater than the ordinate value of the endpoint of the second chip, the first side of the first chip is close to the second side of the second chip, and the first chip and the second chip are any two adjacent chips 10 in the two adjacent rows of chips in the first direction.

[0058] S1032: Based on the coordinates of the endpoints on the first side and the distance between the first chip and the second chip, determine the coordinates of the first starting point of the first inner cutting channel 30. The x-coordinate of the first starting point is equal to the x-coordinate of the endpoints on the first side, and the y-coordinate of the first starting point is equal to the y-coordinate of the endpoints on the first side minus half the distance between the first chip and the second chip; or, based on the coordinates of the endpoints on the second side and the distance between the first chip and the second chip, determine the coordinates of the first starting point of the first inner cutting channel 30. The x-coordinate of the first starting point is equal to the x-coordinate of the endpoints on the second side, and the y-coordinate of the first starting point is equal to the y-coordinate of the endpoints on the second side plus half the distance between the first chip and the second chip.

[0059] S1033: The first inner dicing channel 30 is formed by extending from the first starting point along the second direction to the opposite ends of the wafer 20.

[0060] For example, please refer to Figure 6 , Figure 6 This is a schematic diagram showing the position of the first inner dicing channel 30 formed on the wafer 20, provided in an embodiment of this application. In this embodiment, the layout information of the layout drawing includes: the length and width of each chip 10 are both 20mm; the spacing between any two adjacent chips 10 is 2mm; the multiple rows of chips include a first row, a second row, a third row, and a fourth row; the first row, second row, third row, and fourth row of chips are arranged sequentially and alternately along a first direction; the number of chips in the first row and the fourth row are both two; the number of chips in the second row and the third row are both four; the distance between the second row of chips and the center of the wafer is equal to the distance between the third row of chips and the center of the wafer and is 1mm; the distance between the first row of chips and the center of the wafer is equal to the distance between the fourth row of chips and the center of the wafer and is 23mm.

[0061] A Cartesian coordinate system is established with the wafer center as the origin, the second direction as the x-axis, and the first direction as the y-axis. Based on the aforementioned arrangement information, the coordinate values ​​of each chip 10 are obtained. From the multiple rows of chips, the following is selected: Figure 6 The first chip 11 and the second chip 12 are shown. The coordinates of the first starting point are determined based on the coordinates of the endpoint a of the first side 111 of the first chip 11 and the distance between the first chip 11 and the second chip 12. Wherein, the x-coordinate of endpoint a is 1 and the y-coordinate is 23, then the x-coordinate of the first starting point is determined to be 1 and the y-coordinate to be 22, thus obtaining the following... Figure 6 The first starting point c shown extends along the x-axis to both ends of the wafer 20, forming the first inner dicing channel 30. Obviously, the coordinates of the first starting point can also be determined based on the coordinates of the other end of the first side 111 and the distance between the first chip 11 and the second chip 12. Wherein, the x-coordinate of the other end of the first side 111 is 21 and the y-coordinate is 23, then the x-coordinate of the first starting point is determined to be 21 and the y-coordinate to be 22.

[0062] Alternatively, the coordinates of the first starting point can be determined based on the coordinates of the endpoint b of the second side 121 of the second chip 12 and the distance between the first chip 11 and the second chip 12. Where the x-coordinate of endpoint b is 1 and the y-coordinate is 21, then the x-coordinate of the first starting point is determined to be 1 and the y-coordinate to be 22, thus obtaining the following... Figure 6 The first starting point c shown extends along the x-axis to both ends of the wafer 20, forming the first inner dicing channel 30. Obviously, the coordinates of the first starting point can also be determined based on the coordinates of the other endpoint of the second side 121 and the distance between the first chip 11 and the second chip 12. Wherein, the x-coordinate of the other endpoint of the second side 121 is 21 and the y-coordinate is 21, then the x-coordinate of the first starting point is determined to be 21 and the y-coordinate to be 22.

[0063] In some embodiments, forming a plurality of second inner cutting channels 40 extending along a first direction based on the read arrangement information and the coordinate information of the plurality of chips 10 includes: forming a second inner cutting channel 40 extending along a first direction between every two adjacent chips 10 in a second direction based on the read arrangement information and the coordinate information of the plurality of chips, thereby forming a plurality of second inner cutting channels 40.

[0064] Please see Figure 7 , Figure 7 A flowchart illustrating the formation of the second inner cutting channel 40 provided for an embodiment of this application. (See attached flowchart.) Figure 7As shown, forming a second inner cleavage 40 extending along the first direction between every two adjacent chips 10 in the second direction includes the following steps:

[0065] S1041: Select a third chip and a fourth chip that are adjacent in the second direction, wherein the x-coordinate value of the endpoint of the third chip is less than the x-coordinate value of the endpoint of the fourth chip, the third side of the third chip is close to the fourth side of the fourth chip, and the third chip and the fourth chip are any two chips 10 that are directly opposite each other in the second direction.

[0066] S1042: Based on the coordinates of the endpoints on the third side and the distance between the third chip and the fourth chip, determine the coordinates of the second starting point of the second inner cutting channel 40. The ordinate of the second starting point is equal to the ordinate of the endpoints on the third side, and the abscissa of the second starting point is equal to the abscissa of the endpoints on the third side plus half the distance between the third chip and the fourth chip; or, based on the coordinates of the endpoints on the fourth side and the distance between the third chip and the fourth chip, determine the coordinates of the second starting point of the second inner cutting channel 40. The ordinate of the second starting point is equal to the ordinate of the endpoints on the fourth side, and the abscissa of the second starting point is equal to the abscissa of the endpoints on the fourth side minus half the distance between the third chip and the fourth chip.

[0067] S1043: The second inner dicing channel 40 is formed by extending from the second starting point along the first direction to the opposite ends of the wafer 20.

[0068] For example, please refer to Figure 8 , Figure 8 This is a schematic diagram showing the position of the formed second inner dicing channel 40 on the wafer 20, as provided in an embodiment of this application. Figure 8 As shown in this embodiment, the layout information of the layout drawing includes: the length and width of the chip 10 are both 20mm, the spacing between any two adjacent chips 10 is 2mm, the multi-row chips include a first row of chips, a second row of chips, a third row of chips, and a fourth row of chips, the first row of chips, the second row of chips, the third row of chips, and the fourth row of chips are arranged sequentially and alternately along a first direction, the number of chips in the first row of chips and the fourth row of chips are both two, the number of chips in the second row of chips and the third row of chips are both four, the distance between the second row of chips and the center of the wafer is equal to the distance between the third row of chips and the center of the wafer and is 1mm, and the distance between the first row of chips and the center of the wafer is equal to the distance between the fourth row of chips and the center of the wafer and is 23mm.

[0069] Using the wafer center as the origin, the second direction as the x-axis, and the first direction as the y-axis, a Cartesian coordinate system is established. Based on the aforementioned arrangement information, the coordinate values ​​of each chip 10 are obtained. Adjacent chips along the x-axis are selected... Figure 8 The third chip 13 and the fourth chip 14 are shown. Based on the coordinates of the endpoint d on the third side 131 and the distance between the third chip 13 and the fourth chip 14, the coordinates of the second starting point are determined. Where the x-coordinate of endpoint d is -23 and the y-coordinate is 21, the x-coordinate of the second starting point is determined to be -22 and the y-coordinate to be 21, thus obtaining the following... Figure 8 The second starting point f shown extends along the y-axis to both ends of the wafer 20, forming the second inner dicing channel 40. Obviously, the coordinates of the second starting point can also be determined based on the coordinates of the other endpoint on the third side 131 and the distance between the third chip 13 and the fourth chip 14. Wherein, the x-coordinate of the other endpoint of the third side 131 is -23 and the y-coordinate is 1, then the x-coordinate of the second starting point is determined to be -22 and the y-coordinate to be 1.

[0070] Alternatively, based on the coordinates of the endpoint e of the fourth side 141 of the fourth chip 14 and the distance between the third chip 13 and the fourth chip 14, the coordinates of the second starting point are determined. Where the x-coordinate of endpoint e is -21 and the y-coordinate is 21, then the x-coordinate of the second starting point is determined to be -22 and the y-coordinate to be 21, thus obtaining the following... Figure 8 The second starting point f shown extends along the y-axis to both ends of the wafer 20, forming the second inner dicing channel 40. Obviously, the coordinates of the second starting point can also be determined based on the coordinates of the other endpoint on the fourth side 141 and the distance between the third chip 13 and the fourth chip 14. Wherein, the x-coordinate of the other endpoint of the third side 131 is -21 and the y-coordinate is 1, then the x-coordinate of the second starting point is determined to be -22 and the y-coordinate to be 1.

[0071] In some embodiments, when it is determined that at least one of the plurality of second inner cleaving channels 40 passes through at least one chip 10, and the ordinate value of the endpoint on the fifth side of the at least one chip 10 is less than the ordinate value of the second starting point of the at least one second inner cleaving channel 40, a first target portion of the at least one second inner cleaving channel 40 is removed to form at least one final second inner cleaving channel 40. The first target portion of the at least one second inner cleaving channel 40 is the portion of the at least one second inner cleaving channel 40 whose ordinate value is less than the ordinate value of the first inner cleaving channel 30 located between the second starting point of the at least one second inner cleaving channel 40 and the fifth side. The fifth side is the side of the at least one chip 10 that is close to the second starting point of the at least one second inner cleaving channel 40.

[0072] Alternatively, when it is determined that at least one of the plurality of second inner cleaving channels 40 passes through at least one chip 10, and the ordinate value of the endpoint on the fifth side of the at least one chip 10 is greater than the ordinate value of the second starting point of the at least one second inner cleaving channel 40, the second target portion of the at least one second inner cleaving channel 40 is removed to form at least one final second inner cleaving channel 40, wherein the second target portion of the at least one second inner cleaving channel 40 is the portion of the at least one second inner cleaving channel 40 whose ordinate value is greater than the ordinate value of the first inner cleaving channel 30 located between the second starting point of the at least one second inner cleaving channel 40 and the fifth side, and the fifth side is the side of the at least one chip 10 that is close to the second starting point of the at least one second inner cleaving channel 40.

[0073] For example, please refer to Figure 9 , Figure 9 This is a schematic diagram showing the position of the second inner dicing channel 40 on the wafer 20 when it passes through at least one chip 10, as provided in an embodiment of this application. Figure 9 As shown, in this embodiment, the layout information of the layout drawing includes: the length and width of each chip 10 are both 20mm, the spacing between any two adjacent chips 10 is 2mm, the multiple rows of chips include a first row of chips, a second row of chips, a third row of chips, and a fourth row of chips, the first row of chips, the second row of chips, the third row of chips, and the fourth row of chips are arranged sequentially and alternately along a first direction, the first row of chips has two chips, the second row of chips and the third row of chips each have four chips, the fourth row of chips has three chips, the distance between the first row of chips and the center of the wafer is 26.26mm, the distance between the second row of chips and the center of the wafer is 4.26mm, and the distance between the fourth row of chips and the center of the wafer is 19.74mm.

[0074] like Figure 9 As shown, a Cartesian coordinate system is established with the endpoint of one of the chips 10 located at the edge of the first row of chips near the wafer edge as the origin, the second direction as the x-axis, and the first direction as the y-axis. Based on the aforementioned arrangement information, the coordinate values ​​of each chip 10 are obtained. When the second inner dicing channel 40 passes through the chip 10, and the ordinate value of the endpoint g on the fifth side 151 of the chip 10 is 64, which is less than the ordinate value 66 of the second starting point f of the second inner dicing channel 40 in this embodiment, the final second inner dicing channel 40 is formed by removing the first target portion 41 of the second inner dicing channel 40. The first target portion 41 is the portion of the second inner dicing channel 40 where the ordinate value is less than the ordinate value 65 of the first inner dicing channel 30 located between the second starting point f and the fifth side 151. That is, removing the portion of the second inner dicing channel 40 where the ordinate value is less than 65 forms the final second inner dicing channel 40. The result is as follows. Figure 10 As shown, Figure 10 The final position of the second inner dicing 40 on the wafer 20 is shown.

[0075] In some other embodiments, please refer to Figure 11 , Figure 11 This is a schematic diagram showing the position of the second inner dicing channel 40 on the wafer 20 when it is provided as another embodiment of this application. (See diagram below.) Figure 11 As shown, in this embodiment, the layout information of the layout drawing includes: the length and width of each chip 10 are both 20mm, the spacing between any two adjacent chips 10 is 2mm, the multiple rows of chips include a first row of chips, a second row of chips, a third row of chips, and a fourth row of chips, the first row of chips, the second row of chips, the third row of chips, and the fourth row of chips are arranged sequentially and alternately along a first direction, the first row of chips has two chips, the second row of chips and the third row of chips each have four chips, the fourth row of chips has three chips, the distance between the first row of chips and the center of the wafer is 26.26mm, the distance between the second row of chips and the center of the wafer is 4.26mm, and the distance between the fourth row of chips and the center of the wafer is 19.74mm.

[0076] like Figure 11As shown, a Cartesian coordinate system is established with the endpoint of one of the chips 10 located at the edge of the first row of chips near the wafer edge as the origin, the second direction as the x-axis, and the first direction as the y-axis. Based on the aforementioned arrangement information, the coordinate values ​​of each chip 10 are obtained. When the second inner dicing channel 40 passes through the chip 10, and the ordinate value of the endpoint g on the fifth side 151 of the chip 10 in this embodiment is 66, which is greater than the ordinate value of the second starting point f of the second inner dicing channel 40 in this embodiment (64), the final second inner dicing channel 40 is formed by removing the second target portion 42 of the second inner dicing channel 40. The second target portion 42 is the portion of the second inner dicing channel 40 where the ordinate value is greater than the ordinate value 65 of the first inner dicing channel 30 located between the second starting point f and the fifth side 151. That is, the final second inner dicing channel 40 is formed by removing the portion of the second inner dicing channel 40 where the ordinate value is greater than 65. The result is as follows. Figure 12 As shown, Figure 12 This illustrates the position of the final second inner dicing 40 on the wafer 20 in this embodiment.

[0077] In some embodiments, determining that at least one of the plurality of second inner cut channels 40 passes through at least one chip 10 includes: determining that the at least one second inner cut channel 40 passes through the at least one chip 10 when the abscissa value of the second starting point of the at least one second inner cut channel 40 is located between the abscissa values ​​of the two endpoints of the at least one chip 10 in a second direction, that is, between the abscissa values ​​of the two endpoints of the fifth side 151 of the at least one chip 10.

[0078] For example, please refer again Figure 11 In this embodiment, the two endpoints of the chip 10 in the second direction are endpoint g and endpoint k, respectively. The horizontal coordinate of endpoint g is 9, the horizontal coordinate of endpoint k is -11, and the horizontal coordinate of the second starting point f of the second inner cutting channel 40 is -1. Therefore, it is determined that the second inner cutting channel 40 passes through the chip 10.

[0079] The method for forming a second inner cleaving channel provided in this application embodiment can determine whether the second inner cleaving channel passes through at least one chip 10, and when it is determined that the second inner cleaving channel passes through the at least one chip 10, remove the portion of the second inner cleaving channel that passes through the at least one chip 10 to form the final second inner cleaving channel.

[0080] In some embodiments, the method for forming the dicing channels further includes the step of: forming first edge dicing channels extending along a second direction to opposite ends of the wafer 20 based on the read arrangement information and the coordinate information of the plurality of chips 10, wherein the first edge dicing channels are located on opposite sides of the plurality of rows of chips in a first direction. Forming a plurality of first edge dicing channels refers to obtaining the coordinate information of the plurality of first edge dicing channels on the wafer 20. Since the coordinate information includes multiple coordinate points that form corresponding trajectories on the wafer 20, forming a plurality of first edge dicing channels is equivalent to determining a plurality of dicing channels to be cut on the wafer 20. Further, the cutting equipment can locate the corresponding plurality of first edge dicing channels on the wafer 20 based on the coordinate information of the plurality of first edge dicing channels, so as to perform positioning and cutting along the plurality of first edge dicing channels.

[0081] Please see Figure 13 , Figure 13 A flowchart illustrating a method for forming a first edge cutting path as provided in an embodiment of this application. Figure 13 As shown, in some embodiments, forming a first edge dicing path extending along a second direction to opposite ends of the wafer 20 based on the read arrangement information and the coordinate information of the plurality of chips 10 includes the following steps:

[0082] S1051: Determine the first row of edge chips and the second row of edge chips located at two opposite edges, wherein the ordinate value of the endpoint of the first row of edge chips is greater than the ordinate value of the second row of edge chips.

[0083] S1052: Based on the coordinate value of the endpoint of the first target chip in the first row of edge chips that is far from the wafer center, determine the coordinate value of the third starting point of the first sub-edge cutting channel of the first edge cutting channel, wherein the first target chip is any chip in the first row of edge chips, the abscissa of the third starting point is equal to the abscissa of the endpoint of the first target chip that is far from the wafer center, and the ordinate of the third starting point is greater than the ordinate of the endpoint of the first target chip that is far from the wafer center.

[0084] S1053: The first sub-edge dicing path is formed by extending from the third starting point along the second direction to the opposite ends of the wafer 20.

[0085] S1054: Based on the coordinate value of the endpoint of the second target chip in the second row of edge chips that is far from the wafer center, determine the coordinate value of the fourth starting point of the second sub-edge dicing channel of the first edge dicing channel, wherein the second target chip is any chip in the second row of edge chips, the abscissa of the fourth starting point is equal to the abscissa of the endpoint of the second target chip that is far from the wafer center, and the ordinate of the fourth starting point is less than the ordinate of the endpoint of the second target chip that is far from the wafer center.

[0086] S1055: The second sub-edge dicing path is formed by extending from the fourth starting point along the second direction to the opposite ends of the wafer 20.

[0087] For example, please refer to Figure 14 , Figure 14 This is a schematic diagram showing the position of the first edge dicing channel formed on wafer 20, provided for an embodiment of this application. Figure 14 As shown in this embodiment, the layout information of the layout drawing includes: the length and width of the chip 10 are both 20mm, the spacing between any two adjacent chips 10 is 2mm, the multi-row chips include a first row of chips, a second row of chips, a third row of chips, and a fourth row of chips, the first row of chips, the second row of chips, the third row of chips, and the fourth row of chips are arranged sequentially and alternately along a first direction, the number of chips in the first row of chips and the fourth row of chips are both two, the number of chips in the second row of chips and the third row of chips are both four, the distance between the second row of chips and the center of the wafer is equal to the distance between the third row of chips and the center of the wafer and is 1mm, and the distance between the first row of chips and the center of the wafer is equal to the distance between the fourth row of chips and the center of the wafer and is 23mm.

[0088] like Figure 14 As shown, a Cartesian coordinate system is established with the wafer center as the origin, the second direction as the x-axis, and the first direction as the y-axis. Based on the aforementioned arrangement information, the coordinate values ​​of each chip 10 are obtained, and the coordinates of the chips located at opposite edges are determined. Figure 14 The first row of edge chips 60 and the second row of edge chips 70 are shown, and the ordinate value of the endpoint of the first row of edge chips 60 is greater than the ordinate value of the second row of edge chips 70.

[0089] Specifically, based on the coordinate value of the endpoint m of the first target chip 16 in the first row of edge chips 60, which is furthest from the wafer center, the coordinate value of the third starting point of the first sub-edge dicing track 51 of the first edge dicing track is determined. Where the x-coordinate of endpoint m is -21 and the y-coordinate is 43, then the x-coordinate of the third starting point is -21 and the y-coordinate is greater than 43, i.e., the following is obtained: Figure 14The third starting point q1 shown extends along the second direction to the opposite ends of the wafer 20 to form the first sub-edge dicing channel 51. Obviously, the coordinates of the third starting point can also be determined based on the coordinates of the other end of the first target chip 16 furthest from the wafer center. Wherein, the x-coordinate of the other end of the first target chip 16 furthest from the wafer center is -1 and the y-coordinate is 43, then the x-coordinate of the third starting point is -1 and the y-coordinate is greater than 43.

[0090] Based on the coordinates of the endpoint t of the second target chip 17 in the second row of edge chips 70, which is furthest from the wafer center, the coordinates of the fourth starting point of the second sub-edge dicing track 52 of the first edge dicing track are determined. Where the x-coordinate of endpoint t is -21 and the y-coordinate is -43, the x-coordinate of the fourth starting point is -21, and the y-coordinate of the fourth starting point is less than -43. Therefore, the coordinates of the fourth starting point are obtained as follows: Figure 14 The fourth starting point q2 extends along the second direction to the opposite ends of the wafer 20 to form the first sub-edge dicing channel 51. Obviously, the coordinates of the fourth starting point can also be determined based on the coordinates of the other end of the second target chip 17 furthest from the wafer center. Where the x-coordinate of the other end of the second target chip 17 furthest from the wafer center is -1 and the y-coordinate is -43, then the x-coordinate of the fourth starting point is -1 and the y-coordinate is less than -43.

[0091] In some embodiments, the method for forming the dicing channels further includes: forming a plurality of second edge dicing channels extending along a first direction based on the read arrangement information and the coordinate information of the plurality of chips, wherein each second edge dicing channel is located on opposite sides of each row of chips in a second direction. Forming a plurality of second edge dicing channels refers to obtaining the coordinate information of the plurality of second edge dicing channels on the wafer 20. Since the coordinate information includes multiple coordinate points that form corresponding trajectories on the wafer 20, forming a plurality of second edge dicing channels is equivalent to determining a plurality of dicing channels to be cut on the wafer 20. Further, the cutting equipment can locate the corresponding plurality of second edge dicing channels on the wafer 20 based on the coordinate information of the plurality of second edge dicing channels, and perform positioning and cutting along the plurality of second edge dicing channels.

[0092] Please see Figure 15 , Figure 15 A flowchart illustrating a method for forming a first edge cutting path as provided in an embodiment of this application. Figure 15 As shown, in some embodiments, forming multiple second edge cutting channels extending along a first direction based on the read arrangement information and the coordinate information of the plurality of chips 10 includes the following steps:

[0093] S1061: Determine the first edge chip and the second edge chip on opposite sides of each row of chips in the second direction, wherein the x-coordinate value of the endpoint of the first edge chip is less than the x-coordinate value of the endpoint of the second edge chip.

[0094] S1062: Based on the coordinate value of the endpoint of the first edge chip near the wafer edge, determine the coordinate value of the fifth starting point of the third sub-edge dicing channel of the second edge dicing channel. The ordinate value of the fifth starting point is equal to the ordinate value of the endpoint of the first edge chip near the wafer edge, and the abscissa value of the fifth starting point is less than the abscissa value of the endpoint of the first edge chip near the wafer edge.

[0095] S1063: The third sub-edge dicing path is formed by extending from the fifth starting point along the first direction to both ends of the wafer 20.

[0096] S1064: Based on the coordinate value of the endpoint of the second edge chip near the wafer edge, determine the coordinate value of the sixth starting point of the fourth sub-edge dicing channel of the second edge dicing channel. The ordinate value of the sixth starting point is equal to the ordinate value of the endpoint of the second edge chip near the wafer edge, and the abscissa value of the sixth starting point is greater than the abscissa value of the endpoint of the second edge chip near the wafer edge.

[0097] S1065: The fourth sub-edge dicing path is formed by extending from the sixth starting point along the first direction to both ends of the wafer 20.

[0098] For example, please refer to Figure 16 , Figure 16 This is a schematic diagram showing the location of the formed second edge dicing channel on wafer 20, provided for an embodiment of this application. Figure 16 As shown in this embodiment, the layout information of the layout drawing includes: the length and width of the chip 10 are both 20mm, the spacing between any two adjacent chips 10 is 2mm, the multi-row chips include a first row of chips, a second row of chips, a third row of chips, and a fourth row of chips, the first row of chips, the second row of chips, the third row of chips, and the fourth row of chips are arranged sequentially and alternately along a first direction, the number of chips in the first row of chips and the fourth row of chips are both two, the number of chips in the second row of chips and the third row of chips are both four, the distance between the second row of chips and the center of the wafer is equal to the distance between the third row of chips and the center of the wafer and is 1mm, and the distance between the first row of chips and the center of the wafer is equal to the distance between the fourth row of chips and the center of the wafer and is 23mm.

[0099] like Figure 16As shown, a Cartesian coordinate system is established with the wafer center as the origin, the second direction as the x-axis, and the first direction as the y-axis. Based on the aforementioned arrangement information, the coordinate values ​​of each chip 10 are obtained, and the first edge chip 18 and the second edge chip 19 are determined. Based on the coordinate value of the endpoint v of the first edge chip 18 near the wafer edge, the coordinate value of the fifth starting point of the third sub-edge dicing channel 81 of the second edge dicing channel is determined. Wherein, the x-coordinate of the endpoint v is -43 and the y-coordinate is 21, therefore the y-coordinate of the fifth starting point is 21 and the x-coordinate is less than -43, i.e., the result is as follows. Figure 16 The fifth starting point z1 shown extends along the first direction from the fifth starting point z1 to both ends of the wafer 20 to form the third sub-edge dicing channel 81.

[0100] Based on the coordinate value of the endpoint w near the wafer edge of the second edge chip 19, the coordinate value of the sixth starting point of the fourth sub-edge dicing channel 82 of the second edge dicing channel is determined. Wherein, the abscissa of the endpoint w is 43 and the ordinate is 21. Therefore, the ordinate of the sixth starting point is 21 and the abscissa is greater than 43, i.e., the following is obtained: Figure 16 The sixth starting point z2 shown extends along the first direction to both ends of the wafer 20 to form the fourth sub-edge dicing channel 82.

[0101] In some embodiments, when it is determined that at least one of the plurality of third sub-edge cut channels 81 passes through at least one chip 10, and the ordinate value of the endpoint of the sixth side of the at least one chip 10 is less than the ordinate value of the fifth starting point of the at least one third sub-edge cut channel 81, a third target portion of the at least one third sub-edge cut channel 81 is removed to form at least one final third sub-edge cut channel 81. The third target portion is the portion of the at least one third sub-edge cut channel 81 whose ordinate value is less than the ordinate value of the first inner cut channel 20 located between the fifth starting point of the at least one third sub-edge cut channel and the sixth side. The sixth side is the side of the at least one chip 10 that is close to the fifth starting point of the at least one third sub-edge cut channel 81.

[0102] For example, please refer to Figure 17 , Figure 17 This is a schematic diagram showing the position of the third sub-edge dicing channel 81 on the wafer 20 when it passes through at least one chip, as provided in the embodiments of this application. Figure 17As shown, in this embodiment, the layout information of the layout drawing includes: the length and width of each chip 10 are both 20mm, the spacing between any two adjacent chips 10 is 2mm, the multiple rows of chips include a first row of chips, a second row of chips, a third row of chips, and a fourth row of chips, the first row of chips, the second row of chips, the third row of chips, and the fourth row of chips are arranged sequentially and alternately along a first direction, the first row of chips has two chips, the second row of chips and the third row of chips each have four chips, the fourth row of chips has three chips, the distance between the first row of chips and the center of the wafer is 26.26mm, the distance between the second row of chips and the center of the wafer is 4.26mm, and the distance between the fourth row of chips and the center of the wafer is 19.74mm.

[0103] like Figure 17 As shown, a Cartesian coordinate system is established with the endpoint of one of the chips 10 located at the edge of the first row of chips near the wafer edge as the origin, the second direction as the x-axis, and the first direction as the y-axis. Based on the aforementioned arrangement information, the coordinate values ​​of each chip 10 are obtained. When the third sub-edge dicing channel 81 passes through at least one chip 10, and the ordinate value of the endpoint j of the sixth side 181 of the at least one chip 10 is 64, which is less than the ordinate value 66 of the fifth starting point z1 of the third sub-edge dicing channel 81, the third target portion 811 of the at least one third sub-edge dicing channel 81 is removed to form at least one final third sub-edge dicing channel 81. The third target portion 811 is the portion where the ordinate value of the third sub-edge dicing channel 81 is less than the ordinate value 65 of the first inner dicing channel 20 located between the fifth starting point z1 and the sixth side 181. That is, the portion where the ordinate value of the third sub-edge dicing channel 81 is less than 65 is removed to form the final third sub-edge dicing channel 81. The result is as follows: Figure 18 As shown, Figure 18 The diagram illustrates the position of the final third sub-edge dicing 81 formed in this embodiment on the wafer 20.

[0104] In some other embodiments, when it is determined that at least one of the plurality of third sub-edge cut channels 81 passes through at least one chip 10, and the ordinate value of the endpoint of the sixth side 181 of the at least one chip 10 is greater than the ordinate value of the fifth starting point of the at least one third sub-edge cut channel 81, a fourth target portion of the at least one third sub-edge cut channel 81 is removed to form at least one final third sub-edge cut channel 81, wherein the fourth target portion is the portion of the at least one third sub-edge cut channel 81 whose ordinate value is greater than the ordinate value of the first inner cut channel 20 located between the fifth starting point of the at least one third sub-edge cut channel 81 and the sixth side 181, and the sixth side 181 is the side of the at least one chip 10 that is close to the fifth starting point of the at least one third sub-edge cut channel 81.

[0105] In some embodiments, determining that at least one of the plurality of third sub-edge cutting paths 81 passes through at least one chip 10 includes the step of: determining that the at least one third sub-edge cutting path 81 passes through at least one chip 10 when the abscissa value of the fifth starting point of the at least one third sub-edge cutting path 81 is between the abscissa values ​​of the two endpoints on the edge in the second direction of the at least one chip 10, that is, between the abscissa values ​​of the two endpoints of the sixth edge 181 of the at least one chip 10.

[0106] For example, please refer again Figure 17 The abscissa value of the fifth starting point z1 of the third sub-edge cutting channel 81 is -12, and the two endpoints on the edge of the chip 10 in the second direction are endpoint j and endpoint u, respectively. The abscissa value of endpoint j is -22, and the abscissa value of endpoint u is -2. Therefore, it is determined that the third sub-edge cutting channel 81 passes through the chip 10.

[0107] In some embodiments, when it is determined that at least one of the plurality of fourth sub-edge cut channels 82 passes through at least one chip 10, and the ordinate value of the endpoint of the seventh side of the at least one chip 10 is greater than the ordinate value of the sixth starting point of the at least one fourth sub-edge cut channel 82, a fifth target portion of the at least one fourth sub-edge cut channel 82 is removed to form at least one final fourth sub-edge cut channel 82. The fifth target portion is the portion of the at least one fourth sub-edge cut channel 82 whose ordinate value is greater than the ordinate value of the first inner cut channel 20 located between the sixth starting point of the at least one fourth sub-edge cut channel 82 and the seventh side. The seventh side is the side of the at least one chip 10 that is close to the sixth starting point of the at least one fourth sub-edge cut channel 82.

[0108] In some embodiments, determining that at least one of the plurality of fourth sub-edge cut channels 82 passes through at least one chip 10 includes the step of: determining that the at least one fourth sub-edge cut channel 82 passes through at least one chip 10 when the abscissa value of the sixth starting point of the at least one fourth sub-edge cut channel 82 is between the abscissa values ​​of the two endpoints on the edge in the second direction of the at least one chip 10.

[0109] The method for forming a second edge cutting channel provided in this application embodiment can determine whether the second edge cutting channel passes through at least one chip 10, and when it is determined that the second edge cutting channel passes through the at least one chip 10, remove the portion of the second edge cutting channel that passes through the at least one chip 10 to form the final second edge cutting channel.

[0110] Please see Figure 19 , Figure 19 This is a flowchart illustrating the generation of the arrangement of the plurality of chips 10 on the wafer 20, as provided in an embodiment of this application. Figure 19 As shown, in some embodiments, the method for forming the dicing path further includes the step of generating an arrangement pattern of the plurality of chips 10 on the wafer 20. Generating the arrangement pattern of the plurality of chips 10 on the wafer 20 includes the following steps:

[0111] S1071: Obtain the length and width of the chip 10, the radius of the wafer 20, and the spacing between adjacent chips 10.

[0112] S1072: Determine the number of chips in the first row and arrange the first row of chips along the second direction from any end of the wafer 20. The spacing between adjacent chips 10 in the first row is equal. The two ends of the first row of chips in the second direction are located at the two ends of the wafer 20, respectively. The distance between the side of the first row of chips away from the center of the wafer and the center of the wafer is greater than the difference between the wafer radius and the width of the chip 10.

[0113] S1073: Determine the number of chips in the second row of chips, and arrange the second row of chips along the second direction on the side of the first row of chips near the center of the wafer. The spacing between adjacent chips 10 in the second row of chips is equal to the spacing between adjacent chips 10 in the first row of chips, and is also equal to the spacing between the second row of chips and the first row of chips.

[0114] S1074: Set to the Nth row of chips, where the alignment direction of each chip in each row is the same, and the number of chips in each row is the maximum number of chips that can be set in each row.

[0115] In some embodiments, determining the number of chips in the first row of chips includes: sequentially setting the number of chips in the first row of chips to one, two, and increasing them one by one to M. When the number of chips in the first row of chips is P, and the number of chips 10 disposed on the wafer 20 is at most, the number of chips in the first row of chips is determined to be P, where P is one of one, two to M, and both P and M are integers.

[0116] In some embodiments, the length direction of the chips in the second row is parallel to the second direction, and determining the number of chips in the second row includes: according to the first formula. The number of chips in the second row, X2, is calculated, where X2 is the integer part of X1. R is the wafer radius, P is the number of chips in the first row, L is the chip length, W is the chip width, and G is the spacing between adjacent chips.

[0117] In some other embodiments, the length direction of the chips in the second row is parallel to the first direction, and determining the number of chips in the second row includes: according to the second formula. The number of chips in the second row is calculated to be X4, where X4 is the integer part of X3, R is the wafer radius, P is the number of chips in the first row, L is the chip length, W is the chip width, and G is the spacing between adjacent chips.

[0118] In the arrangement of multiple chips 10 on the wafer 20 provided in this embodiment, the first row of chips is arranged starting from the end of the wafer 20, with the opposite ends of the first row of chips positioned at opposite ends of the wafer 20. Existing arrangements of multiple chips on a wafer use the wafer center as the center of symmetry, leaving large blank spaces at the edges of each row of chips, resulting in wasted wafer space. Compared to existing arrangements of multiple chips on a wafer, the arrangement of multiple chips 10 on the wafer 20 provided in this embodiment effectively improves the utilization rate of the wafer 20, resulting in more chips 10. For example, when the diameter of the wafer 20 is 4 inches, the length and width of each chip 10 are both 20 mm, and the spacing between adjacent chips 10 is 2 mm, the existing center-arrangement method yields 12 chips, while the arrangement method provided in this embodiment yields 13 chips.

[0119] The method for forming dicing channels provided in this application embodiment reads the arrangement information of the plurality of chips 10 in the arrangement drawing on the wafer 20, and obtains the coordinate information of each chip 10 according to the arrangement information. Based on the coordinate information, a first inner dicing channel 30 located between each two adjacent rows of chips, a second inner dicing channel 40 located between adjacent chips 10 in each row, a first edge dicing channel located on opposite sides of the plurality of rows of chips in a first direction, and a second edge dicing channel located on opposite sides of each row of chips in a second direction are automatically formed.

[0120] Please see Figure 20 , Figure 20 The cutting channel forming apparatus 200 provided in this application embodiment. For example... Figure 20 As shown, the cutting channel forming apparatus 200 includes a memory 201 and a processor 202. The memory 201 stores a computer program, which is used by the processor 202 to execute the cutting channel forming method provided in any of the foregoing embodiments.

[0121] This application also provides a computer-readable storage medium storing a computer program for executing, upon invocation, the method for forming a cutting path provided in any of the foregoing embodiments.

[0122] It should be noted that, for the sake of simplicity, the aforementioned method embodiments are described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, because according to this application, some steps may be performed in other orders or simultaneously.

[0123] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0124] It should be understood that the application of this application is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A method for forming dicing paths, used to form dicing paths that define the dicing trajectory in the dicing of a wafer, wherein a plurality of chips are grown on the wafer, characterized in that, The method for forming the cutting channel includes: Obtain a layout drawing of the plurality of chips on the wafer. The layout drawing includes the layout information of the plurality of chips on the wafer. The layout information includes the layout information of the chips. The layout information defines the layout of the plurality of chips arranged in multiple rows. The multiple rows of chips are arranged at intervals along a first direction. Each row of chips includes at least one chip arranged at intervals along a second direction. The second direction is perpendicular to the first direction. Obtain the coordinate information of the multiple chips; Read the layout information from the layout drawing; Based on the read layout information and the coordinate information of the plurality of chips, a plurality of first inner dicing channels extending along the second direction are formed. These first inner dicing channels are located between every two adjacent rows of chips and extend to opposite ends of the wafer. Based on the read layout information and the coordinate information of the multiple chips, multiple second inner cutting channels extending along the first direction are formed, and the second inner cutting channels are located between adjacent chips in each row. The method further includes the following steps: Generating a layout drawing of the plurality of chips on the wafer includes: Obtain the length and width of the chip, the radius of the wafer, and the spacing between adjacent chips; The number of chips in the first row is determined, and the first row of chips is arranged from any end of the wafer along the second direction. The spacing between adjacent chips in the first row is equal, and the two ends of the first row of chips in the second direction are located at the two ends of the wafer. The distance between the side of the first row of chips away from the center of the wafer and the center of the wafer is greater than the difference between the wafer radius and the width of the chip. The number of chips in the second row is determined, and the second row of chips is arranged along a second direction on the side of the first row of chips closest to the center of the wafer. The spacing between adjacent chips in the second row is equal to the spacing between adjacent chips in the first row, and also equal to the spacing between the second row of chips and the first row of chips; and The chips are set up to the Nth row, where the alignment of all chips in each row is the same, and the number of chips in each row is the maximum number of chips that can be set in each row.

2. The method for forming a cutting channel as described in claim 1, characterized in that, The process of obtaining the coordinate information of the multiple chips includes: Using a preset position on the surface of the wafer where the multiple chips are arranged as the origin, the second direction as the horizontal axis, and the first direction as the vertical axis, a Cartesian coordinate system is established on the surface of the wafer. The coordinate values ​​of the endpoints of each chip in the Cartesian coordinate system are obtained. The coordinate values ​​of the endpoints include the horizontal coordinate value and the vertical coordinate value of the endpoints. The endpoints are the endpoints of the orthographic projection of each chip on the wafer.

3. The method for forming a cutting channel as described in claim 2, characterized in that, The method further includes: Based on the read arrangement information and the coordinate information of the multiple chips, a first edge dicing channel is formed extending along the second direction to the opposite ends of the wafer. The first edge dicing channel is located on opposite sides of the multiple rows of chips in the first direction.

4. The method for forming a cutting channel as described in claim 2, characterized in that, The method further includes: Based on the read arrangement information and the coordinate information of the multiple chips, multiple second edge cutting channels extending along the first direction are formed, and each second edge cutting channel is located on opposite sides of each row of chips in the second direction.

5. The method for forming a cutting channel as described in claim 2, characterized in that, The arrangement information also includes the spacing between two adjacent chips. The step of forming multiple first inner cutting channels extending along the second direction based on the read arrangement information and the coordinate information of the multiple chips includes: Based on the read layout information and the coordinate information of the multiple chips, a first inner cutting channel extending along the second direction is formed between each pair of adjacent rows of chips; The first inner dicing channel extending along the second direction is formed between each pair of adjacent rows of chips, further comprising: Select two adjacent rows of chips, including a first chip and a second chip respectively in a first direction, wherein the ordinate value of the endpoint of the first chip is greater than the ordinate value of the endpoint of the second chip, the first side of the first chip is close to the second side of the second chip, and the first chip and the second chip are any two adjacent chips in the two adjacent rows of chips in the first direction. Based on the coordinates of the endpoints on the first side and the distance between the first chip and the second chip, determine the coordinates of the first starting point of the first inner cutting channel. The x-coordinate of the first starting point is equal to the x-coordinate of the endpoints on the first side, and the y-coordinate of the first starting point is equal to the y-coordinate of the endpoints on the first side minus half the distance between the first chip and the second chip; or, Based on the coordinates of the endpoints on the second side and the distance between the first chip and the second chip, the coordinates of the first starting point of the first inner cutting channel are determined. The horizontal coordinate of the first starting point is equal to the horizontal coordinate of the endpoints on the second side, and the vertical coordinate of the first starting point is equal to the vertical coordinate of the endpoints on the second side plus half the distance between the first chip and the second chip. The first inner dicing channel is formed by extending from the first starting point along the second direction to the opposite ends of the wafer.

6. The method for forming a cutting channel as described in claim 2, characterized in that, The arrangement information also includes the spacing between two adjacent chips. The step of forming multiple second inner cutting channels extending along a first direction based on the read arrangement information and the coordinate information of the multiple chips includes: Based on the read arrangement information and the coordinate information of the multiple chips, a second inner cutting channel extending along the first direction is formed between every two adjacent chips in the second direction. Wherein, a second inner cleaving channel extending along the first direction is formed between every two adjacent chips in the second direction, further comprising: Select a third chip and a fourth chip that are adjacent in the second direction, wherein the x-coordinate value of the endpoint of the third chip is less than the x-coordinate value of the endpoint of the fourth chip, the third side of the third chip is close to the fourth side of the fourth chip, and the third chip and the fourth chip are any two chips that are directly opposite each other in the second direction. Based on the coordinates of the endpoints on the third side and the distance between the third and fourth chips, the coordinates of the second starting point of the second inner cutting channel are determined. The ordinate of the second starting point is equal to the ordinate of the endpoints on the third side, and the abscissa of the second starting point is equal to the abscissa of the endpoints on the third side plus half the distance between the third and fourth chips; or, Based on the coordinate values ​​of the endpoints on the fourth side and the distance between the third and fourth chips, the coordinate values ​​of the second starting point of the second inner cutting channel are determined. The vertical coordinate value of the second starting point is equal to the vertical coordinate value of the endpoints on the fourth side, and the horizontal coordinate value of the second starting point is equal to the horizontal coordinate value of the endpoints on the fourth side minus half the distance between the third and fourth chips. The second inner dicing channel is formed by extending from the second starting point along the first direction to the opposite ends of the wafer.

7. The method for forming a cutting channel as described in claim 6, characterized in that, The method further includes: When it is determined that at least one of the plurality of second inner dicing channels passes through at least one chip, and the ordinate value of the endpoint on the fifth side of the at least one chip is less than the ordinate value of the second starting point of the at least one second inner dicing channel, a first target portion of the at least one second inner dicing channel is removed to form at least one final second inner dicing channel. The first target portion of the at least one second inner dicing channel is the portion of the at least one second inner dicing channel whose ordinate value is less than the ordinate value of the first inner dicing channel located between the second starting point of the at least one second inner dicing channel and the fifth side. The fifth side is the side of the at least one chip closest to the second starting point of the at least one second inner dicing channel. Alternatively... When it is determined that at least one of the plurality of second inner dicing channels passes through at least one chip, and the ordinate value of the endpoint on the fifth side of the at least one chip is greater than the ordinate value of the second starting point of the at least one second inner dicing channel, the second target portion of the at least one second inner dicing channel is removed to form at least one final second inner dicing channel. The second target portion of the at least one second inner dicing channel is the portion of the at least one second inner dicing channel whose ordinate value is greater than the ordinate value of the first inner dicing channel located between the second starting point of the at least one second inner dicing channel and the fifth side. The fifth side is the side of the at least one chip that is close to the second starting point of the at least one second inner dicing channel.

8. The method for forming a cutting channel as described in claim 3, characterized in that, The step of forming a first edge dicing path extending along a second direction to opposite ends of the wafer based on the read arrangement information and the coordinate information of the plurality of chips includes: Identify the first row of edge chips and the second row of edge chips located at two opposite edges, wherein the ordinate value of the endpoint of the first row of edge chips is greater than the ordinate value of the second row of edge chips; Based on the coordinates of the endpoint of the first target chip in the first row of edge chips that is far from the wafer center, the coordinates of the third starting point of the first sub-edge dicing channel of the first edge dicing channel are determined. The first target chip is any chip in the first row of edge chips. The abscissa of the third starting point is equal to the abscissa of the endpoint of the first target chip that is far from the wafer center, and the ordinate of the third starting point is greater than the ordinate of the endpoint of the first target chip that is far from the wafer center. The first sub-edge dicing path is formed by extending from the third starting point along the second direction to the opposite ends of the wafer; Based on the coordinates of the endpoint of the second target chip in the second row of edge chips that is far from the wafer center, the coordinates of the fourth starting point of the second sub-edge dicing channel of the first edge dicing channel are determined. The second target chip is any chip in the second row of edge chips. The abscissa of the fourth starting point is equal to the abscissa of the endpoint of the second target chip that is far from the wafer center, and the ordinate of the fourth starting point is less than the ordinate of the endpoint of the second target chip that is far from the wafer center. The second sub-edge dicing path is formed by extending from the fourth starting point along the second direction to the opposite ends of the wafer.

9. The method for forming a cutting channel as described in claim 4, characterized in that, The step of forming multiple second edge cutting channels extending along a first direction based on the read arrangement information and the coordinate information of the multiple chips includes: Determine the first edge chip and the second edge chip on opposite sides of each row of chips in the second direction, wherein the x-coordinate value of the endpoint of the first edge chip is less than the x-coordinate value of the endpoint of the second edge chip. Based on the coordinate value of the endpoint of the first edge chip near the wafer edge, the coordinate value of the fifth starting point of the third sub-edge dicing channel of the second edge dicing channel is determined. The ordinate value of the fifth starting point is equal to the ordinate value of the endpoint of the first edge chip near the wafer edge, and the abscissa value of the fifth starting point is less than the abscissa value of the endpoint of the first edge chip near the wafer edge. The third sub-edge dicing path is formed by extending from the fifth starting point along the first direction to both ends of the wafer; Based on the coordinate value of the endpoint of the second edge chip near the wafer edge, the coordinate value of the sixth starting point of the fourth sub-edge dicing channel of the second edge dicing channel is determined. The ordinate value of the sixth starting point is equal to the ordinate value of the endpoint of the second edge chip near the wafer edge, and the abscissa value of the sixth starting point is greater than the abscissa value of the endpoint of the second edge chip near the wafer edge. The fourth sub-edge dicing path is formed by extending from the sixth starting point along the first direction to both ends of the wafer.

10. The method for forming a cutting channel as described in claim 9, characterized in that, The method further includes: When it is determined that at least one of the plurality of third sub-edge dicing channels passes through at least one chip, and the ordinate value of the endpoint of the sixth side of the at least one chip is less than the ordinate value of the fifth starting point of the at least one third sub-edge dicing channel, a third target portion of the at least one third sub-edge dicing channel is removed to form at least one final third sub-edge dicing channel. The third target portion is the portion of the at least one third sub-edge dicing channel whose ordinate value is less than the ordinate value of the first inner dicing channel located between the fifth starting point of the at least one third sub-edge dicing channel and the sixth side. The sixth side is the side of the at least one chip closest to the fifth starting point of the at least one third sub-edge dicing channel; or, When it is determined that at least one of the plurality of third sub-edge dicing channels passes through at least one chip, and the ordinate value of the endpoint of the sixth side of the at least one chip is greater than the ordinate value of the fifth starting point of the at least one third sub-edge dicing channel, a fourth target portion of the at least one third sub-edge dicing channel is removed to form at least one final third sub-edge dicing channel. The fourth target portion is the portion of the at least one third sub-edge dicing channel whose ordinate value is greater than the ordinate value of the first inner dicing channel located between the fifth starting point of the at least one third sub-edge dicing channel and the sixth side. The sixth side is the side of the at least one chip that is close to the fifth starting point of the at least one third sub-edge dicing channel.

11. The method for forming a cutting channel as described in claim 1, characterized in that, Determining the number of chips in the second row includes: When the length direction of the second row of chips is parallel to the second direction, according to the first formula... The number of chips in the second row, X2, is calculated, where X2 is the integer part of X1, R is the wafer radius, P is the number of chips in the first row, L is the chip length, W is the chip width, and G is the spacing between adjacent chips. When the length direction of the second row of chips is parallel to the first direction, according to the second formula... The number of chips in the second row is calculated to be X4, where X4 is the integer part of X3, R is the wafer radius, P is the number of chips in the first row, L is the chip length, W is the chip width, and G is the spacing between adjacent chips.

12. A cutting track forming apparatus, characterized in that, The cutting channel forming apparatus includes a memory and a processor, the memory storing a computer program, the computer program being invoked by the processor to execute the method as described in any one of claims 1-11.

13. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when invoked, performs the method as described in any one of claims 1-11.

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