Test structure, test method and wafer for improving test reproducibility of ga n devices

Abstract

A test structure, test method, and wafer for GaN devices to improve test reproducibility, belonging to the field of semiconductor technology, includes two rectangular source structures, multiple composite structures, and multiple devices under test (DUTs). On a horizontal plane, the two source structures are located on the left and right sides of the test structure, respectively. The multiple composite structures and multiple DUTs are located between the two source structures, and are spaced apart and arranged sequentially. Each composite structure includes a drain structure, a first gate structure disposed on the upper side of the composite structure, and a second gate structure disposed on the lower side of the composite structure. At least three sides of each DUT are surrounded by the source structures or the gate structures. Therefore, a preset voltage of a preset duration can be applied between the gate structures and the source structures to bring the traps at the bottom of each DUT to a stable state of saturated charging for acceptance testing, thereby improving the reproducibility and accuracy of the acceptance test results.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and in particular relates to a test structure, test method and wafer for GaN devices that improve test reproducibility. Background Technology

[0002] The devices on a gallium nitride (GaN) wafer are interconnected, and the epitaxial layer contains numerous traps that capture electrons and holes, causing electrical changes. Therefore, the reproducibility of test results is very low. For example, a device on the lower left of the wafer might directly charge a trap at the bottom of a device on the upper right when a high voltage is applied. Wafer acceptance testing often requires placing many test devices on the dicing trace, leading to problems with non-reproducible and low-accuracy test results during acceptance testing.

[0003] The current common solution is to place all devices under test in the same area and then use isolation technology to prevent testing in this area from affecting other devices. However, this method has the following side effects:

[0004] 1) The location of the acceptance test is too far from the device to truly reflect the impact of the process;

[0005] 2) The devices in the test area affect each other, making the test results unreliable.

[0006] Therefore, there is an urgent need to propose a test structure and test method for GaN devices to improve test reproducibility, so as to improve the reproducibility and accuracy of the test results of acceptance testing. Summary of the Invention

[0007] The purpose of this application is to provide a test structure, test method, and wafer for GaN devices that improve test reproducibility, aiming to solve the problem that the existing test structures and test methods for GaN devices that improve test reproducibility cannot improve the reproducibility and accuracy of the test results of the acceptance test, and reduce production costs.

[0008] This application provides a test structure for GaN devices to improve test reproducibility, including two source structures, multiple composite structures, and multiple devices under test, all of which are rectangular.

[0009] On a horizontal plane, the two source structures are located on the left and right sides of the test structure, respectively. Multiple composite structures and multiple devices under test are located between the two source structures. The multiple composite structures and multiple devices under test are spaced apart and arranged sequentially. The composite structure includes a drain structure, a first gate structure disposed on the upper side of the composite structure, and a second gate structure disposed on the lower side of the composite structure. The device under test is surrounded by the source structure or the gate structure on at least three sides.

[0010] In one embodiment, it further includes:

[0011] A third gate structure located on the upper side of the test structure in a horizontal plane;

[0012] A fourth gate structure located below the test structure on a horizontal plane;

[0013] In one embodiment, on a longitudinal section, the source structure includes a first metal region disposed on the upper surface of the GaN wafer; the drain structure includes a second metal region disposed on the upper surface of the GaN wafer; and the gate structure includes an insulating region and a third metal region; wherein the insulating region is disposed on the upper surface of the GaN wafer, and the third metal region is disposed on the upper surface of the insulating region.

[0014] In one embodiment, the GaN wafer includes:

[0015] Substrate;

[0016] The epitaxial layer located on the upper surface of the substrate;

[0017] A barrier layer located on the upper surface of the epitaxial layer.

[0018] In one embodiment, the drain structure is located between the first gate structure and the second gate structure.

[0019] In one embodiment, the test structure is located in the dicing channel of the GaN wafer.

[0020] This application also provides a testing method for GaN devices to improve test reproducibility. Based on the structure of the GaN device described above for improving test reproducibility, the testing method includes:

[0021] A preset voltage of a preset duration is applied between the gate structure and the source structure;

[0022] An acceptance test is performed on multiple of the devices under test to obtain a first test result;

[0023] The first test result is used as the test result of the semiconductor device; wherein the semiconductor device is located next to the cut channel where the test structure is located.

[0024] In one embodiment, after applying a preset voltage for a preset duration between the gate structure and the two source structures, the method further includes:

[0025] A test voltage is applied between the drain structure and the two source structures to detect the leakage current;

[0026] Defect parameters are obtained based on leakage current;

[0027] In one embodiment, after performing acceptance testing on the plurality of said devices under test to obtain a first test result, the method further includes:

[0028] The first test result is corrected according to the defect parameters to obtain the corrected first test result;

[0029] The specific meaning of using the first test result as the test result of the semiconductor device is as follows:

[0030] The corrected first test result is used as the test result of the semiconductor device.

[0031] This application also provides a wafer comprising the above-described test structure for GaN devices that improves test reproducibility.

[0032] The beneficial effects of this invention compared to the prior art are as follows: It includes two rectangular source structures, multiple composite structures, and multiple devices under test (DUTs). On a horizontal plane, the two source structures are located on the left and right sides of the test structure, respectively, while the multiple composite structures and DUTs are located between the two source structures. These composite structures and DUTs are spaced apart and arranged sequentially. Each composite structure includes a drain structure, a first gate structure disposed on the upper side of the composite structure, and a second gate structure disposed on the lower side of the composite structure. At least three sides of each DUT are surrounded by either the source structure or the gate structure. Therefore, a preset voltage of a preset duration can be applied between the gate structure and the source structure to bring the traps at the bottom of each DUT to a stable state of saturated charging. Acceptance testing is then performed when each DUT is in a stable state, thereby improving the reproducibility and accuracy of the acceptance test results. Attached Figure Description

[0033] To more clearly illustrate the technical inventions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 A schematic diagram of a test structure for a GaN device to improve test reproducibility, provided in an embodiment of this application;

[0035] Figure 2 This is a schematic diagram of another test structure for a GaN device to improve test reproducibility, provided in an embodiment of this application.

[0036] Figure 3 for Figure 1The structure of the GaN device shown for improving test reproducibility is a cross-sectional view along the AA' plane.

[0037] Figure 4 This is a voltage-time diagram illustrating the test method for improving test reproducibility of GaN devices provided in the embodiments of this application. Detailed Implementation

[0038] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0039] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0040] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0041] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0042] Figure 1 The block structure of the GaN device for improving test reproducibility provided by an embodiment of the present invention is shown. For ease of explanation, only the parts related to the embodiment of the present invention are shown, and are described in detail below:

[0043] The test structure for GaN devices that improves test reproducibility includes two rectangular source structures 10, multiple composite structures 80, and multiple devices under test 90.

[0044] On the horizontal plane, two source structures 10 are located on the left and right sides of the test structure, respectively. Multiple composite structures 80 and multiple devices under test 90 are located between the two source structures 10. The multiple composite structures 80 and multiple devices under test 90 are spaced apart and arranged in sequence. The composite structure 80 includes a drain structure 20, a first gate structure 30 disposed on the upper side of the composite structure 80, and a second gate structure 40 disposed on the lower side of the composite structure 80. The device under test 90 is surrounded by the source structure 10 or the gate structure on at least three sides.

[0045] Since the device under test 90 is surrounded by the source structure 10 or the gate structure on at least three sides, when a preset voltage is applied between the source structure 10 and the gate structure, it can be ensured that each trap of the epitaxial layer 130 of the device under test 90 can be charged, thereby improving the reproducibility and accuracy of the test results in the subsequent acceptance test.

[0046] like Figure 2 As shown, the test structure for GaN devices that improves test reproducibility also includes a third gate structure 50 and a fourth gate structure 60.

[0047] The third gate structure 50 is located on the upper side of the test structure in the horizontal plane; the fourth gate structure 60 is located on the lower side of the test structure in the horizontal plane.

[0048] By setting the third gate structure 50 and the fourth gate structure 60, all four sides of the device under test 90 are surrounded by the source structure 10 or the gate structure, thereby improving the uniformity of trap charging at the bottom of each device under test 90 and further improving the reproducibility and accuracy of the acceptance test results.

[0049] like Figure 3 As shown, in the longitudinal section, the source structure 10 includes a first metal region disposed on the upper surface of the GaN wafer; the drain structure 20 includes a second metal region disposed on the upper surface of the GaN wafer; the gate structure includes an insulating region 31 and a third metal region 32; wherein, the insulating region 31 is disposed on the upper surface of the GaN wafer, and the third metal region 32 is disposed on the upper surface of the insulating region 31.

[0050] The insulating region 31 can be made of P-type GaN, and the metal region can be made of gold or palladium.

[0051] The aforementioned source structure 10, drain structure 20, and gate structure have the advantages of simple and reliable structure.

[0052] It should be noted that, as Figure 3 As shown, the GaN wafer includes a substrate 110, an epitaxial layer 130, and a barrier layer 140.

[0053] Epitaxial layer 130 is located on the upper surface of substrate 110; barrier layer 140 is located on the upper surface of epitaxial layer 130.

[0054] The epitaxial layer 130 can be made of N-type GaN, and the barrier layer 140 can be made of AlGaN. It is understood that a buffer layer 120 can also be disposed between the substrate 110 and the epitaxial layer 130.

[0055] Insulating region 31 and third metal region 32 form a Schottky contact; thus, applying a preset voltage between the gate structure and source structure 10 overcomes the Schottky barrier to charge the traps within epitaxial layer 130. Second metal region forms an ohmic contact with barrier layer 140; used to measure leakage current to detect the number of charged traps in epitaxial layer 130. First metal region forms an ohmic contact with barrier layer 140; used for grounding as a reference voltage.

[0056] By way of example and not limitation, the drain structure 20 is located between the first gate structure 30 and the second gate structure 40. Therefore, when a test voltage is applied between the drain structure 20 and the two source structures 10, the accuracy of leakage current detection is improved.

[0057] Understandably, the test structure can be located in the dicing channel of the GaN wafer.

[0058] By utilizing the dicing channel to place the test structure, more wafer area is saved, reducing production costs.

[0059] Corresponding to an embodiment of a test structure for GaN devices that improves test reproducibility, the present invention also provides an embodiment of a test method for GaN devices that improves test reproducibility.

[0060] A testing method for GaN devices to improve test reproducibility, the method comprising steps 401 to 406.

[0061] In step 401, a preset voltage of a preset duration is applied between the gate structure and the source structure.

[0062] Through step 401, the traps at the bottom of each device under test reach a stable state of charging saturation, ensuring that the trap state of the epitaxial layer under each device under test on the wafer is the same, so as to eliminate the influence of traps on electrical performance and further ensure the reproducibility of each device under test test.

[0063] In step 402, acceptance tests are performed on multiple devices under test to obtain the first test result;

[0064] Step 402 involves performing acceptance testing when each device under test is in a stable state, thereby improving the reproducibility and accuracy of the acceptance test results.

[0065] In step 403, the first test result is used as the test result of the semiconductor device; wherein the semiconductor device is located next to the dicing channel where the test structure is located.

[0066] Step 403 yields the test results of the acceptance test for the corresponding product (semiconductor device).

[0067] Corresponding to a structural embodiment of a GaN device for improving test reproducibility, the present invention also provides another embodiment of a test method for GaN devices for improving test reproducibility.

[0068] A testing method for GaN devices to improve test reproducibility, the method comprising steps 501 to 506.

[0069] In step 501, a preset voltage of a preset duration is applied between the gate structure and the source structure;

[0070] The traps in the device under test are charged based on a preset duration and a preset voltage. Since the charging state of the traps is fixed under the same charging conditions, the charging state of the traps can be fixed by continuously applying a preset voltage for a preset duration between the gate structure and the source structure.

[0071] The number of cycles in the second measurement cycle can be set according to actual needs and is not limited here.

[0072] In step 502, a test voltage is applied between the drain structure and the two source structures to detect the leakage current;

[0073] In step 503, defect parameters are obtained based on the leakage current;

[0074] In this embodiment of the application, after the charging state of the trap is fixed, the leakage current of the device under test caused by the trap is measured, thereby obtaining the value of the defect parameter of the device under test.

[0075] In step 504, acceptance tests are performed on multiple devices under test to obtain the first test result;

[0076] In step 505, the first test result is corrected according to the defect parameters to obtain the corrected first test result;

[0077] In step 506, the corrected first test result is used as the test result of the semiconductor device.

[0078] Since the test results of semiconductor devices are corrected for the defect parameters of the device under test, the accuracy of the acceptance test results is improved.

[0079] In practical implementation, the timing diagram of the testing method for GaN devices to improve test reproducibility is as follows: Figure 4As shown. From time t0 to t1, step 501 is executed, applying a preset voltage VGSQ for a preset duration between the gate and source structures. Electrons and holes flow from the gate structure into traps within the epitaxial layer. From time t1 to t2, the preset voltage VGS is turned off, and the test voltage VDS transitions to the loaded state. From time t2 to t3, the steady-state time for the test voltage VDS is applied, during which leakage current on the drain structure can be detected. From time t3 to t4, the preset voltage VGS is applied, and the test voltage VDS is turned off. Acceptance testing of the device under test can be performed after time t4.

[0080] This invention comprises two rectangular source structures, multiple composite structures, and multiple devices under test (DUTs). On a horizontal plane, the two source structures are located on the left and right sides of the test structure, respectively. The multiple composite structures and DUTs are located between the two source structures, spaced apart and arranged sequentially. Each composite structure includes a drain structure, a first gate structure disposed on the upper side of the composite structure, and a second gate structure disposed on the lower side of the composite structure. At least three sides of each DUT are surrounded by either the source structure or the gate structure. Therefore, a preset voltage of a preset duration can be applied between the gate structure and the source structure to bring the traps at the bottom of each DUT to a stable state of saturated charging. Acceptance testing is then performed when each DUT is in a stable state, thereby improving the reproducibility and accuracy of the acceptance test results.

[0081] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0082] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A test structure for GaN devices to improve test reproducibility, characterized in that, It includes two source structures, both of which are rectangular, multiple composite structures, and multiple devices under test; On a horizontal plane, the two source structures are located on the left and right sides of the test structure, respectively. A plurality of composite structures and a plurality of devices under test are located between the two source structures. The plurality of composite structures and the plurality of devices under test are spaced apart and arranged sequentially. The composite structure includes a drain structure, a first gate structure disposed on the upper side of the composite structure, and a second gate structure disposed on the lower side of the composite structure. The device under test is surrounded by at least one of the first gate structure and the second gate structure and the two source structures on at least three sides. In a longitudinal section, the source structure includes a first metal region disposed on the upper surface of the GaN wafer; The GaN wafer includes an epitaxial layer.

2. The test structure for improving test reproducibility of GaN devices as described in claim 1, characterized in that, Also includes: A third gate structure located on the upper side of the test structure in a horizontal plane; The fourth gate structure is located on the horizontal plane below the test structure.

3. The test structure for improving test reproducibility of GaN devices as described in claim 2, characterized in that, In a longitudinal section, the drain structure includes a second metal region disposed on the upper surface of the GaN wafer.

4. The test structure for improving test reproducibility of GaN devices as described in claim 3, characterized in that, The GaN wafer includes: Substrate; The epitaxial layer located on the upper surface of the substrate; A barrier layer located on the upper surface of the epitaxial layer.

5. The test structure for improving test reproducibility of GaN devices as described in claim 1, characterized in that, The drain structure is located between the first gate structure and the second gate structure.

6. The test structure for improving test reproducibility of GaN devices as described in claim 1, characterized in that, The test structure is located in the dicing channel of the GaN wafer.

7. A testing method for GaN devices to improve test reproducibility, characterized in that, Based on the test structure of the GaN device for improving test reproducibility as described in any one of claims 1 to 6, the test method includes: A preset voltage for a preset duration is applied between the gate structure and the source structure to make the traps at the bottom of each device under test reach a stable state of charging saturation. An acceptance test is performed on multiple of the devices under test to obtain a first test result; The first test result is used as the test result of the semiconductor device; wherein the semiconductor device is located next to the cut channel where the test structure is located.

8. The testing method for GaN devices with improved test reproducibility according to claim 7, characterized in that, The process of applying a preset voltage for a preset duration between the gate structure and the source structure further includes: A test voltage is applied between the drain structure and the two source structures to detect the leakage current; Defect parameters are obtained based on leakage current.

9. The testing method for GaN devices with improved test reproducibility according to claim 8, characterized in that, After performing acceptance testing on the multiple devices under test to obtain the first test result, the method further includes: The first test result is corrected according to the defect parameters to obtain the corrected first test result; The specific meaning of using the first test result as the test result of the semiconductor device is as follows: The corrected first test result is used as the test result of the semiconductor device.

10. A wafer, characterized in that, The wafer includes a test structure for GaN devices that improve test reproducibility as described in any one of claims 1 to 6.

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