A preparation method of a novel InGaAs short-wave infrared detector

Abstract

The application belongs to InGaAs infrared focal plane detector, and provides a preparation method of a new type of InGaAs short-wave infrared detector. After growing P electrode, N electrode, P type metal and N type metal to form ohmic contact, growing connecting layer metal, thinning and polishing InP substrate to form a flat mirror surface, corresponding photoetching on a readout circuit wafer, growing lower electrode metal and indium column, and then carrying out metal stripping; InP epitaxial wafer PDA and readout circuit are uniformly glued, protected, and diced to form independent single; PDA and readout circuit are inversely interconnected to form an infrared detector, and secondary polishing treatment and growth of anti-reflection coating are carried out. The indium column is grown at the end of the readout circuit, and one-step photoetching can be completed. The PDA chip end can reduce the growth of the lower electrode, the growth of the indium column, and the growth of the corresponding passivation layer and the opening of the passivation layer. The process steps are reduced, the probability of defects is reduced, the production cost is reduced, and the final yield of the product is further improved.

Description

Technical Field

[0001] This invention pertains to InGaAs infrared focal plane array detectors, specifically providing a novel method for fabricating InGaAs short-wave infrared detectors. Background Technology

[0002] Generally, the fabrication method of InGaAs infrared detectors is as follows: after passivation, photolithography, diffusion, and electrode fabrication on an InGaAs epitaxial wafer, the fabricated diode array (PDA) and the corresponding readout circuit are flip-chip interconnected to fabricate an infrared focal plane detector.

[0003] The invention patent with application number 202010937303.1, entitled "A Novel Fabrication Process for InGaAs Infrared Focal Plane Detector", discloses a novel fabrication process for an InGaAs infrared focal plane detector. In order to increase the absorption efficiency of infrared light, a Ti / Au reflective layer is added between the pixels. This prevents infrared light that is not absorbed by the InGaAs absorption layer from penetrating the chip and illuminating the readout circuit. Instead, the infrared light is reflected back after passing through the Ti / Au reflective layer and is absorbed a second time by the InGaAs absorption layer. This improves the light absorption rate of the device and thus improves the detection efficiency of the chip.

[0004] However, the method mentioned in the patent involves multiple photolithography openings, and each photolithography may introduce new defects, leading to a decrease in the final chip yield. Therefore, the fabrication method needs to be optimized. Summary of the Invention

[0005] To address the problem that each step in the fabrication process of InGaAs infrared detectors may introduce new defects, leading to a decrease in chip yield, this invention provides a novel method for fabricating InGaAs short-wave infrared detectors.

[0006] This invention is achieved by the following technical solution: a novel method for fabricating an InGaAs short-wave infrared detector, comprising: growing P-electrodes and N-electrodes; forming ohmic contacts between P-type and N-type metals; growing a connecting layer metal; thinning and polishing the InP substrate to form a flat mirror surface; performing photolithography on the corresponding readout circuit wafer; growing the lower electrode metal and indium pillars; and then performing metal lift-off. The InP epitaxial wafer PDA and readout circuit are coated with a homopolymer, diced, and cleaved into independent units. The PDA and readout circuit are inverted and interconnected to form an infrared detector, which is then polished a second time and an anti-reflective coating is grown.

[0007] Furthermore, the specific steps include the following: Step 1: Using MOCVD, sequentially grow an N-type InP metal contact layer and an In absorption layer on an InP substrate. 0.53 Ga0.47 As, N-type InP as the top layer, and InGaAs as the sacrificial layer are used to obtain an InGaAs epitaxial wafer; Step 2: Remove the sacrificial layer on the surface of the InGaAs epitaxial wafer and grow a silicon nitride passivation layer; Step 3: Photolithography to create holes, dry etching of the first layer of silicon nitride, and zinc diffusion within the etched holes to form P-type doping; Step 4: Deposit the second layer of silicon nitride, perform photolithography to create openings on the silicon nitride, etch to form ohmic holes, and grow P electrodes; Step 5: Photolithography, dry etching of silicon nitride, wet etching of the N-type InP cap layer and the In absorption layer. 0.53 Ga 0.47 As, grow the N-electrode; Step 6: Anneal the P-type and N-type metals to form an ohmic contact between them; Step 7: Growing the bonding layer metal; Step 8: Perform the first thinning and polishing on the InP substrate to form a flat mirror surface; Step 9: Perform photolithography on the corresponding readout circuit wafer, then grow the lower electrode metal and indium pillars, and then perform metal stripping; Step 10: The InP epitaxial wafer PDA and readout circuit that have completed the corresponding process are coated with a homogeneous adhesive for protection, then diced on a dicing machine, and finally separated into individual wafers. Step 11: The PDA and readout circuit are interconnected in reverse to form an infrared detector; Step 12: Perform a second polishing process on the infrared detector completed in the previous step, and grow an anti-reflective coating.

[0008] This invention grows indium pillars at the readout circuit end, requiring only one step of photolithography and metal deposition. If the indium pillars were grown at the InP epitaxial end, additional process steps would be needed, including: photolithography and deposition of the lower electrode metal; passivation layer deposition, photolithography, and etching; and photolithography and deposition of the indium pillars. Each process step has a probability of generating defects; the more steps there are, the greater the cumulative probability of defects. Reducing the number of process steps effectively lowers the probability of defects, reduces production costs, and further improves the final product yield. Attached Figure Description

[0009] Figure 1 This is a cross-sectional view of the InGaAS epitaxial wafer structure described in this invention; Figure 2 This is a schematic diagram of the second step of growing the silicon nitride passivation layer; Figure 3 This is a schematic diagram after the first layer of silicon nitride has been etched. Figure 4 This is a schematic diagram after the growth of the P electrode; Figure 5 This is a schematic diagram after the N-electrode has been grown. Figure 6This is a schematic diagram after the growth of the metal bonding layer; Figure 7 A schematic diagram of thinning and polishing an InP substrate in one step to form a flat mirror surface; Figure 8 This is a schematic diagram of the readout circuit after the growth of the lower electrode metal and indium pillars. Figure 9 A schematic diagram showing the inverted interconnection of the PDA and the readout circuit to create an infrared detector; Figure 10 This is a schematic diagram after the anti-reflective coating has been grown; 1-InP substrate; 2-N-type InP metal contact layer; 3-Absorber layer In 0.53 Ga 0.47 As; 4-N-type InP cap layer; 5-Sacrificial InGaAs layer; 6-Silicon nitride passivation layer; 7-Photolithographic opening; 8-P-type doping; 9-P electrode; 10-N electrode; 11-Connecting layer metal; 12-First thinning of InP substrate; Figure 11 The figures show the response rate test results of detectors prepared using the process method of this invention and detectors prepared using the original process method under the same test conditions; in the figures: Series 1 is the detector prepared using the process method of this invention, and Series 2 is the detector prepared using the original process method. Figure 12 The figures show the quantum efficiency test results of detectors prepared using the process method of this invention and detectors prepared using the original process method under the same test conditions; in the figures: Series 1 is the detector prepared using the process method of this invention, and Series 2 is the detector prepared using the original process method. Figure 13 The figures show the pixel goodness rate test results of detectors prepared using the process method of this invention and detectors prepared using the original process method under the same test conditions; in the figures: Series 1 is the detector prepared using the process method of this invention, and Series 2 is the detector prepared using the original process method. Figure 14 The figures show the dark current test results of detectors prepared using the process method of this invention and detectors prepared using the original process method under the same test conditions; in the figures: Series 1 is the detector prepared using the process method of this invention, and Series 2 is the detector prepared using the original process method. Detailed Implementation

[0010] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0011] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains, and all materials publicly cited herein and cited by them are incorporated herein by reference.

[0012] Equivalent technologies of the specific embodiments described herein that are readily apparent to those skilled in the art through routine experimentation are included in this application.

[0013] Unless otherwise specified, the experimental methods used in the following examples are conventional methods. Unless otherwise specified, the instruments and equipment used in the following examples are all standard laboratory instruments and equipment; unless otherwise specified, the experimental materials used in the following examples were all purchased from regular biochemical reagent stores.

[0014] Example 1: A novel method for fabricating an InGaAs short-wave infrared detector, comprising the following steps: Step 1: As Figure 1 As shown, an N-type InP metal contact layer 2 and an absorption layer In are sequentially grown on an InP substrate 1 using MOCVD. 0.53 Ga 0.47 As 3, N-type InP 4, sacrificial InGaAs 5, to obtain an InGaAs epitaxial wafer.

[0015] Step 2: As Figure 2 As shown, the sacrificial layer 5 on the surface of the InGaAs epitaxial wafer is removed, and a silicon nitride passivation layer 6 is grown.

[0016] Step 3: As Figure 3 As shown, photolithography creates an opening 7, dry etching is used to etch the first layer of silicon nitride, and zinc diffusion is performed inside the etched hole to form a P-type doped layer 8.

[0017] Step 4: As Figure 4 As shown, a second layer of silicon nitride is deposited, and photolithography is performed on the silicon nitride to create ohmic holes, and a P electrode 9 is grown.

[0018] Step 5: As Figure 5 As shown, photolithography, dry etching of silicon nitride, and wet etching of the N-type InP cap layer and the In absorption layer are performed. 0.53 Ga 0.47 As, grow N electrode 10.

[0019] Step 6: Anneal the P-type and N-type metals to form an ohmic contact between them.

[0020] Step 7: As Figure 6 As shown, the growth bonding layer metal 11 is grown.

[0021] Step 8: As Figure 7As shown, the InP substrate is first thinned by 12 mm and polished to form a flat mirror surface.

[0022] Step 9: As Figure 8 As shown, photolithography is performed on the corresponding readout circuit wafer, then the lower electrode metal and indium pillars are grown, and then the metal is stripped off.

[0023] Step 10: Apply a top coat of adhesive to the InP epitaxial wafer (PDA) and readout circuit after the corresponding processes are completed. Divide the wafer on a dicing machine and finally separate it into individual wafers.

[0024] Step 11: As Figure 9 As shown, the PDA and the readout circuit are interconnected in reverse to form an infrared detector.

[0025] Step 12: As Figure 10 As shown, the infrared detector completed in the previous step is subjected to a second polishing process to grow an anti-reflective coating.

[0026] Figures 11-14 The figures show the data obtained by testing detectors prepared using the process method of this invention and detectors prepared using the original process method under the same test conditions. In the figures, series 1 is the detector prepared using the process method of this invention, and series 2 is the detector prepared using the original process method.

[0027] It can be observed that the pixel goodness rate is more stable after adopting the new process method, and it is even higher than that of detectors fabricated using the previous process method. The responsivity and quantum efficiency are also improved compared to before. The overall dark current level is also lower than before.

[0028] For short-wave infrared detectors, lower dark current leads to higher responsivity, quantum efficiency, and good pixel ratio, resulting in better performance. Therefore, the method described in this invention effectively improves the performance of the fabricated short-wave infrared detector.

[0029] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A novel method for fabricating an InGaAs short-wave infrared detector, characterized in that: After growing P-electrodes and N-electrodes, forming ohmic contacts between P-type and N-type metals, growing a bonding layer metal, and thinning and polishing the InP substrate to form a flat mirror surface, photolithography is performed on the corresponding readout circuit wafer, and the lower electrode metal and indium pillars are grown and then the metal is lifted off. The InP epitaxial wafer PDA and readout circuit are coated with a homopolymer for protection, diced, and cleaved into individual units. The PDA and readout circuit are inverted and interconnected to form an infrared detector, which is then polished a second time and an anti-reflective coating is grown.

2. The preparation method according to claim 1, characterized in that: Specifically, the steps include the following: Step 1: Using MOCVD, sequentially grow an N-type InP metal contact layer and an In absorption layer on an InP substrate. 0.53 Ga 0.47 As, N-type InP as the top layer, and InGaAs as the sacrificial layer are used to obtain an InGaAs epitaxial wafer; Step 2: Remove the sacrificial layer on the surface of the InGaAs epitaxial wafer and grow a silicon nitride passivation layer; Step 3: Photolithography to create holes, dry etching of the first layer of silicon nitride, and zinc diffusion within the etched holes to form P-type doping; Step 4: Deposit the second layer of silicon nitride, perform photolithography to create openings on the silicon nitride, etch to form ohmic holes, and grow P electrodes; Step 5: Photolithography, dry etching of silicon nitride, wet etching of the N-type InP cap layer and the In absorption layer. 0.53 Ga 0.47 As, grow the N-electrode; Step 6: Anneal the P-type and N-type metals to form an ohmic contact between them; Step 7: Growing the bonding layer metal; Step 8: Perform the first thinning and polishing on the InP substrate to form a flat mirror surface; Step 9: Perform photolithography on the corresponding readout circuit wafer, then grow the lower electrode metal and indium pillars, and then perform metal stripping; Step 10: The InP epitaxial wafer PDA and readout circuit that have completed the corresponding process are coated with a homogeneous adhesive for protection, then diced on a dicing machine, and finally separated into individual wafers. Step 11: The PDA and readout circuit are interconnected in reverse to form an infrared detector; Step 12: Perform a second polishing process on the infrared detector completed in the previous step, and grow an anti-reflective coating.

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