A light-emitting diode and a light-emitting device

Abstract

This invention relates to the field of semiconductor manufacturing technology, and particularly to a light-emitting diode (LED), comprising a semiconductor stack, a first electrode, and a second electrode. The semiconductor stack has a mesa, sidewalls, and opposing lower and upper surfaces. From the lower to the upper surface, the semiconductor stack sequentially includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer. The mesa is on the same side as the upper surface of the semiconductor stack. The sidewalls are the sides connecting the upper surface and the mesa. The first electrode is electrically connected to the first semiconductor layer, and the second electrode is electrically connected to the second semiconductor layer. The mesa has a groove extending into the first semiconductor layer. The first electrode has a first sidewall near the sidewall, which is at least partially disposed within the groove. The groove design allows for layered adjustment of the current flow, reducing current congestion and thus increasing current spread, effectively improving the carrier injection efficiency of the LED.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a light-emitting diode and a light-emitting device. Background Technology

[0002] A light-emitting diode (LED) is a semiconductor light-emitting element, typically made of semiconductors such as GaN, GaAs, GaP, and GaAsP. Its core is a PN junction that emits light. LEDs possess advantages such as high luminous intensity, high efficiency, small size, and long lifespan, and are considered one of the most promising light sources available today. LEDs are widely used in lighting, monitoring and command systems, high-definition broadcasting, high-end cinemas, office displays, interactive conferencing, virtual reality, and other fields.

[0003] In recent years, the immense application value of ultraviolet (UV) LEDs, especially deep UV LEDs, has attracted significant attention and become a new research hotspot. The light extraction efficiency of deep UV LEDs is of paramount importance. Compared to the epitaxy of blue LEDs, UV LEDs utilize Al-containing group III nitride semiconductor materials. However, Al-containing nitride semiconductors have high resistivity, leading to low carrier injection efficiency when used in n-type semiconductor layers. From the chip's light emission distribution, current congestion is particularly prone to occur at electrode corners. Summary of the Invention

[0004] This invention proposes a light-emitting diode and a light-emitting device, one of the objectives of which is to provide a chip structure for layered current conduction, thereby reducing the current congestion effect by adjusting the current flow through layering, thus effectively improving the carrier injection efficiency of the light-emitting diode.

[0005] In some embodiments, the present invention provides a light-emitting diode, comprising:

[0006] A semiconductor stack has a mesa, sidewalls, and opposing lower and upper surfaces. The semiconductor stack, from the lower surface to the upper surface, sequentially includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer. The mesa is on the same side as the upper surface of the semiconductor stack, and the sidewalls are the sides connecting the upper surface and the mesa.

[0007] The first electrode is electrically connected to the first semiconductor layer.

[0008] The second electrode is electrically connected to the second semiconductor layer.

[0009] The mesa has a groove that extends into the first semiconductor layer.

[0010] The first electrode has a first sidewall near the sidewall, which is at least partially disposed within the groove.

[0011] In some embodiments, the grooves are continuously distributed or discontinuously distributed.

[0012] In some embodiments, the groove has a second sidewall away from the first sidewall, and the distance between the first sidewall and the second sidewall is less than the cross-sectional width of the first electrode.

[0013] In some embodiments, the groove has a third sidewall opposite to the second sidewall, the third sidewall being located between the sidewall and the second sidewall; in other embodiments, the third sidewall may be directly connected to the sidewall.

[0014] In some embodiments, the third sidewall has a minimum distance from the sidewall.

[0015] In some embodiments, the third sidewall has a minimum distance from the first sidewall.

[0016] In some embodiments, the distance from the bottom of the groove to the lower surface of the semiconductor stack is 1 / 5 to 1 / 2 of the thickness of the first semiconductor layer.

[0017] In some embodiments, the groove extends from the mesa into the first semiconductor layer by a distance greater than 100 nm.

[0018] In some embodiments, when viewed from above the light-emitting diode toward the semiconductor stack, the first electrode and the groove have an overlapping portion, and the projected area of ​​the overlapping portion is 5%-70% of the projected area of ​​the first electrode.

[0019] In some embodiments, when viewed from above the light-emitting diode toward the semiconductor stack, the area of ​​the recess occupies 5% to 60% of the area of ​​the mesa.

[0020] In some embodiments, when viewed from above the light-emitting diode toward the semiconductor stack, the groove opening shape includes square, circular, and elliptical.

[0021] In some embodiments, the width of the opening of the groove on the tabletop is 1~50μm.

[0022] In some embodiments, the size of the groove on the countertop is larger than the size of the bottom of the groove.

[0023] In some embodiments, the groove has a trapezoidal cross-sectional shape and the inclination angle of the groove is less than 90 degrees.

[0024] In some embodiments, the spacing between the grooves is uniformly distributed or gradually distributed.

[0025] In some embodiments, the first electrode and the second electrode have corners, and a groove is provided near the corner.

[0026] In some embodiments, the spacing between the grooves is gradually increased as the distance from the corner position increases.

[0027] In some embodiments, the grooves are spaced 1 to 40 μm apart near the corner.

[0028] In some embodiments, the grooves are spaced 5 to 100 μm apart near the corner.

[0029] In some embodiments, the first electrode is a strip structure.

[0030] The present invention also provides a light-emitting device, which employs the light-emitting diode provided in any of the above embodiments.

[0031] Compared with the prior art, one of the beneficial effects of the present invention is as follows:

[0032] This invention provides a layered current conduction chip structure. This structure, by setting intermittently distributed grooves, with some first electrodes placed within the grooves and others not, achieves layered adjustment of current flow, reducing current congestion and thus increasing current spread. This results in lower voltage and improved brightness. The layered current conduction structure can be concentrated at electrode corners, effectively solving the current congestion problem that easily occurs at these locations, thereby significantly improving the carrier injection efficiency of the light-emitting diode.

[0033] Other features and advantages of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the invention. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a top view schematic diagram of the structure of a light-emitting diode provided in an embodiment of the present invention.

[0036] Figure 2A This is a longitudinal cross-sectional schematic diagram of a light-emitting diode provided in an embodiment of the present invention.

[0037] Figure 2B yes Figure 2A A magnified view of the area circled by the dashed lines.

[0038] Figure 3 It is along Figure 1 A schematic diagram of the longitudinal section cut by the intercept line A-A'.

[0039] Figure 4 It is along Figure 1 A schematic diagram of the longitudinal section intercepted by the intercept line B-B'.

[0040] Figures 5-7 This is a top view of a light-emitting diode, illustrating several exemplary designs of discontinuously distributed grooves according to the present invention.

[0041] Figure 8 This is a top view of a light-emitting diode, which is an exemplary embodiment of the continuous distributed groove design of the present invention.

[0042] Figure 9 This is a cross-sectional view of a flip-chip light-emitting diode, which is an exemplary embodiment of the present invention.

[0043] Figure 10 This is a cross-sectional view of a light-emitting diode, which is another exemplary embodiment of the present invention.

[0044] Figure 11 This is a cross-sectional view of a light-emitting diode, which is another exemplary embodiment of the present invention.

[0045] Figure 12 This is a cross-sectional view of a light-emitting diode, which is another exemplary embodiment of the present invention.

[0046] Reference numerals: Substrate 110; Semiconductor stack 120; First semiconductor layer 121; Light-emitting layer 122; Second semiconductor layer 123; Upper surface 124; Lower surface 125; Mesa 126; Sidewall 127; Groove 130; First sidewall S1; Second sidewall S2; Third sidewall S3; First electrode 141; Second electrode 142; First distance d1; Cross-sectional width L1 of the first electrode; Second distance d2; Third distance d3; First height H1; Second height H2; First contact electrode 151; First connecting electrode 161; Second contact electrode 152; Second connecting electrode 162; First pad electrode 171; Second pad electrode 172; Insulating layer 180; First highly doped layer 123A; Electron blocking layer 123B; Second highly doped layer 123C. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. The technical features designed in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0048] In the description of this invention, it should be understood that the terms "center," "lateral," "upper," "lower," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more. Additionally, the term "comprising" and any variations thereof mean "at least comprising."

[0049] Please see Figures 1-4 , Figure 1 This is a top view schematic diagram of a light-emitting diode provided in an embodiment of the present invention. Figure 2A This is a longitudinal cross-sectional view of a light-emitting diode provided in an embodiment of the present invention. Figure 2B yes Figure 2A A magnified view of the area circled in dashed lines. Figure 3 It is along Figure 1 The schematic diagram of the longitudinal section taken by the intercept line AA, that is, the schematic diagram of the longitudinal section of the first electrode 141 set in the groove 130. Figure 4 It is along Figure 1 The longitudinal cross-sectional view of the first electrode 141 not set in the groove 130 is shown in the diagram below.

[0050] As shown in the figure, the light-emitting diode may include: a semiconductor stack 120, a first electrode 141, and a second electrode.

[0051] Semiconductor stack 120 is disposed on substrate 110. Substrate 110 may be an insulating substrate. Preferably, substrate 110 may be a transparent substrate or a semi-transparent substrate, wherein the transparent substrate or semi-transparent substrate allows light radiated from light-emitting layer 122 to pass through the substrate and reach the side of the substrate away from semiconductor stack 120. For example, substrate 110 may be any one of sapphire flat substrate, sapphire patterned substrate, silicon substrate, silicon carbide substrate, gallium nitride substrate, and glass substrate.

[0052] In some embodiments, a combined patterned substrate 110 may be used, the pattern of which is a series of raised structures. These raised structures can be one or more layers, including at least one light extraction layer with a refractive index lower than that of the substrate 110. The thickness of this light extraction layer is greater than half the height of the raised structure, which is more beneficial to the light extraction efficiency of the ultraviolet light-emitting diode. Preferably, the raised structure is bullet-shaped, and the material of the light extraction layer can have a refractive index preferably less than 1.6, such as silicon dioxide. In some embodiments, the substrate 110 can be thinned or removed to form a thin-film chip.

[0053] The semiconductor stack 120 has a mesa 126, a sidewall 127, an opposing lower surface 125, and an upper surface 124. The semiconductor stack 120, from the lower surface 125 to the upper surface 124, sequentially includes a first semiconductor layer 121, a light-emitting layer 122, and a second semiconductor layer 123. In this embodiment, the mesa 126 is located on the surface of the first semiconductor layer 121 not covered by the light-emitting layer 122, and is on the same side as the upper surface of the semiconductor stack. The sidewall 127 refers to the side connecting the upper surface 124 and the mesa 126.

[0054] A first semiconductor layer 121 is formed on a substrate 110. The first semiconductor layer 121 can be an N-type semiconductor layer, which can supply electrons to the light-emitting layer 122 under the action of a power source. In some embodiments, the first semiconductor layer 121 includes an N-type doped nitride layer. The N-type doped nitride layer may include one or more N-type impurities of group IV elements. The N-type impurities may include one or a combination of Si, Ge, and Sn. In this embodiment, the first semiconductor layer 121 is doped with Al to facilitate the emission of ultraviolet light by the ultraviolet light-emitting diode. In some embodiments, a buffer layer may be provided between the first semiconductor layer 121 and the substrate 110 to reduce the lattice mismatch between the substrate 110 and the N-type semiconductor layer. The buffer layer may include an un-doped AlN layer (u-AlN) or an un-doped AlGaN layer (u-AlGaN). In other embodiments, the first semiconductor layer 121 may also be connected to the substrate 110 by an adhesive layer.

[0055] The light-emitting layer 122 can be a quantum well (QW) structure. In some embodiments, the light-emitting layer 122 can also be a multiple quantum well (MQW) structure, wherein the multiple quantum well junction includes multiple quantum well layers (Wel1) and multiple quantum barrier layers (Barrier) arranged alternately in a repeating manner, such as GaN / AlGaN, InAlGaN / InAlGaN, or InGaN / AlGaN multi-quantum well structures. Furthermore, the composition and thickness of the well layers within the light-emitting layer 122 determine the wavelength of the generated light. To improve the luminous efficiency of the light-emitting layer 122, this can be achieved by changing the depth of the quantum wells, the number of paired quantum wells and quantum barriers, the thickness, and / or other characteristics within the light-emitting layer 122. In particular, by adjusting the composition of the well layers, a light-emitting layer 122 that generates different colors of light, such as ultraviolet, blue, and green light, can be provided. In this embodiment, the emission wavelength range of the ultraviolet light-emitting diode 1 is 200nm-420nm, that is, the emission wavelength range of the light-emitting layer 122 is 200nm-420nm.

[0056] The second semiconductor layer 123 may be a P-type semiconductor layer, which can provide holes to the light-emitting layer 122 under power supply. In some embodiments, the second semiconductor layer 123 includes a P-type doped nitride layer. The P-type doped nitride layer may include one or more P-type impurities of group II elements. The P-type impurities may include one or a combination of Mg, Zn, and Be.

[0057] Although the first semiconductor layer 121 and the second semiconductor layer 123 can each be a single-layer structure, this invention is not limited to this. The first semiconductor layer 121 and the second semiconductor layer 123 can also be a multi-layer structure with different compositions, and may also include a superlattice layer. Furthermore, the arrangement of the semiconductor stack 120 is not limited to this; other types of semiconductor stacks 120 can be selected according to actual needs. For example, in other embodiments, when the first semiconductor layer 121 is doped with p-type impurities, the second semiconductor layer 123 can be doped with n-type impurities, that is, the first semiconductor layer 121 is a p-type semiconductor layer, and the second semiconductor layer 123 is an n-type semiconductor layer.

[0058] The platform 126 is provided with a groove 130, which extends from the platform 126 into the first semiconductor layer 121. In this embodiment, the first electrode 141 has a strip-shaped structure and is electrically connected to the first semiconductor layer 121, allowing the current injected through the first electrode 141 to be injected from the sidewall of the first semiconductor layer 121, thereby reducing the operating voltage and improving product stability. The first electrode 141 has a first sidewall S1 near the sidewall 127 of the semiconductor stack, which is at least partially disposed within the groove 130. This allows for layered adjustment of the current flow, reducing current congestion and thus increasing current spread, thereby reducing voltage and improving brightness. Specifically, the current flow path of the first electrode 141 disposed within the groove 130 is as follows: Figure 3 Path A in the diagram has both horizontal and vertical directions. The current flow path of the first electrode 141, which is not located within the groove 130, is as follows: Figure 4 Path B in the groove has both horizontal and vertical directions, meaning the current flow path of the first electrode 141 includes paths A and B, which are not in the same dimension. Compared to the prior art's grooveless structure design where the current flow path of the first electrode 141 is only path B in the same dimension, this structure design can simultaneously adjust the current in both horizontal and vertical directions, allowing the current flowing in different areas to be positioned differently, reducing current congestion. Preferably, the groove 130 has a second sidewall S2 away from the sidewall 127. The distance from the first sidewall S1 to the second sidewall S2 is a first distance d1, which is less than the cross-sectional width L1 of the first electrode 141. This means the first electrode 141 can extend upwards from the groove 130 to the surface covering the first semiconductor layer 121, which also allows for layered adjustment of the current flow direction, further reducing current congestion. Specifically, the current flow path of the first electrode 141 disposed in the groove 130 also includes... Figure 3 Path C (dashed line) is the current flow path of the first electrode 141 set on the platform 126. It also has two directions, horizontal and vertical. There are more charge carriers in this area and the charge carrier flow distance is longer. The current flow of path A (solid line) and path C (dashed line) has a time difference, which can further reduce the current congestion effect. At the same time, based on this design, the contact area between the first electrode 141 and the first semiconductor layer 121 is greatly increased, which increases the volume of the first electrode 141 and reduces the voltage.

[0059] In this embodiment, the groove 130 has a second sidewall S2 away from the sidewall 127 and a third sidewall S3 opposite to the second sidewall S2, with the third sidewall S3 located between the sidewall and the second sidewall S2. The third sidewall S3 and the sidewall 127 are separated by a second distance d2 to avoid damage to the second mesa structure during the formation of the groove. Preferably, the second distance d2 is 1 μm or more, for example, it can be 1~10 μm, while also avoiding increasing the current flow distance when the second distance d2 is too large.

[0060] In this embodiment, the third sidewall S3 and the first sidewall S1 are separated by a distance d3, which facilitates the formation of the first electrode 141 within the groove. Preferably, the third distance d3 is 1 μm or more, for example, it can be 1~10 μm, while also avoiding the increase in current flow distance when the third distance d3 is too large.

[0061] In some embodiments, the distance from the bottom of the groove 130 to the lower surface 125 of the semiconductor stack is a second height H2, which is 1 / 5 to 1 / 2 of the thickness of the first semiconductor layer 121. When the second height H2 is too large, the charge carriers will still accumulate near the mesa 126, resulting in poor stratified current regulation and current congestion, thus reducing the injection of charge carriers. When the second height H2 is too small, the distance from the bottom of the groove 130 to the lower surface 125 of the semiconductor stack is very small, which will cause congestion when the charge carriers reach the bottom of the groove, thus reducing the injection of charge carriers and hindering the expansion of charge carriers. Further, in some embodiments, the distance from the mesa 126 into the first semiconductor layer 121 is a first height H1, which is greater than 100 nm. Preferably, the first height H1 is in the range of 600 nm to 1200 nm, so as to simultaneously ensure the effect of stratified current regulation and the effect of charge carrier expansion.

[0062] In some embodiments, the distance from the control surface 126 to the lower surface 125 of the semiconductor stack is greater than or equal to more than half the thickness of the first semiconductor layer 121. When the distance from the control surface 126 to the lower surface 125 of the semiconductor stack is too small, it will cause current congestion in the region below the control surface 126, thereby reducing carrier injection and hindering carrier expansion. Preferably, this distance can be between 60% and 95% of the thickness of the first semiconductor layer.

[0063] In some embodiments, viewed from above the light-emitting diode towards the semiconductor stack 120, such as... Figure 1 As shown, the opening shape of the groove 130 is square, circular, or elliptical. A design that is close to square is more suitable, as it facilitates the first electrode 141 being connected across the groove 130. The width of the opening of the groove 130 is 1~50μm.

[0064] In some embodiments, considering the issue of reflected light and the current level of manufacturing technology, the size of the groove 130 at the platform 126 is larger than the size of the bottom of the groove 130, which can improve the reflective effect and enhance the light emission performance of the light-emitting diode. Preferably, the cross-sectional shape of the groove 130 is an inverted trapezoid, and the inclination angle of the groove 130 is less than 90 degrees, preferably in the range of 20 to 50 degrees, to further enhance the light emission performance of the light-emitting diode. At the same time, when plating the first electrode 141, if the sidewall of the groove 130 is a vertical edge (with an included angle of 90 degrees), there will be uneven plating at the corners of the groove 130.

[0065] In some embodiments, viewed from above the light-emitting diode towards the semiconductor stack 120, such as... Figure 1 As shown, the first electrode 141 and the groove 130 have an overlapping portion, and the projected area of ​​the overlapping portion is 5%-70% of the projected area of ​​the first electrode 141, for example, 15%-50%. Further, in some embodiments, the area of ​​the groove 130 occupies 5%-60% of the area of ​​the mesa 126, that is, the area of ​​the groove 130 projected onto the upper surface of the substrate 110 accounts for 5%-60% of the area of ​​the mesa 126 projected onto the upper surface of the substrate 110, thereby ensuring current transmission. If the area of ​​the groove 130 is too large, it will lead to uneven current and uneven light output. Preferably, the area of ​​the groove 130 occupies 10%-40% of the area of ​​the mesa 126.

[0066] In some embodiments, the grooves 130 are more concentrated at the electrode corners, which effectively solves the current congestion phenomenon that is more likely to occur at the electrode corners, thereby effectively improving the carrier injection efficiency of the light-emitting diode. In this embodiment, the grooves 130 are distributed intermittently, which reduces the number of mesa areas and improves the light emission effect of the light-emitting diode. Please refer to [link to relevant documentation]. Figures 5-7 Several intermittently distributed groove designs are listed, such as Figure 5 Because current congestion is more likely to occur at electrode corners, the grooves 130 can be concentrated only at these corners. This design can address the current congestion effect at electrode corners without sacrificing significant mesa area. Furthermore, the design can increase the area of ​​the light-emitting region (not shown in the figure), thereby effectively improving the light emission performance of the LED. In some embodiments, the groove spacing is uniform or gradually varied. Figure 6 The spacing of the grooves is gradually distributed. Specifically, the spacing of the grooves 130 gradually increases as they move away from the corner positions of the first electrode 141 and the second electrode 142. That is, the grooves with a denser spacing are set near the electrode corner positions, and the grooves with a sparser spacing are set away from the electrode corner positions. This design can also solve the current congestion effect at the electrode corner positions while minimizing the loss of mesa area. Figure 7The grooves are evenly distributed. Specifically, the grooves 130 have different equal spacing near the electrode corner and away from the electrode corner. That is, the grooves 130 have a denser equal spacing near the electrode corner and a sparser equal spacing away from the electrode corner. The spacing of the grooves 130 near the electrode corner can range from 1 to 40 μm, and the spacing of the grooves 130 away from the electrode corner can range from 5 to 100 μm. Preferably, the spacing of the grooves 130 near the electrode corner can range from 10 to 30 μm, and the spacing of the grooves 130 away from the electrode corner can range from 20 to 90 μm, which is more conducive to current spread, thereby reducing voltage and improving brightness.

[0067] In other embodiments, please refer to Figure 8 The distribution of the grooves 130 can also be continuous. When the grooves are continuously distributed, the distance between the first sidewall S1 and the second sidewall S2 of the groove 130 must be less than the cross-sectional width of the first electrode 141. The current flow through paths A and C with different current flow distances forms a similar time difference, thereby reducing the current congestion effect.

[0068] exist Figures 5-7 In the illustrated embodiment, the grooves 130 can be discontinuously distributed. In this case, a portion of the charge carriers injected through the mesa can directly migrate to the first semiconductor layer on the upper surface of the semiconductor stack through the gaps between the grooves 130 (e.g., ...). Figure 4 Path B in the diagram can be used to reduce the height of the second height H2, which can then be 200-500 nm, for example, 300 nm. In other embodiments, the grooves 130 can also be continuously distributed, such as... Figure 8 As shown. In this case, the height of the second height H2 is preferably 400~800nm, for example, it can be 500nm or 600nm.

[0069] The first electrode 141 directly contacts the N-type semiconductor layer (first semiconductor layer 121). The first electrode 141 is selected from one or more of Cr, Pt, Au, Ni, Ti, and Al. Since the first semiconductor layer 121 has a high Al content, the first electrode 141 needs to be fused at high temperature after being deposited on the mesa 126 to form an alloy, thereby forming a good ohmic contact with the first semiconductor layer 121. The first electrode 141 can be a single-layer, double-layer, or multi-layer structure, such as a stacked structure of Ti / Al, Ti / Al / Au, Ti / Al / Ni / Au, Cr / Al / Ti / Au, Ti / Al / Au / Pt, etc.

[0070] The second electrode directly contacts the P-type semiconductor layer (second semiconductor layer 123). This second electrode can be made of a transparent conductive oxide material or a metallic material, such as NiAu, NiAg, NiRh, etc., and its thickness is preferably less than 30 nm to minimize the light absorption rate of this layer. In a preferred embodiment, the wavelength emitted by the light-emitting layer 122 is below 280 nm, and the contact electrode 142 is ITO with a thickness of 5~20 nm, for example, 10~15 nm. In this case, the absorption rate of the ITO layer for the light emitted by the light-emitting layer 122 can be reduced to less than 40%.

[0071] In some embodiments, the light-emitting diode is a flip-chip light-emitting diode, and may further include a first pad electrode 171 and a second pad electrode 172. (See also...) Figure 9 The first electrode 141 includes a first contact electrode 151 and a first connecting electrode 161. The first contact electrode 151 is at least partially disposed within the groove 130 and directly contacts the N-type semiconductor layer (first semiconductor layer 121). The first connecting electrode 161 is at least partially disposed within the groove 130 and connected to the first contact electrode 151. The second electrode includes a second contact electrode 152 and a second connecting electrode 162. The second contact electrode 152 directly contacts the P-type semiconductor layer (second semiconductor layer 123), and the second connecting electrode 162 is connected to the second contact electrode 152. The connecting electrode is preferably a multilayer metal stack, for example, an adhesion layer and a conductive layer are sequentially deposited on the contact electrode. The adhesion layer can be a Cr metal layer with a thickness typically of 1~10 nm, and the conductive layer can be an Al metal layer with a thickness of 100 nm or more, for example, 200 nm~500 nm. On the one hand, Al has good conductivity, and on the other hand, Al has high reflectivity to ultraviolet light. Preferably, the reflectivity of the conductive layer to the light emitted by the light-emitting layer 122 is 70% or more. Furthermore, a stress buffer layer, such as an Al / Ti alternating layer, is preferably inserted inside the conductive layer. Additionally, an etch stop layer (Pt) and an adhesion layer (Ti) can also be formed on the conductive layer. Preferably, the first connecting electrode 161 completely covers the first contact electrode 151, which both increases the height of the first electrode 141 and protects the first contact electrode 151.

[0072] An insulating layer 180 is formed on the connecting electrodes, the sides of the semiconductor layer sequence, the sides of the mesa 126, and within the groove 130, insulating the first connecting electrode 161 and the second connecting electrode 162. The insulating layer 180 has openings to expose the first connecting electrode 161 and the second connecting electrode 162. The insulating layer 180 is made of a non-conductive material. The non-conductive material is preferably an inorganic material or a dielectric material. Inorganic materials include silicone or glass, and dielectric materials include alumina, silicon nitride, silicon oxide, titanium oxide, or magnesium fluoride. For example, the insulating layer 180 can be silicon dioxide, silicon nitride, titanium oxide, tantalum oxide, niobium oxide, barium titanate, or a combination thereof, such as a Bragg reflector (DBR) formed by repeatedly stacking two materials. In some embodiments, the insulating layer 180 is preferably a reflectivity insulating layer. As shown, the light-emitting diode has a large-area mesa structure. Since the second connecting electrode 162 is only partially formed on the second contact electrode 152, the light extraction efficiency of the light-emitting diode can be effectively improved by setting the insulating layer 180 to a highly reflective structure.

[0073] The first pad electrode 171 and the second pad electrode 172 are located on the insulating layer 180 and are electrically connected to the first connecting electrode 161 and the second connecting electrode 162 through openings, respectively. The first pad electrode 171 and the second pad can be formed together in the same process using the same material, and therefore can have the same layer structure. The material of the first and second pads can be selected from one or more of Cr, Pt, Au, Ni, Ti, Al, and AuSn.

[0074] In a modified embodiment, please refer to Figure 10 The groove 130 has a second sidewall S2 away from the sidewall 127 and a third sidewall S3 opposite to the second sidewall S2. The third sidewall S3 is directly connected to the sidewall 127, that is, the second distance d2 is 0μm. Based on this design, the current flow distance can be reduced to a certain extent.

[0075] Figure 11 A schematic diagram of the structure of a light-emitting diode disclosed in another exemplary embodiment of the present invention is shown, and its top view can be referred to. Figure 8 In this embodiment, the light-emitting diode employs continuously distributed grooves 130 (e.g., Figure 8 As shown, the mesa 126 of the light-emitting diode includes a complete first semiconductor layer 121 and a partial light-emitting layer 122, meaning the upper surface of the mesa 126 is located on the light-emitting layer 122. Specifically, the light-emitting layer 122 may have n-type doping, such as Si doping, and its doping depth is preferably 1×10⁻⁶. 18 / cm 3 The preferred value is 1×10. 18 / cm 3 Up to 1×10 19 / cm3 Between, for example, can be 2×10 18 / cm 3 Or 5×10 18 / cm 3 wait.

[0076] In this embodiment, by appropriately adding n-type doping to the light-emitting layer 122, it is beneficial to increase the electron concentration of the light-emitting layer 122 and thus improve the internal quantum efficiency. On the other hand, it makes the light-emitting layer 122 suitable for directly fabricating the first contact electrode 151 with good ohmic contact. In a specific embodiment, the band gap of the light-emitting layer 122 is lower than the band gap of the first semiconductor layer 121, which is more conducive to the formation of good ohmic contact between the first electrode 141 and the upper surface of the mesa 126.

[0077] In a specific embodiment, the semiconductor layer sequence may include a confinement layer (not shown in the figure) disposed between the light-emitting layer 122 and the second semiconductor layer 123. The confinement layer preferably has a high Al content and is low-doped or undoped, and its thickness is preferably less than 50 nm. It can restrict the diffusion of dopants from the second semiconductor layer 123 to the light-emitting layer 122, thereby improving the photoelectric performance of the light-emitting diode.

[0078] In this embodiment, by providing a completely blocking groove 130 on the mesa 126, the light-emitting layer 122 of the semiconductor stack 120 is separated from the light-emitting layer 122 of the mesa 126, which increases the distance between the mesa and the lower surface 125 of the semiconductor stack, thereby further improving the expansion and carrier injection efficiency of the first semiconductor layer 121.

[0079] Figure 12 A schematic diagram of the structure of a light-emitting diode disclosed in another exemplary embodiment of the present invention is shown, and its top view can be referred to. Figure 8 In this embodiment, the light-emitting diode employs continuously distributed grooves 130 (e.g., Figure 8 As shown in the diagram, the mesa 126 of the light-emitting diode includes a complete first semiconductor layer 121, a light-emitting layer 122, and a partial second semiconductor layer 123, meaning the upper surface of the mesa 126 is located on the second semiconductor layer 123. Specifically, the second semiconductor layer 123 is p-type doped and may include a first highly doped layer 123A, an electron blocking layer 123B, and a second highly doped layer 123C stacked sequentially. The first highly doped layer 123A is located between the electron blocking layer 123B and the light-emitting layer 122, serving as the ohmic contact layer and hole injection layer of the first contact electrode 151. The doping concentration of the first highly doped layer 123A is preferably 1 × 10⁻⁶. 19 / cm 3 For example, it could be 1×10 19 / cm 3~5×10 19 / cm 3 The doping concentration of electron blocking layer 123B is 1×10⁻⁶. 17 / cm 3 For example, it could be 1×10 18 / cm 3 ~1×10 19 / cm 3 Between these layers, the preferred doping concentration of the second highly doped layer 123C is 5 × 10⁻⁶. 19 / cm 3 For example, it could be 5×10 19 / cm 3 ~5×10 21 / cm 3 .

[0080] The band gap of the electron blocking layer 123B is higher than that of the first highly doped layer 123A and the second highly doped layer 123C. Therefore, the control surface 126 is lower than the electron blocking layer 123B, preventing carriers injected from the mesa 126 from being blocked by the electron blocking layer 123B and thus reducing the injection efficiency. In a specific embodiment, the height difference between the mesa 126 and the upper surface 124 of the semiconductor stack is preferably greater than 50 nm and less than or equal to 500 nm, for example, it can be greater than 50 nm and less than 200 nm or greater than or equal to 200 nm and less than or equal to 500 nm.

[0081] In this exemplary embodiment, by providing a completely blocking groove 130 on the mesa 126, the light-emitting layer 122 of the semiconductor stack 120 is separated from the light-emitting layer 122 of the mesa 126, so that the mesa 126 can be raised to the second semiconductor layer 123. By inserting a first highly doped layer 123A on the side of the second semiconductor layer 123 near the light-emitting layer 122, the first highly doped layer 123A in the region of the mesa 126 can serve as an electrode contact surface, directly fabricating a first contact electrode 151 with good ohmic contact. The first highly doped layer 123B in the region of the semiconductor stack 120 serves as a hole injection layer, which can improve the hole injection efficiency of the second semiconductor layer 123.

[0082] In this embodiment, since the first electrode 141 is formed on the first highly doped layer 123A of the second semiconductor layer 123, the same material as the second contact electrode 152 can be selected. On the one hand, this solves the problem of forming ohmic contacts in the n-type AlGaN semiconductor layer, and on the other hand, it reduces the height difference between the upper surface 124 and the mesa 126 of the semiconductor stack. When pad electrodes are fabricated on the upper surface 124 and the mesa 126 of the semiconductor stack, the overall product has better thrust and reliability under the same conditions.

[0083] The present invention also provides a light-emitting device, which employs the light-emitting diode provided in any of the above embodiments.

[0084] Furthermore, those skilled in the art should understand that although many problems exist in the prior art, each embodiment or technical solution of the present invention can be improved in only one or a few aspects, without necessarily solving all the technical problems listed in the prior art or the background art simultaneously. Those skilled in the art should understand that any content not mentioned in a claim should not be construed as a limitation on that claim.

[0085] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A light-emitting diode, comprising: A semiconductor stack has a mesa, sidewalls, and opposing lower and upper surfaces. The semiconductor stack includes, from the lower surface to the upper surface, a first semiconductor layer, a light-emitting layer, and a second semiconductor layer. The mesa is on the same side as the upper surface of the semiconductor stack. The sidewalls are the sides connecting the upper surface and the mesa. The first electrode is electrically connected to the first semiconductor layer. The second electrode is electrically connected to the second semiconductor layer. The feature is that: the mesa has a groove extending into the first semiconductor layer; the first electrode has a first sidewall close to the sidewall, the first sidewall being at least partially disposed within the groove; the first electrode has a fourth sidewall away from the sidewall, the fourth sidewall being entirely disposed outside the groove; the groove has a second sidewall away from the sidewall; and the distance from the first sidewall to the second sidewall is less than the cross-sectional width of the first electrode.

2. The light-emitting diode according to claim 1, characterized in that: The grooves can be continuously or intermittently distributed.

3. The light-emitting diode according to claim 1, characterized in that: The groove has a third sidewall opposite to the second sidewall, and the third sidewall is at a distance from the sidewall.

4. The light-emitting diode according to claim 3, characterized in that: The third sidewall is at a distance from the first sidewall.

5. The light-emitting diode according to claim 1, characterized in that: The distance from the bottom of the groove to the lower surface of the semiconductor stack is 1 / 5 to 1 / 2 of the thickness of the first semiconductor layer.

6. The light-emitting diode according to claim 1, characterized in that: The groove extends from the mesa into the first semiconductor layer by a distance greater than 100 nm.

7. The light-emitting diode according to claim 1, characterized in that: Viewed from above the light-emitting diode toward the semiconductor stack, the first electrode and the groove have an overlapping portion, and the projected area of ​​the overlapping portion is 5%-70% of the projected area of ​​the first electrode.

8. The light-emitting diode according to claim 1, characterized in that: Viewed from above the light-emitting diode and towards the semiconductor stack, the area of ​​the recess occupies 5% to 60% of the area of ​​the mesa.

9. The light-emitting diode according to claim 1, characterized in that: Viewed from above the light-emitting diode toward the semiconductor stack, the groove opening shape includes square, circular, and elliptical.

10. The light-emitting diode according to claim 1, characterized in that: The width of the opening of the groove on the platform is 1~50μm.

11. The light-emitting diode according to claim 1, characterized in that: The size of the groove on the table surface is larger than the size of the bottom of the groove.

12. The light-emitting diode according to claim 1, characterized in that: The groove has a trapezoidal cross-sectional shape and an inclination angle of less than 90 degrees.

13. The light-emitting diode according to claim 1, characterized in that: The spacing of the grooves is either uniformly distributed or gradually distributed.

14. The light-emitting diode according to claim 1, characterized in that: The first electrode and the second electrode have a corner, and the groove is disposed near the corner.

15. The light-emitting diode according to claim 14, characterized in that: The spacing between the grooves is set to gradually increase as the distance from the corner position increases.

16. The light-emitting diode according to claim 14, characterized in that: The grooves are spaced 1~40μm apart near the corner.

17. The light-emitting diode according to claim 14, characterized in that: The grooves are spaced 5~100μm apart from the corner position.

18. The light-emitting diode according to claim 1, characterized in that: The first electrode has a strip-shaped structure.

19. A light-emitting device, characterized in that: The light-emitting device is a light-emitting diode as described in any one of claims 1 to 18.

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