Adaptive bridge arm capacitor voltage balancing method for high-power modular multilevel converters

Abstract

The present invention provides a method for adaptive bridge arm capacitor voltage balancing of a high-power modular multilevel converter, including a three-phase modular multilevel converter MMC; the three-phase modular multilevel converter MMC includes six bridge arms, wherein each bridge arm is composed of N completely identical sub-modules SM, a bridge arm inductor L and a bridge arm equivalent resistance R, and the upper and lower bridge arms of each phase are collectively referred to as a phase unit; the voltage between the positive and negative DC busbars is, and the center point of the zero potential reference point is the zero potential reference point O; the application of this technical solution can achieve the reduction of the average switching frequency of the bridge arm submodules while accurately controlling the consistency of the bridge arm capacitor voltage.

Description

Technical Field

[0001] The present invention relates to the technical field of modular multi-level converters, in particular to an adaptive bridge arm capacitor voltage balancing method for a high-power modular multi-level converter. Background Art

[0002] Modular multilevel converters (MMCs) offer inherent advantages such as modular topology, good harmonic characteristics, low switching frequency, redundant control, strong scalability, robust fault protection, and the absence of filtering devices. They have attracted widespread attention and application in medium-, high-voltage, and high-power applications, including flexible direct current (HVDC) transmission, flexible multi-state switches for distribution networks, power routers, and offshore wind power grid integration. As MMC-HVDC systems evolve toward higher voltage levels and larger capacities, the number of submodules within them has increased exponentially, making capacitor voltage balancing a critical and unavoidable issue in the engineering applications of modular multilevel converters.

[0003] Modular multilevel converters (MMCs) require a large number of sub-modules (SMs) connected in series. However, the voltage on the sub-module capacitors is not constant. Due to differences in charging time, parameters, and losses within the MMC, the capacitor voltage exhibits a certain degree of discreteness. If left uncontrolled, this can damage the sub-modules and potentially lead to system failure. However, existing voltage balancing algorithms often suffer from high switching frequencies, resulting in unnecessary switching losses and increased device costs. Summary of the Invention

[0004] In view of this, the object of the present invention is to provide an adaptive bridge arm capacitor voltage balancing method for a high-power modular multi-level converter, which can reduce the average switching frequency of the bridge arm submodules while accurately controlling the bridge arm capacitor voltage consistency.

[0005] To achieve the above object, the present invention adopts the following technical solution: a high-power modular multilevel converter adaptive bridge arm capacitor voltage balancing method, including a three-phase modular multilevel converter MMC; the three-phase modular multilevel converter MMC includes six bridge arms, wherein each bridge arm is composed of N identical sub-modules SM, a bridge arm inductor L and a bridge arm equivalent resistance R, and the upper and lower bridge arms of each phase are collectively referred to as a phase unit; the voltage between the positive and negative DC bus is U dc , the center point of the zero potential reference point is the zero potential reference point O;

[0006] It also includes a half-bridge submodule; the half-bridge submodule includes a first insulated gate bipolar transistor T1, a second insulated gate bipolar transistor T2, a first anti-parallel diode D1, a second anti-parallel diode D2, a submodule DC capacitor C0 and a capacitor voltage u c The input submodule current i between the first insulated gate bipolar transistor T1 and the second insulated gate bipolar transistor T2 sm , submodule current i sm The voltage u across the half-bridge module is between the input point and the emitter of the second insulated gate bipolar transistor T2. sm , each half-bridge sub-module passes the sub-module current i sm The input point of the bus is connected in series with the emitter of the second insulated gate bipolar transistor T2 to the main circuit topology, and the three-phase modular multilevel converter MMC supports the bus voltage through the capacitor voltage in each half-bridge sub-module.

[0007] In a preferred embodiment, under normal working conditions, the first insulated gate bipolar transistor T1 and the second insulated gate bipolar transistor T2 are in complementary switching states, alternately turned on and off; the half-bridge submodule has three working states: locked state, engaged state, and cut-off state.

[0008] In a preferred embodiment, when the first insulated gate bipolar transistor T1 and the second insulated gate bipolar transistor T2 are both applied with a shutdown signal, this is called a locked state. The two operating modes are divided into a first mode a and a second mode b according to the conduction status of the first anti-parallel diode D1 and the second anti-parallel diode D2. In the first mode b, the first anti-parallel diode D1 is turned on, the half-bridge sub-module current charges the capacitor through the first anti-parallel diode D1, and the output voltage is the capacitor voltage. In the second mode b, the second anti-parallel diode D2 is turned on, the half-bridge sub-module current bypasses the capacitor through the second anti-parallel diode D2, and the output voltage is 0.

[0009] In a preferred embodiment, when a turn-on signal is applied to the first insulated gate bipolar transistor T1 and a turn-off signal is applied to the second insulated gate bipolar transistor T2, this state is referred to as the on-state. Two operating modes are also defined based on the direction of current flow in the half-bridge sub-module, namely, a third mode c and a fourth mode d. In the third mode c, the first anti-parallel diode D1 is turned on, while the first insulated gate bipolar transistor T1 is subjected to a reverse voltage. Despite the application of the turn-on signal, the first insulated gate bipolar transistor T1 remains in the off-state. The sub-module current charges the capacitor through the first anti-parallel diode D1, and the output voltage is the capacitor voltage. In the fourth mode d, the first insulated gate bipolar transistor T1 is turned on, while the first anti-parallel diode D1 is in the off-state due to the reverse voltage. The half-bridge sub-module current discharges the capacitor through the first insulated gate bipolar transistor T1, and the output voltage is the capacitor voltage.

[0010] In a preferred embodiment, when a shutdown signal is applied to the first insulated gate bipolar transistor T1 and a turn-on signal is applied to the second insulated gate bipolar transistor T2, this state is referred to as a cut-off state. Two operating modes are also provided based on the direction of current flow in the half-bridge sub-module, namely, a fifth mode e and a sixth mode f. In the fifth mode e, the second insulated gate bipolar transistor T2 is turned on, while the second anti-parallel diode D2 is in the off state due to the reverse voltage. The current of the half-bridge sub-module bypasses the capacitor through the second insulated gate bipolar transistor T2, and the output voltage is zero. In the sixth mode f, the second anti-parallel diode D2 is turned on, while the second insulated gate bipolar transistor T2 is in the off state due to the reverse voltage. Despite the turn-on signal, the second insulated gate bipolar transistor T2 remains in the off state. The current of the half-bridge sub-module bypasses the capacitor through the second anti-parallel diode D2, and the output voltage is zero.

[0011] In a preferred embodiment, the relationship between the switching frequency and the capacitor voltage deviation is analyzed and obtained according to Kirchhoff's voltage-current law:

[0012]

[0013]

[0014] Among them: j represents the three phases a, b, c, j = a, b, c; u pj ,u nj Respectively represents the sum of the voltages of the upper and lower bridge arm submodules of the three phases a, b, and c; U dc Indicates the DC side bus line voltage; u jo Respectively represent the voltage difference between the MMC three-phase AC output side and the neutral point O; i pj ,i nj Respectively represent the current of the upper and lower bridge arms of the three phases a, b, and c; i vj Indicates AC three-phase current measurement; i diffj Indicates the internal current flowing through the upper and lower bridge arms simultaneously;

[0015] According to the analysis, the internal current i diffj The DC current component i during normal operation should be dc and AC circulating current component i cirj Composition, expressed as:

[0016]

[0017] Where: o represents the fundamental angular frequency; δ0 represents the initial phase angle; θ0 represents the power factor angle;

[0018] The AC output voltage of the three-phase modular multilevel converter MMC is expressed as:

[0019]

[0020] Where: m represents the voltage modulation coefficient; ω o represents the fundamental angular frequency; δ0 represents the initial phase angle;

[0021] Substituting equation (4) into equation (1), we can get the upper and lower bridge arm reference voltage u ref for:

[0022]

[0023] At this time, according to the nearest level control method, the number of bridge arm sub-modules is:

[0024]

[0025] Among them: U c_ava represents the average operating voltage of the bridge arm submodule capacitor; round(·) indicates taking the integer closest to the calculated value in the brackets.

[0026] In a preferred embodiment, the number of switches in the three-phase modular multilevel converter MMC consists of two parts, one for providing the required AC output voltage and the other for balancing the capacitor voltage;

[0027] According to the incremental number of bridge arm submodules in the next control cycle, the number of switches in the first part is expressed as:

[0028] Δn ref (T k )=n ref (T k )-n ref (T k-1 ) (7)

[0029] Where: n ref (T k ), n ref (T k-1 ) represent the T k and T k-1 The number of bridge arm submodules put into operation during the control cycle;

[0030] Each cycle needs to change n alt The switch status of the submodules; the number of switches of these submodules is determined by the submodule selection mechanism; by alt Appropriate selection achieves balanced control of capacitor voltage and frequency;

[0031] At this time, the number of submodule switches in each control cycle is expressed as:

[0032]

[0033] Where: nswon Indicates the number of bridge arm submodules that are turned on; n swoff Indicates the number of bridge arm submodules that are closed;

[0034] Δn ref Indicates the incremental number of bridge arm submodules; n alter Indicates the variable number of bridge arm submodules;

[0035] Define the maximum unbalanced capacitance voltage U of the bridge arm c_error is the maximum capacitance voltage difference of the bridge arm, and its expression is:

[0036] U c_error =U c_max -U c_min (9)

[0037] Among them: U c_max , U c_min They represent the maximum capacitance voltage of the bridge arm and the minimum capacitance voltage of the bridge arm respectively.

[0038] In a preferred embodiment, the half-bridge sub-module capacitor voltage increment is composed of two parts. One part is the maximum unbalanced capacitor voltage U c_error , part of which is the minimum voltage increment ΔU c_min :

[0039] ΔU c_x =U c_error +ΔU c_min (10)

[0040] Where: ΔU c_x Indicates the capacitor voltage increment of the xth submodule;

[0041] Since T0-T k At the moment when the submodule x capacitor is in a charging state, the capacitor voltage increment is expressed as:

[0042]

[0043] Assuming that the parameters of the bridge arm submodules are consistent, according to formula (11), T0-T k The average capacitor voltage increment of the bridge arm at the moment ΔU c_ava Expressed as:

[0044]

[0045] Since T0-T k It is a few control cycles, and the time is very short, so it is considered that T0-T k The maximum capacitor voltage increment of the bridge arm at the moment ΔU c_max , the average capacitance voltage increment of the bridge arm ΔU c_ava and the minimum capacitance voltage increment of the bridge arm ΔU c_minThe same, that is:

[0046] ΔU c_ava ≈ΔU c_min ≈ΔU c_max (13)

[0047] Combining equations (3), (10)-(13), we get:

[0048]

[0049] Substituting formula (6) into formula (14), we get:

[0050]

[0051] From formula (15), we can see that the maximum unbalanced capacitance voltage U c_error It includes DC component, fundamental component and double frequency component.

[0052] Compared with the prior art, the present invention has the following beneficial effects: the present invention adopts an adaptive control strategy based on PI-PR hybrid, so that the capacitor voltage balancing control system has better dynamic and steady-state control performance, reduces the maximum unbalanced capacitor voltage control error of the bridge arm, and thus enhances the robustness of the converter system and the system's operational reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 A topological structure diagram of a three-phase modular multilevel converter according to a preferred embodiment of the present invention;

[0054] Figure 2 This is a topological diagram of the MMC submodule according to a preferred embodiment of the present invention;

[0055] Figure 3 Schematic diagram of three switch states of the MMC submodule in a preferred embodiment of the present invention;

[0056] Figure 4 This is a flowchart of triggering a capacitance voltage balancing strategy based on the incremental number of submodules according to a preferred embodiment of the present invention;

[0057] Figure 5 T0-T in the preferred embodiment of the present invention k The graph of the submodule capacitor voltage increment change at each moment;

[0058] Figure 6 This is a control block diagram of an adaptive control strategy according to a preferred embodiment of the present invention;

[0059] Figure 7 This is the structure of the MMC type DC transmission system according to the preferred embodiment of the present invention;

[0060] Figure 8This is a simulation waveform diagram of a conventional sorting voltage balancing strategy system in steady state according to a preferred embodiment of the present invention;

[0061] Figure 9 This is a simulation waveform diagram of the voltage balancing strategy system in steady state according to the preferred embodiment of the present invention;

[0062] Figure 10 This is a dynamic simulation waveform diagram of a traditional sorting voltage balancing strategy system according to a preferred embodiment of the present invention;

[0063] Figure 11 This is a simulation waveform diagram of the voltage balancing strategy system under dynamic conditions according to a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0064] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0065] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the present application belongs.

[0066] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application; as used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form, and it should be understood that when the terms "comprise" and / or "include" are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or their combinations.

[0067] Adaptive bridge arm capacitor voltage balancing method for high-power modular multilevel converters, reference Figures 1 to 11 Specifically, the three-phase modular multilevel converter (MMC) structure is as follows Figure 1 As shown, point O represents the zero potential reference point, and the voltage between the positive and negative DC bus is U dc The converter has six bridge arms, each of which consists of N identical submodules (SMs), bridge arm inductors (L), and bridge arm equivalent resistors (R). The upper and lower bridge arms of each phase are collectively called a phase unit.

[0068] The highly modular three-phase modular multilevel converter can easily adapt to different voltage and capacity scenarios by simply increasing or decreasing the number of submodules in each bridge arm. This facilitates scalable design, shortens project development cycles, reduces complexity, and lowers R&D costs. Unlike traditional VSC topologies, the three-phase modular multilevel converter distributes energy across the capacitors of each submodule, significantly reducing capacitor surge currents during DC-side faults and improving system fault protection and reliability.

[0069] There are three main submodule topologies: Half-Bridge SM (HBSM), Full-Bridge SM (FBSM), and Clamp-Double SM (CDSM). Compared to the latter two topologies, the Half-Bridge SM is widely used in practical projects due to its low losses, low cost, and simple control, although it cannot clear DC faults within the converter itself due to the freewheeling effect of the diodes.

[0070] Figure 2 The topological structure diagram of a half-bridge submodule is shown in Figure 1, where T1 and T2 represent insulated gate bipolar transistors, D1 and D2 represent anti-parallel diodes, and C0 represents the DC capacitor of the submodule. c Represents the capacitor voltage, u sm Represents the voltage across the submodule, i sm Represents the current flowing into the submodule. Figure 2 Obviously, each submodule is connected to the main circuit topology through AB series connection, and the MMC supports the bus voltage through the capacitor voltage in each submodule.

[0071] Under normal working conditions, T1 and T2 are in complementary switching state, turning on and off alternately. Figure 3 As shown, the submodule has three working states: locked state, engaged state, and cut-off state.

[0072] When both T1 and T2 are powered off, this state is called the latched state. Depending on the conduction status of anti-parallel diodes D1 and D2, the system operates in two modes: mode (a) and mode (b). In mode (a), D1 is on, and the submodule current flows through D1, charging the capacitor, resulting in an output voltage equal to the capacitor voltage. In mode (b), D2 is on, and the submodule current flows through D2, bypassing the capacitor, resulting in a zero output voltage.

[0073] When T1 is powered on and T2 is powered off, this state is called the active state. Depending on the direction of the submodule current flow, the device can be divided into two operating modes: mode (c) and mode (d). In mode (c), D1 is on while T1 is subject to reverse voltage. Despite the applied power-on signal, the submodule current flows through D1, charging the capacitor, resulting in the output voltage being the capacitor voltage. In mode (d), T1 is on while D1 is powered off due to the reverse voltage. The submodule current flows through T1, discharging the capacitor, resulting in the output voltage being the capacitor voltage.

[0074] When a shutdown signal is applied to T1 and a turn-on signal is applied to T2, this state is called the cut-off state. Based on the direction of the submodule current flow, there are two operating modes: mode (e) and mode (f). In mode (e), T2 is on, while D2 is in the off state due to the reverse voltage. The submodule current flows through T2, bypassing the capacitor, and the output voltage is 0. In mode (f), D2 is on, while T2 is in the reverse voltage. Despite the turn-on signal, it remains in the off state. The submodule current flows through D2, bypassing the capacitor, and the output voltage is 0.

[0075] The above analysis shows that when the submodule enters steady-state mode, only one transistor is in the on state. Furthermore, if T1 and D1 are considered s1, and T2 and D2 are considered s2, then when the submodule is in the on state, s1 is on and s2 is off, current can flow bidirectionally through s1, and the submodule's external voltage is the capacitor voltage. Similarly, when the submodule is in the off state, s1 is off and s2 is on, current can flow bidirectionally through s2, and the submodule's external voltage is zero. In the blocked state, however, the conduction of s1 and s2 is uncertain.

[0076] The total DC voltage control of the three-phase modular multilevel converter and the parallel structure of the three phase units can maintain DC voltage balance within the phase units. As the switching states of the upper and lower bridge arm submodules of the phase unit are rotated, the voltage balance between the upper and lower bridge arm submodules is also achieved. Therefore, the capacitor voltage balance control of the three-phase modular multilevel converter can be carried out on a per-bridge-arm basis.

[0077] The capacitor voltage balancing strategy based on the concept of submodule number increment is as follows: Figure 4 Compared with the traditional capacitor sorting voltage balancing method, this strategy can minimize the number of submodule changes and thus reduce the switching frequency. However, this strategy will cause some submodules to be in the charging or discharging state for a long time, and even cause output voltage distortion.

[0078] In order to better control the submodule switching frequency and submodule capacitor voltage balancing effect, it is necessary to analyze the relationship between the switching frequency and the capacitor voltage deviation. Figure 1 According to Kirchhoff's voltage-current law, we can get:

[0079]

[0080]

[0081] Where: j represents the three phases a, b, c (j = a, b, c); u pj ,u nj Respectively represents the sum of the voltages of the upper and lower bridge arm submodules of the three phases a, b, and c; U dc Indicates the DC side bus line voltage; ujo Respectively represent the voltage difference between the MMC three-phase AC output side and the neutral point O; i pj ,i nj Respectively represent the current of the upper and lower bridge arms of the three phases a, b, and c; i vj Indicates AC three-phase current measurement; i diffj Represents the internal current flowing through the upper and lower bridge arms simultaneously.

[0082] According to the analysis, the internal current i diffj The DC current component i during normal operation should be dc and AC circulating current component i cirj Composition can be expressed as:

[0083]

[0084] Where: o represents the fundamental angular frequency; δ0 represents the initial phase angle; θ0 represents the power factor angle.

[0085] The MMC AC output voltage can be expressed as:

[0086]

[0087] Where: m represents the voltage modulation coefficient; ω o represents the fundamental angular frequency; δ0 represents the initial phase angle.

[0088] Substituting equation (4) into equation (1), we can get the upper and lower bridge arm reference voltage u ref for:

[0089]

[0090] At this time, according to the Nearest Level Control (NLC) method, the number of bridge arm sub-modules can be obtained as follows:

[0091]

[0092] Among them: U c_ava represents the average operating voltage of the bridge arm submodule capacitor; round(·) indicates taking the integer closest to the calculated value in the brackets.

[0093] It is easy to know that the number of switches in the MMC consists of two parts, one part is used to provide the required AC output voltage, and the other part is used to balance the capacitor voltage.

[0094] According to the incremental number of bridge arm submodules in the next control cycle, the number of switches in the first part can be

[0095] Expressed as:

[0096] Δnref (T k )=n ref (T k )-n ref (T k-1 ) (twenty two)

[0097] Where: n ref (T k ), n ref (T k-1 ) represent the T k and T k-1 The number of bridge arm submodules put into operation during the control cycle.

[0098] Obviously, the change of the number of switches in this part is determined by the MMC topology and system parameters and is uncontrollable. At the same time, in order to achieve the voltage balance of the bridge arm capacitor, it is necessary to change n in each cycle. alt The number of switches of these submodules is determined by the submodule selection mechanism. alt Appropriate selection can achieve balanced control of capacitor voltage and frequency.

[0099] At this time, the number of submodule switches in each control cycle can be expressed as:

[0100]

[0101] Where: n swon Indicates the number of bridge arm submodules that are turned on; n swoff Indicates the number of bridge arm submodules closed; Δn ref Indicates the incremental number of bridge arm submodules; n alter Indicates the variable number of bridge arm submodules.

[0102] Define the maximum unbalanced capacitance voltage U of the bridge arm c_error is the maximum capacitance voltage difference of the bridge arm, and its expression is:

[0103] U c_error =U c_max -U c_min (twenty four)

[0104] Among them: U c_max , U c_min They represent the maximum capacitance voltage of the bridge arm and the minimum capacitance voltage of the bridge arm respectively.

[0105] like Figure 5 As shown, T0—T k The incremental change of the submodule capacitor voltage at the moment is composed of two parts. One part is the maximum unbalanced voltage U c_error , part of which is the minimum voltage increment ΔU c_min :

[0106] ΔU c_x =U c_error +ΔU c_min (25)

[0107] Where: ΔU c_x Indicates the capacitor voltage increment of the xth submodule.

[0108] Since T0-T k At the moment when the submodule x capacitor is in a charging state, the capacitor voltage increment can be expressed as:

[0109]

[0110] Assuming that the parameters of the bridge arm submodules are consistent, according to formula (11), T0-T k The average capacitor voltage increment of the bridge arm at the moment ΔU c_ava It can be expressed as:

[0111]

[0112] Since T0-T k It is a few control cycles, and the time is very short, so it can be approximately considered that T0-T k The maximum capacitor voltage increment of the bridge arm at the moment ΔU c_max , the average capacitance voltage increment of the bridge arm ΔU c_ava and the minimum capacitance voltage increment of the bridge arm ΔU c_min The same, that is:

[0113] ΔU c_ava ≈ΔU c_min ≈ΔU c_max (28)

[0114] Combining equations (3), (10)-(13), we can get:

[0115]

[0116] Substituting formula (6) into formula (14), we can obtain:

[0117]

[0118] From formula (15), it can be seen that the maximum unbalanced capacitance voltage U c_error In view of this, this paper designs an adaptive control strategy based on PI-PR hybrid to achieve the maximum unbalanced capacitor voltage U c_error The control block diagram of the balanced control of the switching frequency is as follows: Figure 6 shown.

[0119] The present invention proposes an adaptive control strategy for high-power MMC with reduced switching frequency without adding additional hardware circuits, so as to achieve the maximum unbalanced capacitor voltage U c_error effective control.

[0120] The present invention builds the following in MATLAB / Simulink Figure 7 The two-terminal MMC VSC-HVDC system shown in the figure has been verified to be feasible through simulation. The parameters of the MMC and control system in the simulation are shown in Table 1.

[0121] Table 1 Simulation system parameters

[0122]

[0123] The feasibility of the present invention will be verified by simulation from the following two aspects: (1) Comparison of simulation results under steady state of the system. (2) Comparison of simulation results under variable power of the system.

[0124] (1) Comparison of simulation results under system steady state

[0125] The simulation verification takes the upper bridge arm of phase A on the inverter side as the research object, and uses the traditional sorting voltage balancing control strategy and the voltage balancing control strategy proposed in this invention for simulation comparison. Figure 8 The waveform of the bridge arm submodule capacitor voltage fluctuation, the average switching frequency of the bridge arm, and the maximum unbalanced capacitor voltage U of the bridge arm under the traditional sorting voltage balancing control strategy are shown in Figure 2. c_error . Figure 9 The voltage fluctuation waveform of each submodule capacitor voltage of the bridge arm under the voltage balancing control strategy proposed in the present invention, the average switching frequency waveform of the bridge arm, and the maximum unbalanced capacitor voltage U of the bridge arm are shown in Figure 2. c_error Variable number of waveforms and submodules n alter Waveform diagram, given the maximum unbalanced capacitor voltage of the bridge arm Take 3.5, 5, and 8 respectively.

[0126] (2) Comparison of simulation results under system power variation

[0127] The simulation verification takes the upper bridge arm of phase A on the inverter side as the research object. At 0.7s, the system active power is increased from 0.6MW to 1MW. The results are as follows Figure 10-11 shown. Figure 10 The waveform of the bridge arm submodule capacitor voltage fluctuation, the average switching frequency of the bridge arm, and the maximum unbalanced capacitor voltage U of the bridge arm under the traditional sorting voltage balancing control strategy are shown in Figure 2. c_error . Figure 11 The voltage fluctuation waveform of each submodule capacitor voltage of the bridge arm under the voltage balancing control strategy proposed in the present invention, the average switching frequency waveform of the bridge arm, and the maximum unbalanced capacitor voltage U of the bridge arm are shown in Figure 2. c_errorVariable number of waveforms and submodules n alter Waveform diagram, given the maximum unbalanced capacitor voltage of the bridge arm Take 4 and 8 respectively.

[0128] In summary, as shown by the above simulation results, this method can achieve balanced control of the switching frequency and voltage of the sub-modules in both dynamic and steady-state conditions, and has good dynamic and steady-state performance and control accuracy, meeting the actual needs of the project.

Claims

1. A method for adaptive bridge arm capacitor voltage balancing in a high-power modular multi-level converter, characterized in that: The three-phase modular multilevel converter MMC includes six bridge arms, each of which is composed of N identical submodules SM, a bridge arm inductor L, and a bridge arm equivalent resistance R. The upper and lower bridge arms of each phase are collectively referred to as a phase unit. The voltage between the positive and negative DC bus is U dc , the center point of the zero potential reference point is the zero potential reference point O; It also includes a half-bridge submodule; the half-bridge submodule includes a first insulated gate bipolar transistor T1, a second insulated gate bipolar transistor T2, a first anti-parallel diode D1, a second anti-parallel diode D2, a submodule DC capacitor C0 and a capacitor voltage u c The input submodule current i between the first insulated gate bipolar transistor T1 and the second insulated gate bipolar transistor T2 sm , submodule current i sm The voltage u across the half-bridge module is between the input point and the emitter of the second insulated gate bipolar transistor T2. sm , each half-bridge sub-module passes the sub-module current i sm The input point of the bus is connected in series with the emitter of the second insulated gate bipolar transistor T2 to the main circuit topology, and the three-phase modular multilevel converter MMC supports the bus voltage through the capacitor voltage in each half-bridge sub-module; The number of switches in the three-phase modular multilevel converter (MMC) consists of two parts: one for providing the required AC output voltage and the other for balancing the capacitor voltage; According to the incremental number of bridge arm submodules in the next control cycle, the number of switches in the first part is expressed as: Δn ref (T k )=n ref (T k )-n ref (T k-1 ) (7) Where: n ref (T k ), n ref (T k-1 ) represent the T k and T k-1 The number of bridge arm submodules put into operation during the control cycle; Each cycle needs to change n alter The switch status of the submodules; the number of switches of these submodules is determined by the submodule selection mechanism; by alter Appropriate selection achieves balanced control of capacitor voltage and frequency; At this time, the number of submodule switches in each control cycle is expressed as: Where: n swon Indicates the number of bridge arm submodules that are turned on; n swoff Indicates the number of bridge arm submodules that are closed; Δn ref Indicates the incremental number of bridge arm submodules; n alter Indicates the variable number of bridge arm submodules; Define the maximum unbalanced capacitance voltage U of the bridge arm c_error is the maximum capacitance voltage difference of the bridge arm, and its expression is: IN c_error =U c_max -IN c_min (9) Among them: U c_max , U c_min Represent the maximum capacitance voltage of the bridge arm and the minimum capacitance voltage of the bridge arm respectively; From formula (15), we can see that the maximum unbalanced capacitance voltage U c_error It includes DC component, fundamental component and double frequency component.

2. The method for adaptive bridge arm capacitor voltage balancing of a high-power modular multi-level converter according to claim 1, characterized in that: Under normal working conditions, the first insulated gate bipolar transistor T1 and the second insulated gate bipolar transistor T2 are in complementary switching states, and are alternately turned on and off; the half-bridge submodule has three working states: locked state, switched-on state, and cut-off state.

3. The method for adaptive bridge arm capacitor voltage balancing of a high-power modular multi-level converter according to claim 2, characterized in that: When the first insulated gate bipolar transistor T1 and the second insulated gate bipolar transistor T2 are both applied with a shutdown signal, this is called a locked state. According to the conduction status of the first anti-parallel diode D1 and the second anti-parallel diode D2, there are two operating modes, namely a first mode A and a second mode B. In the first mode B, the first anti-parallel diode D1 is turned on, and the current of the half-bridge sub-module charges the capacitor through the first anti-parallel diode D1, and the output voltage is the capacitor voltage. In the second mode B, the second anti-parallel diode D2 is turned on, and the current of the half-bridge sub-module bypasses the capacitor through the second anti-parallel diode D2, and the output voltage is 0.

4. The method for adaptive bridge arm capacitor voltage balancing of a high-power modular multi-level converter according to claim 2, characterized in that: When a turn-on signal is applied to the first insulated gate bipolar transistor T1 and a turn-off signal is applied to the second insulated gate bipolar transistor T2, this is called the on-state. Based on the direction of current flow in the half-bridge sub-module, the two operating modes are divided into a third mode C and a fourth mode D. In the third mode C, the first anti-parallel diode D1 is turned on, while the first insulated gate bipolar transistor T1 is subjected to a reverse voltage. Despite the application of the turn-on signal, it remains in the off state. The sub-module current charges the capacitor through the first anti-parallel diode D1, and the output voltage is the capacitor voltage. In the fourth mode D, the first insulated gate bipolar transistor T1 is turned on, while the first anti-parallel diode D1 is in the off state due to the reverse voltage. The half-bridge sub-module current discharges the capacitor through the first insulated gate bipolar transistor T1, and the output voltage is the capacitor voltage.

5. The method for adaptive bridge arm capacitor voltage balancing of a high-power modular multi-level converter according to claim 2, characterized in that: When a shutdown signal is applied to the first insulated gate bipolar transistor T1 and a turn-on signal is applied to the second insulated gate bipolar transistor T2, this state is called a cut-off state. According to the direction of current flow in the half-bridge sub-module, the operation is divided into two operating modes, namely, the fifth mode e and the sixth mode f. In the fifth mode e, the second insulated gate bipolar transistor T2 is turned on, while the second anti-parallel diode D2 is in the off state due to the reverse voltage. The current of the half-bridge sub-module bypasses the capacitor through the second insulated gate bipolar transistor T2, and the output voltage is 0. In the sixth mode f, the second anti-parallel diode D2 is turned on, while the second insulated gate bipolar transistor T2 is subjected to the reverse voltage. Despite the application of the turn-on signal, it is still in the off state. The current of the half-bridge sub-module bypasses the capacitor through the second anti-parallel diode D2, and the output voltage is 0.

6. The method for adaptive bridge arm capacitor voltage balancing of a high-power modular multi-level converter according to claim 2, characterized in that: Analyzing the relationship between switching frequency and capacitor voltage deviation, according to Kirchhoff's voltage-current law, we can get: Among them: j represents the three phases a, b, c, j = a, b, c; u pj ,u nj Respectively represents the sum of the voltages of the upper and lower bridge arm submodules of the three phases a, b, and c; U dc Indicates the DC side bus line voltage; u jo Respectively represent the voltage difference between the MMC three-phase AC output side and the neutral point O; i pj ,i nj Respectively represent the current of the upper and lower bridge arms of the three phases a, b, and c; i vj Indicates AC three-phase current measurement; i diffj Indicates the internal current flowing through the upper and lower bridge arms simultaneously; According to the analysis, the internal current i diffj The DC current component i during normal operation should be dc and AC circulating current component i cirj Composition, expressed as: Where: ω0 represents the fundamental angular frequency; δ0 represents the initial phase angle; θ0 represents the power factor angle; The AC output voltage of the three-phase modular multilevel converter MMC is expressed as: Where: m represents the voltage modulation coefficient; ω o represents the fundamental angular frequency; δ0 represents the initial phase angle; Substituting equation (4) into equation (1), we can get the upper and lower bridge arm reference voltage u ref for: At this time, according to the nearest level control method, the number of bridge arm sub-modules is: Among them: U c_ava represents the average operating voltage of the bridge arm submodule capacitor; round(·) indicates taking the integer closest to the calculated value in the brackets.

7. The method for adaptive bridge arm capacitor voltage balancing of a high-power modular multi-level converter according to claim 1, characterized in that: The incremental change of the capacitor voltage of the half-bridge submodule consists of two parts. One part is the maximum unbalanced voltage U c_error , part of which is the minimum voltage increment ΔU c_min : ΔU c_x =U c_error +ΔU c_min (10) Where: ΔU c_x Indicates the capacitor voltage increment of the xth submodule; Since T0-T k At the moment when the submodule x capacitor is in a charging state, the capacitor voltage increment is expressed as: Assuming that the parameters of the bridge arm submodules are consistent, according to formula (11), T0-T k The average capacitor voltage increment of the bridge arm at the moment ΔU c_ava Expressed as: Since T0-T k It is a few control cycles, and the time is very short, so it is considered that T0-T k The maximum capacitor voltage increment of the bridge arm at the moment ΔU c_max , the average capacitance voltage increment of the bridge arm ΔU c_ava and the minimum capacitance voltage increment of the bridge arm ΔU c_min The same, that is: ΔU c_ava ≈ΔU c_min ≈ΔU c_max (13) Combining equations (3), (10)-(13), we get: Substituting equation (6) into equation (14), we obtain equation (15).

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