Analog-to-digital conversion calibration circuit, multi-channel analog-to-digital conversion circuit, chip, and computing device

Abstract

The embodiment of the present disclosure discloses an analog-to-digital conversion calibration circuit, a multi-channel analog-to-digital conversion circuit, a chip and a computing device, wherein the analog-to-digital conversion calibration circuit comprises an analog-to-digital converter, a digital-to-analog converter and a digital register, the analog-to-digital converter comprises a logic control unit; the analog-to-digital converter is used for outputting a digital mismatch signal when an analog input signal is a preset value in a calibration mode; the logic control unit generates a digital calibration signal according to the digital mismatch signal and stores the digital calibration signal in the digital register; the digital-to-analog converter converts the digital calibration signal into an analog calibration signal and sends it to the analog-to-digital converter; the analog-to-digital converter is further used for converting the analog calibration signal into a digital output signal; and the logic control unit is further used for adjusting the digital calibration signal in the digital register so that the digital output signal reaches a preset expected digital output signal. The embodiment of the present disclosure simplifies the structure of the calibration circuit, reduces the area and power consumption of the calibration circuit.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit design technology, and in particular to an analog-to-digital conversion calibration circuit, a multiplex analog-to-digital conversion circuit, a chip, and a computing device. Background Technology

[0002] An analog-to-digital converter (ADC) is used to convert analog signals into digital signals, and it has applications in many fields. However, due to various factors such as manufacturing processes and material differences, ADCs often suffer from some degree of mismatch, meaning that when the input analog signal is zero, the output digital signal is not zero.

[0003] In some application areas, mismatch between analog-to-digital converters (ADCs) should be avoided as much as possible. For example, in-memory computing architectures based on analog signals or mixed analog-to-digital signals have high energy efficiency advantages when implementing multiply-accumulate (MAC) calculations in low-to-medium precision computing scenarios (such as low-to-medium precision deep learning scenarios). Analog-to-memory computing processes rely on analog signals, and to achieve a universal interface, highly parallel ADCs are typically required to digitize the signals. Mismatch between multiple ADCs will impair the linearity of the entire in-memory array.

[0004] Current calibration schemes for digital-to-analog converters typically involve adding a digital calibration circuit after the converter. This circuit executes a calibration algorithm to calibrate the digital signal output by the converter, thereby reducing the impact of mismatch. Summary of the Invention

[0005] Embodiments of this disclosure provide an analog-to-digital converter (ADC) calibration circuit, comprising: an ADC, a digital-to-analog converter (DAC), and a digital register. The ADC includes a logic control unit. The ADC is configured to output a digital mismatch signal in calibration mode when the analog input signal is a preset value. The logic control unit is configured to generate a digital calibration signal based on the digital mismatch signal and store the digital calibration signal in the digital register. The DAC converts the digital calibration signal into an analog calibration signal and sends the analog calibration signal to the ADC. The ADC further converts the analog calibration signal into a digital output signal. The logic control unit further adjusts the digital calibration signal in the digital register to achieve a preset desired digital output signal.

[0006] In some embodiments, the digital-to-analog converter is further configured to: read the digital calibration signal in the digital register and convert the digital calibration signal into an analog calibration signal when the current mode of the circuit is the normal application mode; the analog-to-digital converter is further configured to: receive the analog input signal and superimpose the analog calibration signal and the analog input signal to obtain the calibrated analog signal; convert the calibrated analog signal into a calibrated digital signal and output the calibrated digital signal.

[0007] In some embodiments, the analog-to-digital converter further includes a comparator and a digital-to-analog conversion unit, wherein a first input terminal of the comparator is used to receive an analog reference signal output by the digital-to-analog conversion unit, and a second input terminal of the comparator is used to receive a calibrated analog signal obtained by superimposing an analog input signal and an analog calibration signal.

[0008] In some embodiments, the bit width of the digital register is the same as the bit width of the analog-to-digital converter.

[0009] In some embodiments, the analog-to-digital converter is further configured to: enter a calibration mode in response to circuit activation; and exit the calibration mode in response to the digital output signal reaching the desired digital output signal.

[0010] In some embodiments, the analog-to-digital converter is further configured to: enter calibration mode in response to receiving a mode selection signal indicating entry into calibration mode; and exit calibration mode in response to the digital output signal reaching the desired digital output signal.

[0011] According to another aspect of the present disclosure, a multi-channel analog-to-digital converter (ADC) circuit is provided. The circuit includes: a preset number of ADCs, a preset number of digital registers, and a multi-channel ADC. The multi-channel ADCs are resistive ADCs, and each of the preset number of single-channel ADCs includes a common resistor network and a decoding unit. Each ADC corresponds to a digital register and a single-channel ADC. The corresponding ADCs, digital registers, and single-channel ADCs constitute the aforementioned ADC calibration circuit.

[0012] In some embodiments, the multiplexed digital-to-analog converter and the preset number of digital registers are disposed between the preset number of analog-to-digital converters.

[0013] According to another aspect of the present disclosure, a chip is provided that includes the analog-to-digital conversion calibration circuit or the multiplex analog-to-digital conversion circuit described above.

[0014] According to another aspect of the present disclosure, a computing device is provided, the computing device including the above-described chip.

[0015] The analog-to-digital converter (ADC) calibration circuit, multi-channel ADC circuit, chip, and computing device provided in the above embodiments of this disclosure, by setting up an ADC, a digital-to-analog converter (DAC), and a digital register, when the analog input signal is a preset value, the ADC outputs a digital mismatch signal. The logic control unit generates a digital calibration signal based on the digital mismatch signal and stores the digital calibration signal in the digital register. The DAC converts the digital calibration signal into an analog calibration signal and sends the analog calibration signal to the ADC. The ADC converts the analog calibration signal into a digital output signal. The logic control unit further adjusts the digital calibration signal in the digital register so that the digital output signal reaches the preset desired digital output signal. Thus, calibration is performed using the ADC and based on the analog calibration signal before the ADC outputs the digital signal, without the need to set up a digital calibration circuit and run a digital calibration algorithm. Moreover, the calibration circuit reuses the logic control unit of the ADC, which greatly simplifies the structure of the calibration circuit and reduces the area and power consumption of the calibration circuit.

[0016] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0017] The above and other objects, features, and advantages of this disclosure will become more apparent from the more detailed description of the embodiments thereof in conjunction with the accompanying drawings. The drawings are provided to further illustrate the embodiments of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the disclosure and do not constitute a limitation thereof. In the drawings, the same reference numerals generally represent the same components or steps;

[0018] Figure 1 This is a schematic diagram of the structure of an analog-to-digital conversion calibration circuit provided in an exemplary embodiment of this disclosure;

[0019] Figure 2 This is another schematic diagram of the analog-to-digital conversion calibration circuit provided in an exemplary embodiment of this disclosure;

[0020] Figure 3 This is a schematic diagram of the structure of a multiplexed analog-to-digital converter circuit provided in an exemplary embodiment of the present disclosure. Detailed Implementation

[0021] Hereinafter, exemplary embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of the present disclosure, and not all embodiments of the present disclosure, and it should be understood that the present disclosure is not limited to the exemplary embodiments described herein.

[0022] It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of this disclosure.

[0023] Those skilled in the art will understand that the terms "first," "second," etc., in the embodiments of this disclosure are only used to distinguish different steps, devices, or modules, and do not represent any specific technical meaning, nor do they indicate a necessary logical order between them.

[0024] It should also be understood that in the embodiments disclosed herein, "a plurality of" may refer to two or more, and "at least one" may refer to one, two or more.

[0025] It should also be understood that any component, data or structure mentioned in the embodiments of this disclosure can generally be understood as one or more unless expressly defined or given to the contrary in the context.

[0026] Furthermore, the term "and / or" in this disclosure is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this disclosure generally indicates that the preceding and following related objects have an "or" relationship.

[0027] It should also be understood that the description of the various embodiments in this disclosure emphasizes the differences between the various embodiments, and the similarities or similarities can be referred to each other. For the sake of brevity, they will not be described in detail.

[0028] At the same time, it should be understood that, for ease of description, the dimensions of the various parts shown in the accompanying drawings are not drawn according to actual scale.

[0029] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this disclosure or its application or use.

[0030] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0031] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0032] Application Overview

[0033] Current calibration schemes for digital-to-analog converters typically involve adding a digital calibration circuit after the converter. This circuit executes a calibration algorithm to calibrate the digital signal output by the converter, thereby reducing the impact of mismatch.

[0034] However, existing digital calibration circuits are set up independently of the analog-to-digital converter. Digital calibration circuits usually require a large area and have a large power consumption when operating at high speed. In in-memory computing scenarios with high parallelism of ADCs, this results in high power consumption and a large area occupation.

[0035] Exemplary Structure

[0036] Figure 1 This is a schematic diagram of the structure of an analog-to-digital conversion calibration circuit provided in an exemplary embodiment of this disclosure. The various components of this circuit can be integrated into a single chip or disposed in different chips or circuit boards, with data communication links established between these chips or circuit boards.

[0037] like Figure 1 As shown, the circuit includes an analog-to-digital converter 101, a digital-to-analog converter 102, and a digital register 103. The analog-to-digital converter 101 includes a logic control unit 1011.

[0038] In this embodiment, the analog-to-digital converter 101 is used in calibration mode to output a digital mismatch signal when the analog input signal is a preset value. The preset value can be set arbitrarily, but is typically zero. The digital mismatch signal is a signal that has a certain error compared to the expected signal when the analog input signal is the preset value. For example, when the analog input signal is zero, the expected digital output signal of the converter is zero, but due to factors such as the manufacturing process of the converter 101, the actual output digital signal is not zero; this actual output digital signal is the digital mismatch signal.

[0039] The aforementioned logic control unit 1011 is used to provide logic control signals to the analog-to-digital converter 101. For example, the analog-to-digital converter 101 may be a SAR-ADC (Successive Approximation Register ADC). The logic control unit 1011 included in the SAR-ADC is used to generate digital signals sequentially, convert the digital signals into analog signals, compare the analog signals with the analog input signals, and output digital signals bit by bit according to the comparison result.

[0040] In this embodiment, the logic control unit 1011 is used to generate a digital calibration signal based on the digital mismatch signal and store the digital calibration signal in the digital register 103. Besides performing logic control and outputting digital signals during normal operation of the analog-to-digital converter 101, the logic control unit 1011 can also be multiplexed into the calibration circuit in this embodiment, i.e., generating a digital calibration signal and storing it in the digital register 103. Typically, the digital calibration signal gradually changes from an initial signal (e.g., 0). The logic control unit 1011 can detect the value of the digital signal output by the analog-to-digital converter 101 in real time, and the digital calibration signal stops changing when the desired digital output signal (e.g., 0) is reached.

[0041] In this embodiment, a digital-to-analog converter (DAC) 102 is used to convert a digital calibration signal into an analog calibration signal and send the analog calibration signal to an analog-to-digital converter 101. The DAC 102 can be of various types, such as a resistive DAC or a capacitive DAC.

[0042] In this embodiment, the analog-to-digital converter 101 is further used to convert the analog calibration signal into a digital output signal. Since the current analog input signal is a fixed preset value, the digital output signal at this time represents the magnitude of the analog calibration signal.

[0043] In this embodiment, the logic control unit 1011 is further used to adjust the digital calibration signal in the digital register 103 so that the digital output signal reaches the preset desired digital output signal. The logic control unit 1011 can monitor the value of the digital output signal in real time. If the digital output signal does not reach the desired digital output signal, the logic control unit 1011 adjusts the digital calibration signal and stores the adjusted digital calibration signal in the digital register 103. If the digital output signal reaches the desired digital output signal, the logic control unit 101 stops updating the digital output signal stored in the digital register 103. Subsequently, during the normal operation of the analog-to-digital converter 101, the digital-to-analog converter 102 continuously outputs analog calibration signals to the analog-to-digital converter 101 according to the most recently updated digital calibration signal in the digital register 103, thereby canceling the digital mismatch signal and achieving the purpose of calibrating the analog-to-digital converter 101.

[0044] In this embodiment, the analog-to-digital converter (ADC) performs various functions in calibration mode. Specifically, in calibration mode, the ADC's logic control unit generates a digital calibration signal and stores it in a digital register, and adjusts the digital calibration signal to achieve the desired digital output signal value. Optionally, the ADC calibration circuit provided in this embodiment can be applied to in-memory computing circuits based on analog signals. This involves repeatedly setting multiple sets of the circuit provided in this embodiment to calibrate the ADC within the in-memory computing unit array, thereby reducing the area and power consumption of the calibrable in-memory computing circuit.

[0045] The circuit provided in the above embodiments of this disclosure, by setting up an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), and a digital register, when the analog input signal is a preset value, the ADC outputs a digital mismatch signal. The logic control unit generates a digital calibration signal based on the digital mismatch signal and stores the digital calibration signal in the digital register. The DAC converts the digital calibration signal into an analog calibration signal and sends the analog calibration signal to the ADC. The ADC converts the analog calibration signal into a digital output signal. The logic control unit further adjusts the digital calibration signal in the digital register so that the digital output signal reaches the preset desired digital output signal. Thus, calibration is performed using the ADC and based on the analog calibration signal before the ADC outputs the digital signal, without the need to set up a digital calibration circuit and run a digital calibration algorithm. Moreover, the calibration circuit reuses the logic control unit of the ADC, which greatly simplifies the structure of the calibration circuit and reduces the area and power consumption of the calibration circuit.

[0046] In some alternative implementations, the analog-to-digital converter 101 is further used for:

[0047] Upon activation of this circuit, calibration mode is entered;

[0048] When the digital output signal reaches the desired digital output signal, exit calibration mode.

[0049] That is, each time the circuit is started, it automatically enters calibration mode to calibrate the analog-to-digital converter. After calibration is completed, it exits calibration mode.

[0050] This embodiment automatically enters calibration mode after each startup, which enables the analog-to-digital converter to more accurately eliminate output data mismatch during normal application, thereby improving the conversion accuracy of the analog-to-digital converter.

[0051] In some alternative implementations, the analog-to-digital converter 101 is further used for:

[0052] Upon receiving a mode selection signal indicating that calibration mode has been entered, the system enters calibration mode.

[0053] When the digital output signal reaches the desired digital output signal, exit calibration mode.

[0054] The aforementioned mode selection signal can be sent by an external controller, meaning that the analog-to-digital converter is calibrated under the control of an external controller.

[0055] This embodiment controls the analog-to-digital converter to enter calibration mode by receiving a mode selection signal, which allows for more flexible control of the analog-to-digital converter during calibration and improves the convenience of operating the circuit.

[0056] Optionally, digital register 103 can be a volatile register. Since volatile registers cannot retain data stored before startup, they can automatically enter calibration mode each time the circuit starts up, and exit calibration mode after calibration is complete. Digital register 103 can also be a non-volatile register, meaning that after one calibration, the digital calibration signal is stored permanently, eliminating the need for subsequent calibrations. The digital-to-analog converter 102 directly reads the digital calibration signal from digital register 103. When digital register 103 is a non-volatile register, the analog-to-digital converter can automatically enter calibration mode after each startup; alternatively, it can enter calibration mode at any time under the control of the aforementioned mode selection signal, eliminating the need to enter calibration mode after each startup.

[0057] In some alternative implementations, the digital-to-analog converter 102 is further used for:

[0058] When the circuit is in normal application mode, the digital calibration signal in digital register 103 is read and converted into an analog calibration signal.

[0059] Specifically, the normal application mode is the mode in which the analog-to-digital converter 101 operates normally after calibration. In the normal application mode, the logic control unit no longer stores digital calibration signals into the digital register.

[0060] Optionally, the circuit can automatically enter calibration mode after startup, execute the calibration process described in the above embodiments, and automatically enter normal application mode after calibration is completed. Alternatively, the circuit can receive a mode selection signal sent by an external controller. That is, when the analog-to-digital converter 101 receives a mode selection signal indicating entry into calibration mode, it executes the calibration process described in the above embodiments; when the analog-to-digital converter 101 receives a mode selection signal indicating entry into normal application mode, the logic control unit 1011 stops outputting digital calibration signals and executes normal analog-to-digital conversion logic.

[0061] The analog-to-digital converter 101 is further used for:

[0062] The analog input signal is received, and the analog calibration signal and the analog input signal are superimposed to obtain the calibrated analog signal.

[0063] The calibrated analog signal is converted into a calibrated digital signal and then output.

[0064] Specifically, the superposition of the analog calibration signal and the analog input signal can be achieved through the circuitry inside the analog-to-digital converter 101. For example, an analog adder circuit for superimposing analog signals can be provided inside the analog-to-digital converter 101 to superimpose the analog calibration signal and the analog input signal.

[0065] In this embodiment, when the circuit is in normal application mode, the digital-to-analog converter directly outputs an analog calibration signal to the analog-to-digital converter based on the digital calibration signal in the digital register. This cancels out the digital mismatch signal output by the analog-to-digital converter, thereby reducing the area and power consumption of the calibration circuit and further outputting a high-precision calibrated digital signal.

[0066] In some alternative implementations, such as Figure 2 As shown, the analog-to-digital converter 101 also includes a comparator 1012 and a digital-to-analog conversion unit 1013. The first input terminal of the comparator is used to receive the analog reference signal output by the digital-to-analog conversion unit, and the second input terminal of the comparator is used to receive the calibrated analog signal after the analog input signal and the analog calibration signal are superimposed.

[0067] like Figure 2 As shown, based on the principle of successive approximation register-type ADC, the logic control unit 1011 inputs a digital signal to the digital-to-analog converter unit 1013 through successive shifts. The digital-to-analog converter unit 1013 outputs an analog reference signal successively. The comparator 1012 is used to compare the above-mentioned calibrated analog signal and the analog reference signal. The logic control unit 1011 obtains a digital signal based on the comparison result. After multiple shifts, conversions, and comparisons, a digital output signal is obtained.

[0068] This embodiment, by superimposing the analog input signal and the analog calibration signal and comparing them with the analog reference signal generated inside the analog-to-digital converter, can maximize the use of the analog-to-digital converter's own structure and output a calibrated digital signal, which helps to improve the area utilization of the calibration circuit and further simplify the structure of the calibration circuit.

[0069] In some alternative implementations, the bit width of digital register 103 is the same as the bit width of analog-to-digital converter 101. The bit width of analog-to-digital converter 101 is the bit width of the digital signal output by analog-to-digital converter 101. The bit width of digital register 103 is the bit width of the data stored in digital register 103.

[0070] This embodiment sets the bit width of the digital register to be the same as that of the analog-to-digital converter, allowing the digital register to directly store the digital calibration signal generated by the logic control unit. This further makes full use of the structure of the analog-to-digital converter, which helps to further improve the integration of the calibration circuit and reduce the area and power consumption of the calibration circuit.

[0071] Figure 3 This is a schematic diagram of the structure of a multiplexed analog-to-digital converter circuit provided in an exemplary embodiment of this disclosure. The various components of this circuit can be integrated into a single chip or disposed in different chips or circuit boards, establishing data communication links between these chips or circuit boards.

[0072] like Figure 3 As shown, the circuit includes: a preset number of analog-to-digital converters 301, a preset number of digital registers 302, and a multiplex digital-to-analog converter 303;

[0073] The multi-channel digital-to-analog converter 303 is a resistive digital-to-analog converter, and the multi-channel digital-to-analog converter 303 includes a preset number of single-channel digital-to-analog converters, each of which includes a common resistor network and a decoding unit. For example... Figure 3 As shown, the common resistor network 3031 and the decoding unit 3032 constitute a single-channel digital-to-analog converter, and the common resistor network 3031 and the decoding unit 3033 constitute another single-channel digital-to-analog converter.

[0074] Each of the preset number of analog-to-digital converters 301 corresponds to a digital register and a single-channel digital-to-analog converter; the corresponding analog-to-digital converters, digital registers and single-channel digital-to-analog converters constitute the analog-to-digital conversion calibration circuit described in the above embodiments.

[0075] Based on the principle of resistive digital-to-analog converters (DACs), the decoding unit receives the digital calibration signal output by the corresponding DAC. The decoding unit can include multiple switches, the number of which is the same as the number of bits in the digital calibration signal, and each switch is connected to a different node in the resistor network. The decoding unit sets the on / off state of each switch according to the individual bits of the digital calibration signal, and then uses the voltage division effect of the resistor network to output the corresponding analog calibration signal.

[0076] The preset quantity can be set arbitrarily; typically, the preset quantity is 2, i.e. Figure 3 As shown, a set of analog-to-digital converters, two digital registers, and a multi-channel digital-to-analog converter are configured.

[0077] like Figure 3As shown, a multi-channel digital-to-analog converter (DAC) 303 is provided between the two analog-to-digital converters (i.e., 3011 and 3012). The multi-channel DAC 303 includes a common resistor network 3031. The two single-channel DACs included in the multi-channel DAC can simultaneously read digital calibration signals CD0 and CD1 from two digital registers respectively. That is, a single-channel DAC composed of decoding unit 3032 and common resistor network 3031 performs digital-to-analog conversion on CD1 and outputs an analog calibration signal CA0. The other single-channel DAC composed of decoding unit 3033 and common resistor network 3031 performs digital-to-analog conversion on CD2 and outputs an analog calibration signal CA1. The two DACs receive the analog calibration signals respectively, and superimpose them with the input analog input signals IN0 and IN1 to output calibrated digital signals D0 and D1.

[0078] Optionally, the multi-channel analog-to-digital converter circuit provided in this embodiment can be applied to in-memory computing circuits based on analog signals, that is, multiple sets of the circuits provided in this embodiment can be repeatedly set to reduce the area and power consumption of the calibrable in-memory computing circuit.

[0079] The circuits provided in the above embodiments of this disclosure share a single multi-channel analog-to-digital converter (ADC). The ADC outputs multiple analog calibration signals through a common resistor network and a preset number of decoding units, thereby improving the integration of the ADC circuit with calibration function and helping to reduce the area and power consumption of the ADC circuit.

[0080] In some optional implementations, multiplexed digital-to-analog converters and a preset number of digital registers are positioned between a preset number of analog-to-digital converters. For example... Figure 3 As shown, a multi-channel digital-to-analog converter 303 and a preset number of digital registers 302 are disposed between analog-to-digital converters 3011 and 3012.

[0081] This embodiment, by placing a multi-channel digital-to-analog converter and a preset number of digital registers among a preset number of analog-to-digital converters, enables the multi-channel analog-to-digital converters to share a single multi-channel analog-to-digital converter for calibration, and keeps the distance between the multi-channel analog-to-digital converters as close as possible, thereby further improving the circuit integration and helping to reduce the circuit area.

[0082] Embodiments of this disclosure also provide a chip on which an analog-to-digital conversion calibration circuit or a multi-channel analog-to-digital conversion circuit is integrated. Technical details of the analog-to-digital conversion calibration circuit and the multi-channel analog-to-digital conversion circuit are as follows: Figures 1-3 As shown in the relevant descriptions, further details will not be provided here.

[0083] Embodiments of this disclosure also provide a computing device including the chip described in the above embodiments. Furthermore, the computing device may also include an input device, an output device, and necessary memory. The input device may include devices such as a mouse, keyboard, touchscreen, or communication network connector for inputting analog input signals. The output device may include devices such as a display, printer, and communication networks and their connected remote output devices for outputting digital output signals and calculation results based on the digital output signals. The memory is used to store data input by the input devices, as well as data generated during the operation of the analog-to-digital conversion calibration circuit or the multiplexed analog-to-digital conversion circuit. The memory may include volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc.

[0084] The basic principles of this disclosure have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.

[0085] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0086] The block diagrams of devices, apparatuses, devices, and systems disclosed herein are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as “comprising,” “including,” “having,” etc., are open-ended terms meaning “including but not limited to,” and are used interchangeably with them. The terms “or” and “and” as used herein refer to the terms “and / or,” and are used interchangeably with them unless the context clearly indicates otherwise. The term “such as” as used herein refers to the phrase “such as but not limited to,” and is used interchangeably with it.

[0087] The circuits of this disclosure may be implemented in many ways. For example, they may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above-described order of steps of the method in the circuit is for illustrative purposes only, and the steps of the method of this disclosure are not limited to the order specifically described above, unless otherwise specifically stated. Furthermore, in some embodiments, this disclosure may also be implemented as a program recorded on a recording medium, the program including machine-readable instructions for implementing the functions of the circuits according to this disclosure. Thus, this disclosure also covers recording media storing programs for performing the functions of the circuits according to this disclosure.

[0088] It should also be noted that in the circuits of this disclosure, the components or steps can be decomposed and / or recombined. These decompositions and / or recombinations should be considered as equivalent solutions of this disclosure.

[0089] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the aspects shown herein, but rather to be carried out within the widest scope consistent with the principles and novel features disclosed herein.

[0090] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this disclosure to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations therein.

Claims

1. An analog-to-digital conversion calibration circuit, comprising: An analog-to-digital converter, a digital-to-analog converter, and a digital register, wherein the analog-to-digital converter includes a logic control unit; The analog-to-digital converter is used to output a digital mismatch signal in calibration mode when the analog input signal is a preset value; The logic control unit is used to generate a digital calibration signal based on the digital mismatch signal and store the digital calibration signal in a digital register; The digital-to-analog converter is used to convert the digital calibration signal into an analog calibration signal, and send the analog calibration signal to the analog-to-digital converter; The analog-to-digital converter is further used to convert the analog calibration signal into a digital output signal; The logic control unit is further used to adjust the digital calibration signal in the digital register so that the digital output signal reaches the preset desired digital output signal; The analog-to-digital converter further includes a comparator and a digital-to-analog conversion unit, wherein the first input terminal of the comparator is used to receive the analog reference signal output by the digital-to-analog conversion unit, and the second input terminal of the comparator is used to receive the calibrated analog signal after superimposing the analog input signal and the analog calibration signal; the logic control unit is used to generate the digital output signal according to the comparison result output by the comparator.

2. The circuit according to claim 1, wherein, The digital-to-analog converter is further used for: When the current mode of the circuit is the normal application mode, the digital calibration signal in the digital register is read and the digital calibration signal is converted into an analog calibration signal; The analog-to-digital converter is further used for: Receive the analog input signal, and superimpose the analog calibration signal and the analog input signal to obtain the calibrated analog signal; The calibrated analog signal is converted into a calibrated digital signal and the calibrated digital signal is output.

3. The circuit according to claim 1, wherein, The bit width of the digital register is the same as the bit width of the analog-to-digital converter.

4. The circuit according to any one of claims 1-3, wherein, The analog-to-digital converter is further used for: In response to the activation of the circuit, the calibration mode is entered; In response to the digital output signal reaching the desired digital output signal, the calibration mode is exited.

5. The circuit according to any one of claims 1-3, wherein, The analog-to-digital converter is further used for: In response to receiving a mode selection signal indicating entry into calibration mode, the system enters the calibration mode; In response to the digital output signal reaching the desired digital output signal, the calibration mode is exited.

6. A multi-channel analog-to-digital converter circuit, comprising: A preset number of analog-to-digital converters, a preset number of digital registers, and multiplex digital-to-analog converters; The multi-channel digital-to-analog converter is a resistive digital-to-analog converter, and the multi-channel digital-to-analog converter includes a preset number of single-channel digital-to-analog converters. Each of the preset number of single-channel digital-to-analog converters includes a common resistor network and a decoding unit. Each of the preset number of analog-to-digital converters corresponds to a digital register and a single-channel digital-to-analog converter; The corresponding analog-to-digital converter, digital register, and single-channel digital-to-analog converter constitute the analog-to-digital conversion calibration circuit according to any one of claims 1-5.

7. The circuit according to claim 6, wherein, The multi-channel digital-to-analog converter and the preset number of digital registers are arranged between the preset number of analog-to-digital converters.

8. A chip, characterized in that, It includes the analog-to-digital conversion calibration circuit according to any one of claims 1-5, or the multiplex analog-to-digital conversion circuit according to any one of claims 6-7.

9. A computing device, characterized in that, Includes the chip according to claim 8.

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