Analog-to-digital converter, chip, and electronic device

Abstract

The disclosed embodiments provide an analog-to-digital converter, chip, and electronic device, including a channel multiplexing selection unit, a group / channel control configuration unit, a group / channel arbitration control unit, an incremental accumulator, and a sampling time register. Through the disclosed processing scheme, the analog-to-digital converter can effectively reduce the problem of excessive mismatching between the sampling time and conversion result of a particular analog channel due to factors such as prioritization of other analog channels or fluctuations in sampling conversion time, thereby improving the accuracy of subsequent analysis and processing of the sampling results in such situations.

Description

Technical Field

[0001] The present invention relates to the technical field of analog-to-digital conversion controllers, and in particular to an analog-to-digital converter, a chip, and an electronic device. Background Art

[0002] Generally speaking, the analog-to-digital conversion process implemented by the AD circuit is specifically a discrete sampling and conversion process for digitizing analog signals (abbreviated as sampling and conversion processing). Therefore, the mapping accuracy between the sampling time of the sampling and conversion processing and the content of the sampling and conversion results is crucial for the subsequent analysis and processing of the sampling and conversion results in the MCU (microprocessor chip) system. Although theoretically, the error deviation of the above mapping relationship may be minimized by using some compensation / correction algorithm in the MCU system (such operations will increase the complexity of the analysis and processing). However, if it is not reduced in a timely and sufficient manner, it will accumulate to a certain extent and will lead to the complete collapse / uncorrectability of the subsequent analysis and processing (that is, it will introduce initialization operations to restore the analysis and processing system to normal, which will increase the complexity of the analysis and processing and reduce the available time margin for normal subsequent analysis and processing).

[0003] To minimize the deviation in the mapping relationship between sampling time and the content of the sampled results, MCU system designers must take some targeted measures:

[0004] The first common approach is to physically integrate multiple AD circuits so that regular packets and injected packets can be sampled and converted in separate AD circuits, thereby fundamentally eliminating the "insertion of injected packets into the process." However, this approach clearly imposes significant hardware overhead and is not an effective way to improve the matching error between sampling time and conversion results.

[0005] Another common approach is to prioritize regular packets over injected packets to prevent the injected packets from being inserted into the regular packets. However, this approach clearly violates the definition of the injected packets, thus failing to ensure timely processing of the injected channel analog signals and effectively reducing the mismatch between sampling time and conversion results. Summary of the Invention

[0006] The embodiments of the present disclosure provide an analog-to-digital converter, a chip, and an electronic device, which at least partially solve the problems existing in the prior art.

[0007] In a first aspect, an embodiment of the present disclosure provides an analog-to-digital converter, comprising: a channel multiplexing selection unit, configured to determine a target channel to be subjected to AD processing from a plurality of input channels based on at least one input analog signal and at least one channel selection signal corresponding to the analog signal, and to determine a target analog signal corresponding to the channel to be subjected to AD processing, and to transmit the target analog signal to an AD circuit for actual analog-to-digital conversion processing;

[0008] A group / channel control configuration unit, configured to determine control configuration information based on the received configuration information of the MCU system, wherein the control configuration information is used to configure and control the acquisition and transfer processing of different groups or channels;

[0009] a group / channel arbitration control unit, configured to determine a channel selection signal and a channel sampling trigger signal for each channel based on the received global sampling trigger signal, the control configuration information, and a processing sequence or priority rule pre-programmed for each channel, wherein the channel selection signal is used to indicate the selection of the channel, and the channel sampling trigger signal is used to indicate to the AD circuit to start the current AD processing;

[0010] An incremental accumulator, driven by the working clock of the analog-to-digital converter, is used to incrementally and cumulatively update each working clock cycle of the analog-to-digital converter, so as to provide a time reference for capturing the sampling time;

[0011] At least one sampling time register unit is used to capture and store the real-time value of the incremental accumulator based on the channel sampling trigger signal as the sampling time, and combine the sampling time with the channel conversion result content and provide it to the MCU system.

[0012] According to a specific implementation of the embodiment of the present disclosure, the method further includes:

[0013] A global sampling trigger signal generating unit is generated by other circuit logic outside the analog-to-digital converter and / or by a certain circuit logic inside the analog-to-digital converter. The global sampling trigger signal is used to start the sequential and continuous sampling process of analog signals of multiple channels;

[0014] When the incremental accumulator is in absolute counting mode, it is used to regard the global sampling trigger signal as a time zero point, and start to accumulate incrementally from the corresponding zero point value. When it increases to the maximum value or encounters an MCU system reset, the incremental accumulator will return to the zero point value.

[0015] According to a specific implementation method of an embodiment of the present disclosure, when the incremental accumulator is in relative counting mode, it is used to regard the global sampling trigger signal and the sampling trigger signal of any channel as a time zero point, and start incremental accumulation from the corresponding zero point value. When the next sampling is started, the real-time value of the incremental accumulator is captured and then returned to the zero point value.

[0016] According to a specific implementation of the embodiment of the present disclosure, when the incremental accumulator is in the absolute counting mode, the sampling time register unit is used to reflect the sampling time starting time value of each channel.

[0017] According to a specific implementation of the embodiment of the present disclosure, when the incremental accumulator is in the relative counting mode, the sampling time register unit is used to reflect the time consumed for completing the sampling process of the latest historical channel.

[0018] According to a specific implementation of the embodiment of the present disclosure, after a valid global sampling trigger signal appears, the first sampling time captured by the sampling time register unit represents the time difference between the valid global sampling trigger signal and the first valid channel sampling trigger signal.

[0019] According to a specific implementation of the embodiment of the present disclosure, the MCU system is used to calculate the sampling start time point of each channel according to the sampling time captured by the sampling time register unit.

[0020] According to a specific implementation of the embodiment of the present disclosure, when the MCU system does not need to know the sampling time information of each channel, the incremental accumulator and the sampling time register unit are in an idle state and are not used.

[0021] In a second aspect, an embodiment of the present disclosure provides a chip, comprising: the analog-to-digital converter described in any one of the above aspects.

[0022] In a third aspect, an embodiment of the present disclosure further provides an electronic device comprising: at least one chip as described in the second aspect.

[0023] The analog-to-digital converter, chip, and electronic device disclosed in the embodiments of the present disclosure include a channel multiplexing selection unit, a group / channel control configuration unit, a group / channel arbitration control unit, an incremental accumulator, and a sampling time register unit. By adding the incremental accumulator and sampling time register unit, the disclosed solution can effectively reduce the problem of excessive mismatching between the sampling time and conversion result of a particular analog channel due to factors such as other analog channels being prioritized or fluctuations in sampling conversion time, thereby improving the accuracy of subsequent analysis and processing of the sampling results in such situations. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0025] Figure 1 A schematic diagram of a circuit architecture of an analog-to-digital converter provided in an embodiment of the present disclosure;

[0026] Figure 2 A schematic diagram of the principle of analog-to-digital conversion processing for continuous analog signals;

[0027] Figure 3 This is a schematic diagram of the consequences of a single channel when the sampling time and conversion result do not match;

[0028] Figure 4 This is a schematic diagram showing that multiple related channels cannot achieve absolute synchronous sampling;

[0029] Figure 5 This is a schematic diagram of the application of analog-to-digital conversion processing in a common motor closed-loop automatic control system;

[0030] Figure 6 A schematic diagram of the present disclosure in which a packet is injected into the process of processing a queue in the middle of a regular packet transfer in the absolute counting mode;

[0031] Figure 7 The present disclosure is a schematic diagram of a process in which an injected packet is interrupted in the middle of a regular packet transfer in the relative counting mode. DETAILED DESCRIPTION

[0032] Many microprocessor chips (hereinafter referred to as MCU) are integrated with analog-to-digital converter controllers (Analog-to-Digital Converter, refers to analog / digital converter or analog / digital converter, hereinafter referred to as ADC, or ADC system) to control analog-to-digital conversion circuits (Analog-to-Digital, analog / digital conversion, hereinafter referred to as AD circuit) to complete the sampling and digital conversion of analog signals. An ADC can control the AD circuit to complete the time-sharing sampling of multi-channel analog signals and convert them into digital signals through multiplexing (refer to Figure 2 , Figure 2(This figure illustrates the principle of analog-to-digital conversion for continuous analog signals.) Each channel's analog signal has a corresponding sampling trigger signal, which triggers the AD circuit at a specific moment to complete analog-to-digital sampling and conversion. The conversion result must maintain a one-to-one correspondence with the time of the sampling trigger (referred to as the sampling time, similarly below) to ensure a consistent match between the sampling time and the digital conversion result. Only when this matching relationship is accurate can the characteristic curve of the analog signal be relatively accurately restored during subsequent digital signal processing.

[0033] In one application scenario, among the multi-channel analog signals to be processed by an ADC, the analog signals of some channels are a group of interrelated signals. It is expected that the sampling and conversion of this group of signals can be completed at the same time to restore the relationship between the signals at that moment. However, since an AD circuit can only process one channel analog signal at a time, after receiving a valid sampling trigger signal for the analog signal group, the ADC can only perform scanning-style continuous sampling on the analog signal group and complete it in the shortest possible time. The sampling and conversion time of each channel of the analog signal group is often the same. If the ADC does not insert the sampling and conversion processing of other analog signals during the scanning sampling process of the analog signal group, the conversion result of each channel can be matched to the sampling time one by one. Then, the conversion result of the analog signal group can be used through a post-processing algorithm to more realistically restore the conversion relationship of the signal group, or the unsampled signal situation can be deduced by using the obtained conversion result and the known correlation relationship.

[0034] However, in practical applications of MCU chips, it's difficult to guarantee that a channel's analog signal sampling request will be processed promptly. Fluctuations in the ADC sampling conversion time can cause the sampling time of a channel's analog signal to deviate from the expected value, introducing errors in the matching relationship between the conversion result and the expected sampling time. This matching error inevitably increases the error between the original analog signal curve and the digitized fitted signal curve, or increases the complexity of the digital signal post-processing algorithm.

[0035] Currently, the ADC calculates the expected sampling time for a channel's analog signal based on its sampling trigger signal. The ADC only outputs the channel's sampling conversion result and does not output any sampling time information. If the ADC fails to respond to a channel's valid sampling trigger signal in a timely manner (for example, because other channels must be processed first), or if the channel's valid sampling trigger signal itself fluctuates over time, the channel's actual sampling time will deviate from its expected value, inevitably introducing errors in the matching relationship between the conversion result and the sampling time. Post-processing algorithms generally cannot detect this error from the conversion result alone, which in turn increases the error between the original analog signal curve and the digitized fitted signal curve, or increases the complexity of the digital signal post-processing algorithm.

[0036] like Figure 3 The figure below illustrates a single channel experiencing a mismatch between sampling time and conversion results. Assuming a single target channel, without any special circumstances, repeatedly performs analog-to-digital sampling and conversion of the corresponding analog signal at times such as t1 / t2 / … / t7. Furthermore, assume that the original input analog signal is an ideal triangle wave (shown as the dashed line in the figure, which represents the original analog signal curve).

[0037] Because the ADC can't respond to the channel's valid sampling trigger signal in a timely manner (for example, because other channels must be processed first), or because the channel's valid sampling trigger signal itself exhibits temporal fluctuations, the channel sampling process, originally scheduled to begin at t2 / t5, is delayed until tA / tB, respectively. However, the MCU system, unaware of this unusual situation, mistakenly interprets the conversion result at tA / tB as the conversion result at t2 / t5. Consequently, it infers an erroneous digital fitting curve based on the ideal fitting function (as shown in the solid waveform in the figure). Consequently, based on this significantly erroneous fitting curve, the MCU system will accumulate errors in subsequent processing of the digital signal.

[0038] like Figure 4 The figure below illustrates the inability to achieve absolutely synchronous sampling of multiple interconnected channels. In a specific embodiment of a brushless DC motor control MCU system, the three-phase stator winding coils utilize a three-on-three configuration (rather than a two-on-two configuration). Therefore, synchronous detection of the three-phase armature current is required to estimate the back EMF (E). However, typical motor control MCUs typically integrate only one set of analog-to-analog circuitry to conserve hardware resources. Consequently, the sampling and processing of the three-phase current analog signals from different channels, originally intended to begin simultaneously, must be performed separately and in parallel.

[0039] like Figure 4As shown, assuming that the U-phase current begins sampling and processing at time t0 and is completed at time t0+n, the sampling and processing of the V-phase and W-phase currents can only be triggered at time t0+n and t0+2n, respectively (Note: For clarity, the three moments are drawn with large spacing in the figure, but in the actual waveform curve, they are very close together). Therefore, the actual conversion results of the V-phase and W-phase currents (as shown in Iv' and Iw' in the figure) are definitely different from the conversion results originally expected at time t0 (as shown in Iv and Iw in the figure). However, if the correlation matching accuracy of the sampling time and conversion results of the three-phase current channels can be guaranteed, the MCU system can reversely calculate a high-precision approximation of the expected conversion result on the time axis based on the detected actual conversion results and the target fitting function. Therefore, in subsequent analysis and processing, a sufficiently high-precision back-EMF curve can still be calculated based on the three-phase current conversion results at the same time.

[0040] Taking a brushless DC motor control MCU chip (hereinafter referred to as a motor control MCU) as an example, a typical motor control MCU needs to collect a set of back-EMF voltage analog signals corresponding to the motor's three-phase stator winding coils. It then uses the changes in these back-EMF voltage analog signals to calculate information such as the angular position and speed of the motor winding coils relative to the motor's inner rotor permanent magnet. Because the sum of the three back-EMF voltage analog signals of the motor's three-phase stator winding coils is ideally zero at any given moment, the back-EMF voltage of the remaining phase can be inferred by sampling the back-EMF voltage analog signals of any two phases.

[0041] In a configuration scenario without a position sensor, in order to sample and obtain the above-mentioned three-phase back electromotive force voltage analog signal, in a common solution, it is necessary to output the current analog signal corresponding to the three-phase stator winding coil of the motor from the motor and provide it as feedback information to the motor control MCU.

[0042] While performing the aforementioned A / D processing (i.e., analog / digital conversion) on the current analog signal, the same motor control MCU may also need to sample and convert (sampling and conversion, short for sampling and conversion) input analog signals from other channels, such as the MCU's own power supply voltage, chip temperature, drive current, and so on. Therefore, the MCU may need to perform A / D and subsequent analysis on analog signals from multiple input channels from different sources relatively synchronously within the same short time window.

[0043] To perform the above processing on multi-channel input analog signals from different sources, the conventional method in the motor control MCU system is generally as follows:

[0044] Ensure that the sampling rate of the AD processing is much higher than the required sampling rate of the input analog signal, and the sampling frequency is greater than twice the maximum frequency of the input analog signal;

[0045] Group analog signals on multiple input channels into different categories (for example, motor feedback current and MCU chip temperature are two analog signals that need to be grouped separately in the example above).

[0046] Using time-division multiplexing and a preset priority algorithm, only one set of ADC circuits is integrated to complete the AD processing and control of multi-channel input analog signals in different groups (of course, it can also be the same group);

[0047] The unique ADC circuit provides the sampling results of the different channels to the MCU system for further subsequent analysis and processing.

[0048] In more specific application scenarios, a common practice for motor control MCUs is to define the motor feedback current analog signal in a regular group (note: correspondingly called a regular channel), and to define analog signals from other sources in an injected group (note: correspondingly called an injected channel). When the MCU system generates a sampling trigger signal to "start sampling and processing of the regular group," the input analog signals of multiple channels selected in the regular group will be sampled and processed sequentially according to a preset sequence or priority setting (note: the control involved is the responsibility of the ADC circuit, while the underlying analog-to-digital sampling and processing is implemented by the AD circuit; the same is true for the injected group). In conventional ADC circuit design, the processing priority of injection packets is generally designed to be higher than that of regular packets. In other words, if an injection packet's acquisition processing request is inserted into the multi-channel acquisition process of a regular packet, the acquisition processing of the remaining channels of the regular packet will be suspended, and the ADC circuit will prioritize the acquisition processing of the channels of the injected packet. After the acquisition processing of all selected channels in the injected packet is completed, it will return to resume the acquisition processing control of the remaining channels in the regular packet. Note: The entire process of injection interruption → regular interruption → regular resumption can be simply referred to as the "injection packet insertion process."

[0049] Now assume that: during the sampling process of each channel of a regular group, no injection group insertion process occurs. Since the sampling time of a single channel is usually fixed (assuming the working principle of the AD circuit and the sampling resolution are determined, the single sampling time of the regular channel and the injection channel is consistent and fixed), if the sampling time of the first channel in the group can be determined (hereinafter referred to as the sampling start time), then the sampling time of each channel in the regular group can be calculated. In this way, and under the premise that each sampling result can be stored in time, the mapping relationship between the sampling time of each regular channel and the content of the sampling result is bound.

[0050] However, if the above assumption is not true, that is, the "insertion process of the injected group" occurs during the sampling process of each channel of the conventional group, because the MCU system cannot predict the specific insertion time of the injected group, if it still uses the above assumption to calculate the mapping relationship between the sampling time of the conventional channel and the content of the sampling result, it will inevitably produce errors and deviations.

[0051] In some situations where analog-to-digital conversion requires high precision, errors in this mapping relationship are clearly detrimental to the subsequent digital analysis and processing of the conversion results. To avoid such mapping errors between sampling time and the content of the conversion results during AD processing and subsequent analysis of multi-channel input analog signals, the present disclosure proposes an analog-to-digital converter, an embodiment of which is described in detail below with reference to the accompanying drawings.

[0052] The following describes the embodiments of the present disclosure through specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. The present disclosure can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0053] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on this disclosure, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects described herein can be used to implement an apparatus and / or practice a method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this apparatus and / or practice this method.

[0054] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present disclosure. The illustrations only show components related to the present disclosure and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0055] Additionally, in the following description, specific details are provided to provide a thorough understanding of the examples. However, one skilled in the art will appreciate that the aspects described can be practiced without these specific details.

[0056] See also Figure 1 , Figure 1 Schematic diagram of some embodiments of an analog-to-digital converter disclosed herein. Figure 1 As shown, the analog-to-digital converter includes:

[0057] a channel multiplexing selection unit, configured to determine a target channel to be processed by AD from a plurality of input channels based on at least one input analog signal and at least one channel selection signal corresponding to the analog signal, and to determine a target analog signal corresponding to the channel to be processed by AD, and to transmit the target analog signal to the AD circuit for actual analog-to-digital conversion processing;

[0058] A group / channel control configuration unit, configured to determine control configuration information based on the received configuration information of the MCU system, wherein the control configuration information is used to configure and control the acquisition and transfer processing of different groups or channels;

[0059] a group / channel arbitration control unit, configured to determine a channel selection signal and a channel sampling trigger signal for each channel based on the received global sampling trigger signal, the control configuration information, and a processing sequence or priority rule pre-programmed for each channel, wherein the channel selection signal is used to indicate the selection of the channel, and the channel sampling trigger signal is used to indicate to the AD circuit to start the current AD processing;

[0060] An incremental accumulator, driven by the working clock of the analog-to-digital converter, is used to incrementally and cumulatively update each working clock cycle of the analog-to-digital converter, so as to provide a time reference for capturing the sampling time;

[0061] At least one sampling time register unit is used to capture and store the real-time value of the incremental accumulator based on the channel sampling trigger signal as the sampling time, and combine the sampling time with the channel conversion result content and provide it to the MCU system.

[0062] In some embodiments, reference Figure 1 The circuit architecture includes an ADC circuit 1 (i.e., an analog-to-digital conversion controller) and an AD circuit 2. The ADC circuit 1 is responsible for arbitrating and selecting input signals for analog-to-digital conversion and registering the conversion results. The analog-to-digital conversion controller first includes the following components and key signals typically included in a general ADC circuit:

[0063] Multiplexing selection unit 10;

[0064] Group / channel control configuration unit 11;

[0065] · Group / channel arbitration control unit 12;

[0066] Channel conversion result register unit 13;

[0067] Global sampling trigger signal;

[0068] Channel selection signal;

[0069] Channel sampling trigger signal.

[0070] The multiplexing selection unit 10 is used to select an analog signal from multiple input channels based on the corresponding channel selection signal and transmit it to the AD circuit for actual analog-to-digital conversion processing;

[0071] The group / channel control configuration unit 11 is used to configure and control the data acquisition and conversion processing that the ADC circuit may carry out for different groups or channels based on the relevant configuration information from the MCU system;

[0072] The group / channel arbitration control unit 12 is configured to arbitrate and select the channel currently to be processed for AD processing based on the control configuration information and the processing sequence or priority setting pre-programmed for each channel;

[0073] The channel conversion result storage unit 13 is used to properly store the conversion result output by the AD circuit after the acquisition is completed, so that it can be obtained by the MCU system in various application scenarios;

[0074] The global acquisition trigger signal is used to start the sequential acquisition process of analog signals from a group of multiple channels. Generally, it is generated by other circuit logic outside the ADC circuit, but it can also be generated by some circuit logic inside the ADC circuit.

[0075] The channel selection signal is used to indicate the selection of the channel currently to be processed by AD, and is generated by the group / channel arbitration control unit.

[0076] The channel sampling trigger signal is used to indicate to the AD circuit to start the current AD processing, and is generated by the group / channel arbitration control unit.

[0077] Secondly, based on any of the above embodiments, the embodiment of the analog-to-digital converter disclosed in the present invention adds the following components to a general ADC circuit: an incremental accumulator and a sampling time register unit.

[0078] The incremental accumulator is driven by the working clock of the ADC circuit. The accumulator is updated incrementally in each ADC clock cycle to provide a time reference for capturing the sampling time.

[0079] Among them, the sampling time storage unit is used to capture and store the real-time value of the incremental accumulator at the time based on the effective channel sampling trigger signal, as the sampling time information, and merge it with the channel conversion result content for the MCU system to obtain in pairs.

[0080] Based on any of the above embodiments, only one incremental accumulator (or multiple accumulators depending on actual conditions) needs to be integrated in the ADC circuit to implement the absolute counting mode and / or the relative counting mode.

[0081] In absolute counting mode, the incremental accumulator considers the global sampling trigger signal as a time zero and begins to count incrementally from a selected zero value (including but not limited to 0 or 1, the same below). The incremental accumulator returns to zero only when it reaches a limit value or maximum value (for example, a 32-bit accumulator will return to zero if it counts to 0xFFFF_FFFF) or when a system reset occurs.

[0082] In relative counting mode, the incremental accumulator treats the global sampling trigger signal and any channel sampling trigger signal as a time zero and begins counting from a selected zero point. Generally, when the increment reaches a smaller corresponding value (for example, a 5-bit accumulator counting to 0x12), the incremental accumulator returns to zero (for example, 1) and restarts counting. The difference between this smaller corresponding value and the selected zero point is the time required to complete a single AD (i.e., single channel) acquisition process.

[0083] The zero point value under the relative counting modulus may be preset.

[0084] Among them, under the relative counting modulus, the global sampling trigger signal and the sampling trigger signal of any channel are regarded as a time zero point, and the accumulation starts from the corresponding zero point value. When the next sampling is started, the real-time value of the incremental accumulator is captured and then returned to the zero point value. The difference between the captured real-time value and the zero point value is the broad time consumption of this sampling (the narrow time consumption is the time consumption of the sampling processing itself, and the broad time consumption includes the delay increased by other factors, such as the queue interruption of the injected group).

[0085] Based on any of the above embodiments, at least one sampling time register unit is integrated into the ADC circuit, and multiple units may be integrated according to specific application requirements. Generally speaking, the number of integrated units and the number of integrated channel conversion result register units may be consistent.

[0086] No matter which counting mode the incremental accumulator is in, the sampling time register unit is captured and stored as the real-time value of the incremental accumulator when any channel sampling trigger signal is valid.

[0087] Based on any of the above embodiments, the number and reasons for the integration of sampling time register units can be divided into:

[0088] 1) All integrated channels of the conventional group are integrated with independent sampling time register units, so that the conversion results of each conventional channel will not overwrite each other and cause data omission;

[0089] 2) For all integrated channels in a conventional group, only one shared sampling time register is integrated, so that the MCU system can obtain the conversion results of all conventional channels from the same register unit, reducing the corresponding control complexity;

[0090] 3) All integrated channels of the injection group are integrated with independent sampling time register units, so that the conversion results of each injection channel will not overwrite each other and cause data omission;

[0091] 4) For all the integrated channels of the injection group, only one shared sampling time register unit is integrated, so that the MCU system can obtain the conversion results of all injection channels from the same register unit, reducing the corresponding control complexity;

[0092] 5) When both regular and injected groups exist, the sampling time register unit integration solutions for the two types of groups can respectively adopt the above solutions 1) or 2), and 3) or 4). Furthermore, in certain cases where the application and configuration environment permit, it may also be feasible to integrate one or more sampling time register units for both types of groups without distinction.

[0093] In addition, if the application can ensure that the channel sampling processing of the injection group always has the highest priority, it is generally not necessary to integrate a dedicated sampling time register unit for it, that is, the regular group and the injection group can share one or more of the sampling time register units.

[0094] Based on any of the above embodiments, when the incremental accumulator is in the absolute counting mode, the sampling time register unit generally reflects the sampling time starting time value of each channel.

[0095] Based on any of the above embodiments, when the incremental accumulator is in the relative counting mode, the sampling time register generally reflects the time taken to complete the sampling process of the latest historical channel.

[0096] Regardless of the counting mode of the incremental accumulator, the sampling time register unit is captured and stored as the real-time value of the incremental accumulator when the sampling trigger signal of any channel is valid.

[0097] Based on any of the above embodiments, regardless of the counting mode, the first sampling time register capture value after a valid global sampling trigger signal appears specifically reflects the time difference between the valid global sampling trigger signal and the first valid channel sampling trigger signal;

[0098] Based on any of the above embodiments, no matter in which counting mode, the MCU system can infer the same time information of the sampling start time point of each channel from the captured value of the sampling time register unit, that is, the high-precision sampling start time information of each channel on the time axis "taking the effective point of the global sampling trigger signal as the initial time zero point".

[0099] Based on any of the above embodiments, the incremental accumulator and sampling time register may be in a disabled idle state in some circumstances. These circumstances include, but are not limited to, situations where the MCU system does not need to know the sampling time information of each channel, for example, when the MCU system can confirm that the acquisition of analog signals from a certain group of input channels will not be interrupted by the acquisition of other channels, and the acquisition time of each channel in the group is known and determined.

[0100] The analog-to-digital converter in the disclosed embodiment includes a channel multiplexing selection unit, a group / channel control configuration unit, a group / channel arbitration control unit, an incremental accumulator, and a sampling time register unit. By adding the incremental accumulator and sampling time register unit, the disclosed solution effectively reduces the problem of excessive mismatching between the sampling time and conversion result of a particular analog channel due to factors such as other analog channels being prioritized or fluctuations in sampling conversion time, thereby improving the accuracy of subsequent analysis and processing of the sampling results in such situations.

[0101] In one embodiment, a global sampling trigger signal corresponds to the time zero. This signal needs to pass through A unit time before driving the generation of the first channel sampling trigger signal in the ADC circuit. At this time, the incremental accumulator has been updated to A (regardless of whether it is in absolute or relative counting mode). After the first channel sampling trigger signal is effectively generated, the AD sampling process of the first channel begins. During this period:

[0102] 1. If the incremental accumulator is in relative counting mode, its update process starts from 1 (selected zero value) + 1 and increments to n (indicating the time taken to complete the acquisition of a single AD process);

[0103] 2. If the incremental accumulator is in absolute counting mode, its update process starts from A+1 (selected zero value) and increments by +1 to A+n (representing the time taken to complete the acquisition of a single AD process);

[0104] When the first channel is sampled and transferred, the second channel sampling trigger signal can be generated synchronously or after a slight delay, depending on the MCU system and the AD circuit itself. Note that whether it must be generated after a delay or can be generated immediately requires comprehensive consideration of the following two factors:

[0105] The specific delay between "the channel sampling trigger signal generated by the ADC circuit" and "the corresponding receiving port of the ADC circuit being able to recognize the channel sampling trigger signal" in an actual circuit environment;

[0106] The specific delay between "the channel acquisition completion indication signal generated by the AD circuit" and "the corresponding receiving port of the ADC circuit being able to recognize the acquisition completion indication signal" in an actual circuit environment.

[0107] In some application scenarios, the two delay factors mentioned above can be ignored. In other words, the following process is described based on the premise that "the sampling trigger signal of the next channel is generated synchronously when the sampling of the previous channel is completed." In other words, when the sampling of the (i-1)th channel is completed, the system will generate the channel sampling trigger signal of the i-th channel (i≥2). Therefore, during the sampling process of the i-th channel, the update process of the incremental accumulator is:

[0108] (1) In relative counting mode, start from 1 + 1 and increment to n;

[0109] (2) In absolute counting mode, it starts from "A+1+(i-2)*n" and increases by +1 to "A+(i-1)*n".

[0110] As can be seen, in relative counting mode, the maximum calculable value of the incremental accumulator is A or n, whichever is the smaller of the two. Therefore, the circuit scale of the incremental accumulator and the sampling time register can be relatively small. In absolute counting mode, the maximum calculable value of the incremental accumulator is obviously much larger, so the circuit scale of the incremental accumulator and the sampling time register must be relatively large.

[0111] The sampling time, which is one of the final results of the conversion, i.e., the value captured by the sampling time register unit, must be provided to the MCU system in pairs together with the content of the conversion result in the method provided by the present invention. Obviously, the increase in the circuit scale of the sampling time register unit will inevitably increase the amount of data accessed by the MCU system, which may in turn reduce the overall completion performance of the AD and subsequent analysis and processing.

[0112] As can be seen, in some specific environments, using the relative counting mode for the incremental accumulator can help improve system processing performance in terms of "accessing the sampling time from the sampling time register." In other environments, using the absolute counting mode for the incremental accumulator can eliminate the software calculation required by the MCU system to calculate the "absolute start time" based on the "relative completion time," thereby improving overall system processing performance in these environments.

[0113] Figure 5 This is a schematic diagram of analog-to-digital conversion processing in a common motor closed-loop automatic control system.

[0114] The so-called automatic control system refers to "a management system with its own goals and functions, which automatically controls certain key parameters in production so that when they deviate from the normal state due to external interference, they can be automatically adjusted to return to the numerical range required by the process. It is composed of a control subject, a control object and a control medium."

[0115] Automatic control systems are generally categorized as open-loop and closed-loop. Closed-loop control is often chosen for motor drive applications requiring high control precision. Closed-loop control, also known as (negative) feedback control, consists of a detection device, a control device, an actuator, and a controlled object. The detection device detects certain state information (output) of the controlled object and converts it into a physical signal (typically an analog electrical signal) that is transmitted to the control device. The control device compares the deviation of the controlled object's current state (output) with the desired state (reference value) and generates a set of control signals. These signals, through the actuator, drive the controlled object to move closer to the desired state.

[0116] The above description is specifically applied to the application environment of motor drive control. The various components of the closed-loop control system are generally mapped as follows: detection device = feedback detection circuit (for example, with a Hall position sensor), control device = motor control MCU system (chip) (containing circuit sub-modules responsible for analog-to-digital conversion processing and PWM waveform signal generation), actuator = electrode power amplification drive circuit, and controlled object = motor body, that is, the (brushless DC) electrode in the figure.

[0117] In order to achieve closed-loop control of the brushless DC motor and thus automatically and intelligently control its speed, angular position and torque (torque for short), in a specific embodiment, the following can be implemented: Figure 5 The following figure illustrates a motor control system. Note that in applications requiring high control precision, driving the motor to produce smooth torque (i.e., minimizing torque ripple) is a major challenge in the motor control industry. To overcome this difficulty, motor control MCU systems typically employ feedback algorithms known as PID and FOC for more precise motor control. The effective implementation of these feedback algorithms requires the motor control MCU system to obtain accurate and sufficiently precise feedback information.

[0118] In a typical brushless DC motor with a Y-shaped stator winding coil arrangement, the three stator windings, spaced 120° apart on the outer ring, are generally referred to as the three-phase motor. By controlling the presence and direction of current (i.e., armature current) flowing through these coils, an armature magnetic field is generated, creating an attractive or repulsive magnetic field with the permanent magnets in the motor's inner ring, thereby driving the rotation of the motor shaft, which is coaxially bound to the inner permanent magnets. In the "two-two conduction" configuration scenario, well-known in the motor industry, only two of the three-phase stator winding coils may be conducting (referred to as the "conducting phase") within a short time window, while the remaining one is non-conducting (referred to as the "non-conducting phase"). Assuming that within a certain time window, the conducting phases are A and B, and the non-conducting phase is C, then for phases A+B, a circuit model such as "two half-bridges with a total of four N-type MOS transistors" can control whether current will flow through their winding coils, as well as the positive and negative directions of the current flow; while for phase C, "one half-bridge with a total of two N-type MOS transistors" remains in the off state, even if no current flows through its winding coils.

[0119] For the three half-bridges of the three phases A+B+C, comprising a total of six N-type MOSFETs, current motors typically employ PWM modulation-based control techniques to microscopically manage the presence and direction of voltage applied to the source and drain terminals of the MOSFETs, thereby controlling the presence and direction of the armature current in the conducting phases. In a common six-step PWM modulation scheme, a 360° rotation of the motor shaft is divided into six 60° sectors. During a single 60° modulation cycle, the two conducting phases and one non-conducting phase are maintained constant, thereby continuously driving the motor shaft to rotate 60° in the desired direction. However, near the sector boundary, the combination of conducting and non-conducting phases must be changed (for example, originally phase C was non-conducting and phases A+B were conducting; now, phase B is non-conducting and phases A+C are conducting) to control the motor shaft to continue rotating in the desired direction. This operation is generally referred to as commutation.

[0120] The feedback detection circuit in the motor closed-loop automatic control system can be divided into two types: with position sensor and without position sensor (abbreviated as inductive and non-inductive). For the inductive type feedback detection circuit, an additional position sensor (such as a Hall element or a grating encoder) is generally responsible for providing the angular position information of the motor shaft. The non-inductive type feedback detection circuit is in great demand in certain applications because it saves the configuration cost and occupied volume of the position sensor. As a price, in the non-inductive feedback detection circuit, it is generally necessary to monitor the zero-crossing moment of the so-called back electromotive force Ea to deduce the angular position information; and to monitor the back electromotive force Ea, it is necessary to monitor the armature current of the three phases.

[0121] During the switching process of the above-mentioned commutation operation, due to the existence of back electromotive force, an "excitation current component that has the opposite effect on the original armature current component" will be formed in the conduction phase winding coil (Note: This description is only a simple understanding), making the armature current of the conduction phase unable to reach the original ideal level. This will appear as a relatively short downward jitter in the resulting motor torque waveform, which is the so-called motor torque fluctuation.

[0122] In order to compensate for the torque fluctuations during the commutation process and make the torque waveform as smooth as possible, and based on the consistent idea of closed-loop automatic control systems, the deviation between the current state of the armature current of the controlled object (motor body) and the desired state of the armature current expected by the system needs to be known in real time by the control device (motor control MCU system). Then, the control device can simulate an armature current with a sinusoidal waveform and added compensation components at the macro level in the DC circuit system based on the PWM signal with constant voltage amplitude and real-time modulated conduction duty cycle at the micro level.

[0123] To determine the armature current deviation mentioned above, the current state of the armature current must be known as accurately as possible. This leads to the necessity of implementing high-precision analog-to-digital conversion and subsequent analysis and processing in the motor control MCU system. Furthermore, calculating the armature current deviation requires comparing the current state and the desired state of a single-phase current at the same target time. Therefore, if an error occurs on the time axis (for example, comparing the desired state at time t1 with the current state at time t2) and this error exceeds a certain threshold, the PWM signal generated by the corresponding closed-loop feedback control algorithm will be difficult to achieve the desired control effect of reducing torque fluctuations. Therefore, the implementation of the analog-to-digital conversion and subsequent analysis and processing must ensure both high precision in the acquisition and conversion processing and low error in the analysis and processing.

[0124] from Figure 5 It can be seen from the embodiments that the use of the analog-to-digital converter disclosed in the present invention can effectively avoid the time error when the armature current of each phase output by the motor is detected and obtained by the motor control MCU system in the motor closed-loop automatic control system in a sensorless configuration environment.

[0125] Figure 6 、 Figure 7 Schematic diagram of the present disclosure showing that an injected packet is interrupted in the middle of regular packet transfer in the absolute and relative counting modes.

[0126] In one specific embodiment, the three-phase armature current analog signal output by the motor can be mapped to three or six input channels in a conventional group (depending on whether the current signal is single-ended or differential), while the reference voltage signal within the MCU system is mapped to one channel in an injection group. Therefore, when the three-phase armature current signal is processed via the conventional channels for analog-to-digital conversion, it is often impossible to predict when the AD acquisition request for the internal reference voltage signal will be submitted. This creates the possibility that the acquisition process of a conventional channel and subsequent channels may be delayed due to the injection channel's interruption in the acquisition process, without the MCU system being aware of the delay.

[0127] For the above possible solutions, you can use Figure 6 and Figure 7 The circuit logic of the specific embodiment shown in the figure is described in detail. Figure 6 and Figure 7 The essential difference is that the incremental accumulator is updated in absolute and relative counting modes respectively.

[0128] like Figure 6 As shown, first assume that at time t1 on the timeline, a global sampling trigger signal for a regular group is generated in the system. In practice, this signal is expected to continuously perform AD processing on the armature current signals (UV, W, etc.) of the three phases of the regular group, following the sequence U→V→W→U→V→W→…. Furthermore, assume that after a delay of Δ(A) from time t1, the group / channel arbitration control unit 12 generates the first channel sampling trigger signal (at time t2). At this point, the corresponding incremental accumulator has incremented to A, and therefore (the channel sampling trigger signal is valid at this time) this value A is captured and stored in the sampling time register dedicated to the regular group.

[0129] After time t2, the first regular channel (designated RG#1), selected according to a pre-programmed sequence or priority setting, begins its sampling process. Under the common assumption that AD circuit 2's sampling principle and resolution remain constant, the time required to complete a single AD process on a single channel is constant. Assuming its value is n (units are 1 ADC clock cycle, the same applies below), AD circuit 2 outputs the current AD sampling result when the incremental accumulator updates to the value (A+n). Simultaneously, a channel sampling trigger signal for channel RG#2 is generated (at time t3; Note: As previously mentioned, assuming that the sampling trigger signal for the next channel is generated immediately upon completion of the current channel's sampling), thus capturing the real-time value (A+n) of the incremental accumulator and storing it in the same sampling time register.

[0130] After time t3, similarly to the above, the second regular channel (labeled as RG#2) begins its sampling process, which is completed and outputs the conversion result when the incremental accumulator is updated to the value (A+2n) (at time t4). At the same time, the channel sampling trigger signal for channel RG#3 is also generated; therefore, the real-time value (A+2n) of the incremental accumulator is captured and stored in the same sampling time register unit.

[0131] After time t4, similar to the above, the third regular channel (marked as RG#3) begins its acquisition and transfer processing. However, the difference is that at time t5, before the AD processing is completed, a higher priority injection group global acquisition and transfer trigger signal is suddenly inserted. This injection global trigger signal is detected by the group / channel arbitration control unit 12, and after the acquisition and transfer processing of the RG#3 channel is completed, it jumps to implement the acquisition and transfer processing control of the injection group. Note that Figure 6 and Figure 7 For the two specific embodiments shown, the time window {t5-t6} represents a time delay from the generation of the above-mentioned injection global trigger signal to the generation of the first injection channel sampling trigger signal.

[0132] Assumptions Figure 6 The injection group in the specific embodiment shown corresponds to two sampling applications for injection channels. Similar to the above, the group / channel arbitration control unit 12 will recognize that the two channel sampling trigger signals at times t6 and t7 do not belong to the regular group. Therefore, in the absolute counting mode, the real-time values of the incremental accumulator at the above two times will not be captured and stored in the sampling time storage unit dedicated to the regular group.

[0133] At time t8, the packet / channel arbitration control unit 12 discovers that all channels of the injected packet have completed sampling. Therefore, it immediately (as previously mentioned, there may be a slight delay) resumes sampling control for the next channel of the previously interrupted regular packet (i.e., RG#4), thereby generating a channel sampling trigger signal for RG#4. Subsequently, within the time windows {t8-t9}, {t9-t10}, etc., sampling for the remaining regular channels, such as RG#4, RG#5, etc., is completed. Assuming that the real-time value of the incremental accumulator at time t8 is C, similarly, the real-time values C, C+n, etc. of the incremental accumulator at times t8, t9, etc., will be captured and stored in the same sampling time register.

[0134] contrast Figure 6 and Figure 7 , also refer to the definition difference between absolute counting mode and relative counting mode mentioned above, Figure 7It can be clearly observed that in the relative counting mode, the incremental accumulator should be initialized to the zero value when each regular channel sampling trigger signal is generated ( Figure 7 In absolute counting mode, the counter is initialized to 1, rather than continuously increasing and accumulating as in absolute counting mode.

[0135] like Figure 6 As shown, in the absolute counting mode, at the sampling completion time of the conventional channels such as t3, t4, t6, t9, and t10, the real-time values of the sampling time register unit (i.e., A, A+n, A+2n, C, and C+n) are indeed the corresponding sampling start time values of these conventional channels.

[0136] like Figure 7 As shown, in the relative counting mode, at the sampling completion time of the conventional channels such as t3, t4, t6, t9, and t10, the accumulated results of the real-time values of the sampling time register units (i.e., A, A+n, A+2n, A+2n+B, A+3n+B) are indeed the corresponding sampling start time values of these conventional channels.

[0137] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. An analog-to-digital converter, characterized in that include: a channel multiplexing selection unit, configured to determine a target channel to be processed by AD from a plurality of input channels based on at least one input analog signal and at least one channel selection signal corresponding to the analog signal, and to determine a target analog signal corresponding to the channel to be processed by AD, and to transmit the target analog signal to the AD circuit for actual analog-to-digital conversion processing; A group / channel control configuration unit, configured to determine control configuration information based on the received configuration information of the MCU system, wherein the control configuration information is used to configure and control the acquisition and transfer processing of different groups or channels; a group / channel arbitration control unit, configured to determine a channel selection signal and a channel sampling trigger signal for each channel based on the received global sampling trigger signal, the control configuration information, and a processing sequence or priority rule pre-programmed for each channel, wherein the channel selection signal is used to indicate the selection of the channel, and the channel sampling trigger signal is used to indicate to the AD circuit to start the current AD processing; An incremental accumulator, driven by the working clock of the analog-to-digital converter, is used to incrementally and cumulatively update each working clock cycle of the analog-to-digital converter, so as to provide a time reference for capturing the sampling time; At least one sampling time register unit, configured to capture and store the real-time value of the incremental accumulator based on the channel sampling trigger signal as the sampling time, and combine the sampling time with the channel conversion result content and provide the result to the MCU system; The global sampling trigger signal is generated by other circuit logic outside the analog-to-digital converter and / or by a certain circuit logic inside the ADC circuit. The global sampling trigger signal is used to start the sequential and continuous sampling process of analog signals of multiple channels; When the incremental accumulator is in absolute counting mode, it is used to regard the global sampling trigger signal as a time zero point, and start to accumulate incrementally from the corresponding zero point value. When it increases to the maximum value or encounters an MCU system reset, the incremental accumulator will return to the zero point value; When the incremental accumulator is in relative counting mode, it is used to regard the global sampling trigger signal and the sampling trigger signal of any channel as a time zero point, start incremental accumulation from the corresponding zero point value, capture the real-time value of the incremental accumulator when the next sampling is started, and then return to the zero point value.

2. The analog-to-digital converter according to claim 1, wherein When the incremental accumulator is in the absolute counting mode, the sampling time register unit is used to reflect the sampling time starting time value of each channel.

3. The analog-to-digital converter according to claim 1, wherein: When the incremental accumulator is in the relative counting mode, the sampling time register unit is used to reflect the time consumed for completing the sampling process of the latest historical channel.

4. The analog-to-digital converter according to claim 1, wherein: After a valid global sampling trigger signal appears, the first sampling time captured by the sampling time register unit represents the time difference between the valid global sampling trigger signal and the first valid channel sampling trigger signal.

5. The analog-to-digital converter according to claim 1, wherein: The MCU system is used to calculate the sampling start time point of each channel according to the sampling time captured by the sampling time storage unit.

6. The analog-to-digital converter according to claim 1, wherein: When the MCU system does not need to know the sampling time information of each channel, the incremental accumulator and the sampling time register unit are in an idle state and are not used.

7. A chip, characterized in that The analog-to-digital converter comprises the analog-to-digital converter according to any one of claims 1 to 6.

8. An electronic device, characterized in that The device comprises the analog-to-digital converter according to any one of claims 1 to 6 or the chip according to claim 7.

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