Substrate comprising inductors and capacitors located in the encapsulation layer

Abstract

A package includes a power amplifier and a substrate coupled to the power amplifier. The substrate includes an encapsulation layer, a capacitor device located in the encapsulation layer, an inductor located in the encapsulation layer, at least one first dielectric layer coupled to a first surface of the encapsulation layer, and a plurality of first interconnects coupled to the first surface of the encapsulation layer. The plurality of first interconnects is located in at least the at least one first dielectric layer. The plurality of first interconnects is coupled to the capacitor device and the inductor. The inductor and the capacitor device are configured to be electrically coupled together to operate as elements of a matching network for the power amplifier. The capacitor device is configured to be coupled to ground.

Description

[0001] Cross-reference to related applications

[0002] This patent application claims priority and benefit to pending non-provisional application No. 16 / 927,823, filed on July 13, 2020, with the United States Patent and Trademark Office, the entire contents of which are incorporated herein by reference as if fully set forth herein and used for all applicable purposes. Technical Field

[0003] Various features relate to the package and the substrate, but more specifically to the substrate including inductors and capacitors embedded in the encapsulation layer. Background Technology

[0004] Figure 1 The illustration shows a package 100 including a substrate 102, an integrated device 106, a capacitor 108, and an inductor 109. The integrated device 106 is coupled to the surface of the substrate 102. The capacitor 108 and the inductor 109 are coupled to the surface of the substrate 102. Both the capacitor 108 and the inductor 109 are discrete surface mount devices (SMDs). The substrate 102 includes at least one dielectric layer 120 and multiple interconnects 122. Multiple solder interconnects 130 are coupled to the substrate 102. The combination of the capacitor 108 and the inductor 109 occupies a significant amount of space and substrate surface area. Small wireless devices have space constraints and may not be able to accommodate many capacitors and / or inductors. Wireless devices may rely on many capacitors and / or inductors to provide efficient and effective wireless communication. The relatively large size of surface mount capacitors and inductors can limit the wireless performance of small wireless devices because not enough surface mount capacitors and inductors can be installed within a small wireless device. There is still a need to provide capacitors and inductors with better form factors and smaller dimensions so that they can be implemented in smaller devices. Summary of the Invention

[0005] Various features relate to the package and the substrate, but more specifically to the substrate including inductors and capacitors embedded in the encapsulation layer.

[0006] One example provides a substrate including an encapsulation layer, a capacitor device located within the encapsulation layer, an inductor located within the encapsulation layer, at least one first dielectric layer coupled to a first surface of the encapsulation layer, and a plurality of first interconnects coupled to the first surface of the encapsulation layer. The plurality of first interconnects are located at least in at least one first dielectric layer. The plurality of first interconnects are coupled to the capacitor device and the inductor.

[0007] Another example provides a package including a power amplifier and a substrate coupled to the power amplifier. The substrate includes an encapsulation layer, a capacitor device located within the encapsulation layer, an inductor located within the encapsulation layer, at least one first dielectric layer coupled to a first surface of the encapsulation layer, and a plurality of first interconnects coupled to the first surface of the encapsulation layer. The plurality of first interconnects are located at least in at least one first dielectric layer. The plurality of first interconnects are coupled to the capacitor device and the inductor. The inductor and capacitor device are configured to be electrically coupled together to operate as elements of a matching network for the power amplifier. The capacitor device is configured to be coupled to ground.

[0008] Another example provides an apparatus including a component for encapsulation, a component for capacitance located within the component for encapsulation, a component for inductance located within the component for encapsulation, at least one first dielectric layer coupled to a first surface of the component for encapsulation, and a plurality of first interconnects coupled to the first surface of the component for encapsulation. The plurality of first interconnects are located at least in at least one first dielectric layer. The plurality of first interconnects are coupled to the component for capacitance and the component for inductance.

[0009] Another example provides a method for manufacturing a substrate. The method provides at least one capacitor device. The method provides at least one inductor device. The method forms an encapsulation layer that encapsulates the at least one capacitor device and the at least one inductor device. The method forms at least one first dielectric layer over a first surface of the encapsulation layer. The method forms a plurality of first interconnects over the first surface of the encapsulation layer. The plurality of first interconnects are located at least within the at least one first dielectric layer. The plurality of first interconnects are coupled to the capacitor device and the inductor device. Attached Figure Description

[0010] The various features, properties and advantages will become apparent from the detailed description set forth below when understood in conjunction with the accompanying drawings, in which the same reference numerals are always used to identify them.

[0011] Figure 1 The illustration shows a package including a surface-mount inductor and a surface-mount capacitor coupled to a substrate.

[0012] Figure 2 The illustration shows a cross-sectional view of an exemplary substrate including capacitor devices and inductor devices.

[0013] Figure 3 A cross-sectional view of an exemplary package is shown, the package including a substrate on which capacitor devices and inductor devices are implemented.

[0014] Figure 4 A cross-sectional view of an exemplary package is shown, the package including a substrate on which capacitor devices and inductor devices are implemented.

[0015] Figure 5 A cross-sectional view of an exemplary package is shown, the package including a substrate on which capacitor devices and inductor devices are implemented.

[0016] Figure 6 A cross-sectional view of an exemplary package is shown, which includes a substrate on which capacitor devices and inductors are implemented.

[0017] Figure 7 An exemplary wafer comprising multiple capacitor devices is illustrated.

[0018] Figure 8 An exemplary wafer comprising multiple inductor devices is illustrated.

[0019] Figures 9A-9D An exemplary sequence for manufacturing capacitor devices is illustrated.

[0020] Figures 10A-10B An exemplary sequence for manufacturing inductor devices is illustrated.

[0021] Figures 11A-11C An exemplary sequence for fabricating a substrate comprising at least a capacitor device and at least one inductor is illustrated.

[0022] Figures 12A-12D An exemplary sequence for fabricating a substrate comprising at least a capacitor device and at least one inductor device is illustrated.

[0023] Figure 13 An exemplary flowchart of a method for manufacturing a substrate comprising at least a capacitor device and at least one inductor device is illustrated.

[0024] Figure 14 The diagram illustrates possible filters for various frequencies.

[0025] Figure 15 The diagram illustrates a conceptual matching network coupled to a power amplifier and an antenna.

[0026] Figure 16 The diagrams illustrate various circuit diagrams for matching networks.

[0027] Figure 17 The diagram illustrates the performance of various exemplary matched networks for different frequencies.

[0028] Figure 18 The illustrations depict various electronic devices that can be integrated with the dies, integrated devices, integrated passive devices (IPDs), device packages, packages, integrated circuits, and / or PCBs described herein. Detailed Implementation

[0029] In the following description, specific details are set forth to provide a thorough understanding of various aspects of this disclosure. However, those skilled in the art will understand that these aspects can be practiced without these specific details. For example, circuits may be shown as block diagrams to avoid obscuring these aspects with unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail to avoid obscuring aspects of this disclosure.

[0030] This disclosure describes a package including a power amplifier and a substrate coupled to the power amplifier. The substrate includes an encapsulation layer, a capacitor device located within the encapsulation layer, an inductor located within the encapsulation layer, at least one first dielectric layer coupled to a first surface of the encapsulation layer, and a plurality of first interconnects coupled to the first surface of the encapsulation layer. The plurality of first interconnects are located at least in at least one first dielectric layer. The plurality of first interconnects are coupled to the capacitor device and the inductor. The substrate may include at least one second dielectric layer coupled to a second surface of the encapsulation layer, and may include at least one second interconnect coupled to the second surface of the encapsulation layer. At least one second interconnect is located at least in at least one second dielectric layer. The encapsulation layer may include a plurality of via interconnects. The inductor may be defined by some of the plurality of via interconnects and at least one first interconnect. The inductor may be part of an inductor device. The inductor device may include a dielectric layer, a plurality of via interconnects, and a plurality of interconnects. The inductor device may be embedded in the encapsulation layer. The capacitor device may include a metal-insulator-metal (MIM) capacitor. Capacitor devices can be configured to be electrically coupled to inductors. Inductors and capacitor devices are configured to be electrically coupled together to operate as elements of a matching network for a power amplifier (e.g., a matching network between a power amplifier and an antenna). Capacitor devices are configured to be coupled to ground. The design and / or configuration of (multiple) capacitor devices and (multiple) inductors can provide a more compact form factor to the substrate, allowing more capacitor devices and / or inductors to be placed within the substrate. The ability to provide a substrate with several capacitor devices and / or inductors allows for better impedance matching and thus better and improved signal filtering (e.g., broadband filtering) across a wider frequency range. The design and configuration of substrates with capacitors and inductors provide an overall better form factor and smaller size (while still providing effective performance capabilities), enabling the implementation of substrates, capacitors, and inductors in smaller devices.

[0031] Exemplary packages and substrates including inductors and capacitors embedded in the encapsulation layer.

[0032] Figure 2An example of a substrate 202 including an inductor and a capacitor embedded in an encapsulation layer is illustrated. The substrate 202 includes an encapsulation layer 203, at least one inductor device 205, at least one capacitor device 207, at least one first dielectric layer 204, at least one second dielectric layer 206, a plurality of first interconnects 240, and a plurality of second interconnects 260.

[0033] Substrate 202 includes inductor device 205a, inductor device 205b, capacitor device 207a, and capacitor device 207b. Inductor device 205a, inductor device 205b, capacitor device 207a, and capacitor device 207b are located within encapsulation layer 203 (e.g., laterally encapsulated by encapsulation layer 203). Encapsulation layer 203 may include a mold, resin, and / or epoxy resin. Encapsulation layer 203 may be a component for encapsulation.

[0034] At least one first dielectric layer 204 is located on and coupled to the first surfaces of (i) the encapsulation layer 203, (ii) the inductor device 205a, (iii) the inductor device 205b, (iv) the capacitor device 207a, and (v) the capacitor device 207b. At least one second dielectric layer 206 is located on and coupled to the second surfaces of (i) the encapsulation layer 203, (ii) the inductor device 205a, (iii) the inductor device 205b, (iv) the capacitor device 207a, and (v) the capacitor device 207b. At least one first dielectric layer 204 and / or at least one second dielectric layer 206 may comprise polyimide. Different embodiments may include different dielectric layers for at least one first dielectric layer 204 and / or at least one second dielectric layer 206.

[0035] A plurality of first interconnects 240 are located in and above at least one first dielectric layer 204. The plurality of first interconnects 240 may be coupled to inductor device 205a, inductor device 205b, capacitor device 207a, and / or capacitor device 207b. A plurality of second interconnects 260 are located in and above at least one second dielectric layer 206. The plurality of second interconnects 260 may be coupled to inductor device 205a, inductor device 205b, capacitor device 207a, and / or capacitor device 207b.

[0036] Inductor device 205a and inductor device 205b can both be represented by inductor device 205. Inductor device 205 can be a component for inductance. Inductor device 205 includes a core layer 250, a plurality of interconnects 251, a plurality of interconnects 255, a plurality of interconnects 257, a dielectric layer 254, and a dielectric layer 256. Core layer 250 may include a dielectric layer. Core layer 250 may include a substrate. Core layer 250 can be an inductor core layer. A plurality of interconnects 251 (e.g., vias, via interconnects) pass through core layer 250. A plurality of interconnects 251, a plurality of interconnects 255, and a plurality of interconnects 257 can define an inductor. The inductor can be configured as a solenoid inductor. Inductor device 205a and inductor device 205b can have the same or different configurations (e.g., size, shape, number of turns, number of windings) to provide the same or different inductance.

[0037] Capacitor device 207a and capacitor device 207b can both be represented by capacitor device 207. Capacitor device 207 can be a component for capacitance. Capacitor device 207 includes a substrate 270, at least one dielectric layer 272, a plurality of interconnects 275, and an insulating layer 274. Substrate 270 can be a capacitor substrate. The plurality of interconnects 275 includes interconnects 275a and interconnects 275b. Capacitor device 207 includes capacitor 271. Capacitor 271 can be a metal-insulator-metal (MIM) capacitor. Capacitor 271 can be defined by interconnects 275a, insulating layer 274, and interconnects 275b. Insulating layer 274 is located between interconnects 275a and interconnects 275b. Insulating layer 274 can include a high-k dielectric layer. For example, insulating layer 274 can include silicon nitride (SiN). Capacitor device 207 can include several metal layers (e.g., M1, M2, M3, M4). Interconnect 275a may be on the first capacitor metal layer (M1), and interconnect 275b may be on the second capacitor metal layer (M2). However, the metal layer of capacitor 271 may be defined on any metal layer of capacitor device 207. Capacitor 271 may be a component for capacitance.

[0038] Inductor device 205a can be configured to be electrically coupled to capacitor device 207a via a plurality of first interconnects 240 and / or a plurality of second interconnects 260. Inductor device 205b can be configured to be electrically coupled to capacitor device 207b via a plurality of first interconnects 240 and / or a plurality of second interconnects 260. Inductor device 205a and capacitor device 207a can be configured to be electrically coupled to inductor device 205b and / or capacitor device 207b via a plurality of first interconnects 240 and / or a plurality of second interconnects 260.

[0039] As will be further described below, inductor device 205a, inductor device 205b, capacitor device 207a and / or capacitor device 207b can be configured to operate as output matching elements(s) of a power amplifier (PA). Inductor device 205a, inductor device 205b, capacitor device 207a and / or capacitor device 207b can be part of the output matching network of the power amplifier.

[0040] Figure 3 The illustration shows a package 300 including a substrate 202, a power amplifier (PA) 308, and an integrated device 304. The substrate 202 is similar to... Figure 2 The substrate 202 is described in the figure. The substrate 202 includes an encapsulation layer 203, at least one first dielectric layer 204, at least one second dielectric layer 206, a plurality of first interconnects 240, a plurality of second interconnects 260, a plurality of interconnects 330, inductor devices 205a and 205b, capacitor devices 207a and 207b. The plurality of interconnects 330 (e.g., vias, via interconnects) pass through the encapsulation layer 203. The plurality of interconnects 330 are coupled to the plurality of interconnects 240 and the plurality of interconnects 260.

[0041] Power amplifier 308 is coupled to a first surface of substrate 202 via a plurality of solder interconnects 380. Integrated device 304 is coupled to the first surface of substrate 202 via a plurality of solder interconnects 340. Power amplifier 308 may be configured to amplify at least one electrical signal (e.g., an electrical signal from at least one transmit path). Power amplifier 308 may be a component for power amplification. In some embodiments, power amplifier 308 may be configured to be coupled to at least one antenna (e.g., via an output matching network). A plurality of solder interconnects 310 are coupled to a second surface of substrate 202. The plurality of solder interconnects 310 may be coupled to a plurality of interconnects 260.

[0042] Power amplifier 308 is configured to be electrically coupled to inductor device 205a, capacitor device 207a, inductor device 205b, and capacitor device 207b via multiple interconnects 240 and / or multiple interconnects 260. Inductor device 205a, capacitor device 207a, inductor device 205b, and / or capacitor device 207b may define an output matching network (e.g., for power amplifier 308). Examples of various configurations of the output matching network are given below at least... Figure 16 The diagrams and descriptions are shown in the text.

[0043] Figure 3The illustration shows capacitor devices 207a and 207b located (e.g., embedded) in a substrate 202, such that capacitors (e.g., 271a, 271b) are located near a second surface (e.g., a bottom surface) of the substrate 202. For example, capacitors 271a and 271b are located near at least one dielectric layer 206. The substrate 270 of the capacitor devices (e.g., 207a, 207b) may be coupled to at least one dielectric layer 206. In some embodiments, the capacitor devices may be located differently in the substrate.

[0044] Figure 4 The illustration shows a package 400 including a substrate 402, a power amplifier (PA) 408, and an integrated device 404. The substrate 402 includes an encapsulation layer 203, at least one first dielectric layer 204, at least one second dielectric layer 206, a plurality of first interconnects 240, a plurality of second interconnects 260, a plurality of interconnects 330, inductor devices 205a and 205b, capacitor devices 207a and 207b. The plurality of interconnects 330 (e.g., vias, via interconnects) pass through the encapsulation layer 203. The plurality of interconnects 330 are coupled to the plurality of interconnects 240 and the plurality of interconnects 260. The substrate 402 is similar to... Figure 2 and Figure 3 The substrate 202 described herein, and therefore includes, with Figure 2 and Figure 3 Components similar to substrate 202. However, in Figure 4 In this configuration, capacitor devices 207a and 207b are located (e.g., embedded) in substrate 402 such that the capacitors (e.g., 271a, 271b) are located near a first surface (e.g., top surface) of substrate 402. For example, capacitors 271a and 271b are located near integrated device 404. The substrate 270 of the capacitor devices (e.g., 207a, 207b) can be coupled to at least one dielectric layer 206. Therefore, in Figure 4 In, with Figure 2 and Figure 3 Compared to the capacitor device shown, the capacitor device is vertically flipped. Therefore, in some embodiments, the capacitor device may be located upright and / or upside down in the substrate.

[0045] Power amplifier 408 is coupled to a first surface of substrate 402 via a plurality of solder interconnects 480. Integrated device 404 is coupled to the first surface of substrate 402 via a plurality of solder interconnects 440. Power amplifier 408 may be configured to amplify at least one electrical signal (e.g., an electrical signal from at least one transmit path). Power amplifier 408 may be a component for power amplification. In some embodiments, power amplifier 408 may be configured to be coupled to at least one antenna (e.g., via an output matching network). The output matching network of power amplifier 408 may include inductor device 205a, capacitor device 207a, inductor device 205b, and / or capacitor device 207b.

[0046] Figure 5 The illustration shows a package 500 including a substrate 502, a power amplifier (PA) 508, and an integrated device 304. The substrate 502 is similar to... Figure 2 and Figure 3 The substrate 202 described herein, and therefore includes, with Figure 2 and Figure 3 Components similar to substrate 202. Figure 5 In this configuration, the power amplifier is configured to be electrically coupled to a plurality of inductors and capacitors. Substrate 502 includes an encapsulation layer 203, at least one first dielectric layer 204, at least one second dielectric layer 206, a plurality of first interconnects 240, a plurality of second interconnects 260, a plurality of interconnects 330, inductor devices 205a, 205b, and 205c, and capacitor devices 207a, 207b, and 207c. A plurality of interconnects 330 (e.g., vias, via interconnects) pass through the encapsulation layer 203. The plurality of interconnects 330 are coupled to the plurality of interconnects 240 and the plurality of interconnects 260. The plurality of interconnects 330, inductor devices 205a, 205b, 205c, capacitor devices 207a, 207b, and 207c are located within the encapsulation layer 203.

[0047] Power amplifier 508 is coupled to a first surface of substrate 502 via a plurality of solder interconnects 580. Integrated device 304 is coupled to the first surface of substrate 502 via a plurality of solder interconnects 340. Power amplifier 508 may be configured to amplify at least one electrical signal (e.g., an electrical signal from at least one transmit path). Power amplifier 508 may be a component for power amplification. In some embodiments, power amplifier 508 may be configured to be coupled to at least one antenna (e.g., via an output matching network). A plurality of solder interconnects 310 are coupled to a second surface of substrate 502. The plurality of solder interconnects 310 may be coupled to a plurality of interconnects 260.

[0048] Power amplifier 508 is configured to be electrically coupled to inductor device 205c, capacitor device 207c, inductor device 205b, capacitor device 207b, inductor device 205a, and capacitor device 207a via multiple interconnects 240 and / or multiple interconnects 260. Inductor device 205a, capacitor device 207a, inductor device 205b, capacitor device 207b, inductor device 205c, and / or capacitor device 207c may define an output matching network (e.g., for power amplifier 508). The following at least... Figure 16 Examples of various output matching networks are illustrated and described in the diagram. As will be further described, increasing the number of inductors and / or capacitors in the output matching network can help provide better impedance matching over a wider frequency range.

[0049] In some implementations, at least one inductor may be implemented in the encapsulation layer of the substrate. Figure 6 The illustration shows a package 600 including a power amplifier 508, an integrated device 304, and a substrate 602. The substrate 602 is similar to... Figure 2 and Figure 3 The substrate 202 described herein, and therefore includes, with Figure 2 and Figure 3 Components similar to substrate 202. Figure 6 In this configuration, the power amplifier is electrically coupled to additional inductors and capacitors. Substrate 602 also includes at least one inductor formed by interconnects in and over the encapsulation layer.

[0050] Substrate 602 includes an encapsulation layer 203, at least one first dielectric layer 204, at least one second dielectric layer 206, a plurality of first interconnects 240, a plurality of second interconnects 260, a plurality of interconnects 330, inductor devices 205a, 605a, 605b, capacitor devices 207a, 207b, and 207c. The plurality of interconnects 330 (e.g., vias, via interconnects) pass through the encapsulation layer 203. The plurality of interconnects 330 are coupled to the plurality of interconnects 240 and the plurality of interconnects 260. The plurality of interconnects 330, inductor devices 205a, 605a, 605b, capacitor devices 207a, 207b, and 207c are located within the encapsulation layer 203. The plurality of first interconnects 240 and / or the plurality of second interconnects 260 may include redistributed interconnects. Multiple first interconnects 240 and / or multiple second interconnects 260 can be manufactured using a redistribution layer (RDL) manufacturing process.

[0051] like Figure 6As shown, some of the interconnects from the plurality of interconnects 330, 240, and 260 can be configured to operate as at least one inductor. For example, inductor 605a can be defined by the plurality of interconnects 330a, 240a, and 260a. Similarly, inductor 605b can be defined by the plurality of interconnects 330b, 240b, and 260b. The inductors (e.g., 605a, 605b) can be solenoid inductors. The inductors (e.g., 605a, 605b) can be components for inductance.

[0052] Power amplifier 508 is coupled to a first surface of substrate 602 via a plurality of solder interconnects 580. Integrated device 304 is coupled to the first surface of substrate 602 via a plurality of solder interconnects 340. Power amplifier 508 may be configured to amplify at least one electrical signal (e.g., an electrical signal from at least one transmit path). Power amplifier 508 may be a component for power amplification. In some embodiments, power amplifier 508 may be configured to be coupled to at least one antenna (e.g., via an output matching network). A plurality of solder interconnects 310 are coupled to a second surface of substrate 502. The plurality of solder interconnects 310 may be coupled to a plurality of interconnects 260.

[0053] Power amplifier 508 is configured to be electrically coupled to inductor 605b, capacitor device 207c, inductor 605a, capacitor device 207b, inductor device 205a, and capacitor device 207a via multiple interconnects 240 and / or multiple interconnects 260. Inductor 605b, capacitor device 207a, inductor 605a, capacitor device 207b, inductor device 205a, and / or capacitor device 207a may define an output matching network (e.g., for power amplifier 508). The following at least... Figure 16 Examples of various output matching networks are illustrated and described in the diagram. As will be further described, increasing the number of inductors and / or capacitors in the output matching network can help provide better impedance matching over a wider frequency range.

[0054] The various capacitors and inductors (and combinations thereof) described in this disclosure can be configured to operate as output matching elements (and / or output matching networks) of a power amplifier. The output matching network provided by the capacitors and / or inductors (e.g., output matching elements) can be impedance matching, which helps to match the output impedance of the power amplifier to the input load of another component (e.g., an integrated device, a die) in order to maximize energy transfer between the power amplifier and other components. Combinations of capacitors and inductors can be configured to operate as LC resonators, resonant traps, and / or output matching elements of a power amplifier. As will be stated below at least... Figure 16As further described, the output matching network can have different orders (e.g., first-order, second-order, and third-order output matching networks). Note that capacitors (multiple) and / or inductors (multiple) can be one of many elements in the output matching network. Therefore, the output matching network can include elements other than capacitors (multiple) and / or inductors (multiple) other elements.

[0055] Integrated devices (e.g., 304, 404) may include dies (e.g., bare dies). Integrated devices may include radio frequency (RF) devices, analog devices, passive devices, filters, capacitors, inductors, antennas, transmitters, receivers, surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, light-emitting diode (LED) integrated devices, silicon (Si)-based integrated devices, silicon carbide (SiC)-based integrated devices, GaAs-based integrated devices, GaN-based integrated devices, memories, power management processors, and / or combinations thereof.

[0056] The packages described in this disclosure (e.g., 300, 400, 500, 600) can be radio frequency (RF) packages. The packages (e.g., 300, 400, 500, 600) can be portions of a radio frequency front-end (RFFE) package. The packages (e.g., 300, 400, 500, 600) can be configured to provide wireless fidelity (WiFi) communication and / or cellular communication (e.g., 2G, 3G, 4G, 5G). The packages (e.g., 300, 400, 500, 600) can be configured to support Global System for Mobile Communications (GSM), Universal Mobile Telecommunications System (UMTS), and / or Long Term Evolution (LTE).

[0057] The packages described in this disclosure (e.g., 300, 400, 500, 600) can be coupled to a board (e.g., a printed circuit board (PCB)) via multiple solder interconnects. Substrates (e.g., 202, 402, 502, 602) can be configured as intermediaries between the integrated device and the board (e.g., the PCB). The substrates (e.g., 202, 402, 502, 602) can include one or more dielectric layers (e.g., 204, 206) and one or more metal layers defining interconnects 240 and / or interconnects 260. Capacitor devices (e.g., 207a, 207b, 207c), inductor devices (e.g., 205a, 205b, 205c), and / or inductors (e.g., 605a, 605b) can be configured to be electrically coupled together to operate as elements of a matching network between a power amplifier and an antenna. Some or all of the capacitor devices (e.g., 207a, 207b, 207c), inductor devices (e.g., 205a, 205b, 205c), and / or inductors (e.g., 605a, 605b) may be configured to be coupled to ground. The capacitor and inductor devices described in this disclosure may be fabricated as part of a wafer. The wafer is diced to form individual capacitor devices or individual inductor devices. Figure 7 and Figure 8 An exemplary wafer with corresponding capacitor and inductor devices is illustrated.

[0058] Figure 7 The illustration shows a wafer 700 comprising multiple capacitor devices 207 (e.g., 207a, 207b, 207c, 207d). Each capacitor device includes a substrate 270, at least one dielectric layer 272, multiple interconnects 275, and an insulating layer 274. Each capacitor device includes a capacitor 271. The capacitor 271 may be a metal-insulator-metal (MIM) capacitor.

[0059] Figure 8 The illustration shows a wafer 800 including multiple inductor devices 205 (e.g., 205a, 205b, 205c). Each inductor device includes a core layer 250, multiple interconnects 251, multiple interconnects 255, multiple interconnects 257, a dielectric layer 254, and a dielectric layer 256. The core layer 250 may include a dielectric layer. The core layer 250 may include a substrate (e.g., silicon (Si)). Multiple interconnects 251 (e.g., vias) pass through the core layer 250. The multiple interconnects 251, multiple interconnects 255, and multiple interconnects 257 may define an inductor. The inductor may be configured as a solenoid inductor.

[0060] Wafers comprising multiple capacitor devices or multiple inductor devices have been described; the processes for manufacturing capacitor devices and inductor devices will now be described below.

[0061] Exemplary sequence for manufacturing capacitor devices

[0062] In some implementations, manufacturing a capacitor device includes several processes. Figures 9A-9D The illustration shows an exemplary sequence for providing or manufacturing capacitor devices. In some embodiments, Figures 9A-9D The sequence can be used to provide or manufacture capacitor device 207. However, Figures 9A-9D The process can be used to manufacture any capacitor device described in this disclosure.

[0063] It should be noted that Figures 9A-9D The sequence can combine one or more stages to simplify and / or clarify the sequence used to provide or manufacture capacitor devices. In some embodiments, the order of processes can be changed or modified. In some embodiments, one or more processes can be substituted or replaced without departing from the spirit of this disclosure.

[0064] like Figure 9A As shown, stage 1 illustrates the state after substrate 270 has been provided. Substrate 270 may include silicon (Si). Substrate 270 may be provided as a wafer.

[0065] Stage 2 illustrates the state after the formation of multiple interconnects 902. Interconnects 902 can be formed on the surface of substrate 270 using patterning and plating processes. The interconnects 902 can be on the first capacitor metal layer (M1). Interconnects 902 can represent interconnects 275a, such as... Figure 2 As described in [the text].

[0066] Stage 3 illustrates the state after the dielectric layer 910 is formed on the surface of the substrate 270. The dielectric layer 910 can be formed using a deposition process. The dielectric layer 910 may include polyimide. However, different materials may be used for the dielectric layer 910 in different embodiments.

[0067] Stage 4 illustrates the state after the insulating layer 274 is formed on the interconnect 902. The insulating layer 274 can be formed on the interconnect 902 using a deposition process. The insulating layer 274 may include a high-k dielectric layer, such as silicon nitride (SiN). However, different materials may be used for the insulating layer 274 in different embodiments.

[0068] Stage 5 illustrates the state after the dielectric layer 920 is formed on the surface of the dielectric layer 910. The dielectric layer 920 can be formed using a deposition process. The dielectric layer 920 can be similar to or the same as the dielectric layer 910. The dielectric layer 920 may include polyimide. However, different materials may be used for the dielectric layer 920 in different embodiments.

[0069] like Figure 9B As shown, stage 6 illustrates the state after the formation of multiple interconnects 904. Interconnects 904 can be formed on the insulating layer 274 using patterning and plating processes. The interconnects 904 can be on the second capacitor metal layer (M2). Interconnects 904 can represent interconnects 275b, as shown... Figure 2 As described in the diagram. Stage 6 can be illustrated by a capacitor 271 defined by interconnect 902, insulating layer 274, and interconnect 904.

[0070] Phase 7 illustrates the state after dielectric layer 930 is formed over dielectric layer 920 and interconnect 904. Dielectric layer 930 can be formed using a deposition process. Dielectric layer 930 can be similar to or the same as dielectric layer 920. Dielectric layer 930 may include polyimide. However, different materials may be used for dielectric layer 930 in different embodiments.

[0071] Stage 8 illustrates the formation of multiple cavities 931 in the dielectric layer 930. The cavities 931 can be formed using laser processes (e.g., laser ablation), photolithography processes (e.g., exposure and development), or etching processes.

[0072] like Figure 9C As shown, stage 9 illustrates the state after a plurality of interconnects 906 have been formed in and / or on dielectric layer 932. Dielectric layer 932 may represent dielectric layers 910, 920, and / or 930. Interconnects 906 may be formed using patterning and plating processes. Interconnects 906 may be formed in cavity 931. Interconnects 906 may include vias, pads, and / or traces. Some of the interconnects from the plurality of interconnects 906 may be formed on a third metal layer (M3).

[0073] Phase 10 illustrates the state after dielectric layer 940 is formed over dielectric layer 932 and interconnect 906. Dielectric layer 940 can be formed using a deposition process. Dielectric layer 940 can be similar to or the same as dielectric layer 932. Dielectric layer 940 may include polyimide. However, different materials may be used for dielectric layer 940 in different embodiments.

[0074] Stage 11 illustrates the formation of multiple cavities 941 in the dielectric layer 940. The cavities 941 can be formed using laser processes (e.g., laser ablation), photolithography processes (e.g., exposure and development), or etching processes.

[0075] like Figure 9DAs shown, stage 12 illustrates the state after a plurality of interconnects 908 have been formed in and / or on dielectric layer 942. Dielectric layer 942 may represent dielectric layers 910, 920, 930, 932, and / or 940. Interconnects 908 may be formed using patterning and plating processes. Interconnects 908 may be formed in cavity 941. Interconnects 908 may include vias, pads, and / or traces. Some of the interconnects from the plurality of interconnects 908 may be formed on a fourth metal layer (M4).

[0076] Phase 13 illustrates the state after dielectric layer 950 is formed over dielectric layer 942 and interconnect 908. Dielectric layer 950 can be formed using a deposition process. Dielectric layer 950 can be similar to or the same as dielectric layer 942. Dielectric layer 950 may include polyimide. However, different materials may be used for dielectric layer 950 in different embodiments.

[0077] Phase 14 illustrates the state after the wafer is diced to form multiple capacitor devices 207 (e.g., 207a, 207b, 207c, 207d). Each capacitor device 207 includes a substrate 270, at least one dielectric layer 272, multiple interconnects 275, and an insulating layer 274. The at least one dielectric layer 272 may represent dielectric layers 942 and / or 950. Each capacitor device includes a capacitor 271. The capacitor 271 may be a metal-insulator-metal (MIM) capacitor.

[0078] Different implementations may use different processes to form interconnects and / or (multiple) metal layers. In some implementations, chemical vapor deposition (CVD) and / or physical vapor deposition (PVD) processes are used to form (multiple) metal layers. For example, sputtering, spraying, and / or plating processes may be used to form (multiple) metal layers.

[0079] Exemplary sequence for manufacturing inductor devices

[0080] In some implementations, manufacturing a capacitor device includes several processes. Figures 10A-10B The illustration shows an exemplary sequence for providing or manufacturing inductor devices. In some embodiments, Figures 10A-10B The sequence can be used to provide or manufacture inductor device 205. However, Figures 10A-10B The process can be used to manufacture any inductor device described in this disclosure.

[0081] It should be noted that Figures 10A-10BThe sequence can be combined to simplify and / or clarify the sequence used to provide or manufacture inductor devices. In some embodiments, the order of processes can be changed or modified. In some embodiments, one or more processes can be substituted or replaced without departing from the spirit of this disclosure.

[0082] like Figure 10A As shown, stage 1 illustrates the state after the core layer 250 has been provided. The core layer 250 may include a substrate such as silicon (Si). The core layer 250 may be provided as a wafer.

[0083] Stage 2 illustrates the formation of multiple cavities 1002 in the core layer 250. The cavities 1002 can be formed using a laser process (e.g., laser ablation) or an etching process.

[0084] Stage 3 illustrates the state after a plurality of interconnects 251 have been formed in cavity 1002. Interconnects 251 can be formed in cavity 1002 using a plating or bonding process. Interconnects 251 pass through core layer 250. Interconnects 251 may include vias (e.g., via interconnects).

[0085] like Figure 10B As shown, stage 4 illustrates the state after (i) forming a plurality of interconnects 255 on a first surface of core layer 250 and (ii) forming a plurality of interconnects 257 on a second surface of core layer 250. The plurality of interconnects 255 and 257 can be formed using patterning and plating processes. The plurality of interconnects 255 and 257 can be coupled to a plurality of interconnects 251. The plurality of interconnects 251, the plurality of interconnects 255, and the plurality of interconnects 257 can define an inductor (e.g., can define the windings of an inductor).

[0086] Phase 5 illustrates the state after (i) forming a dielectric layer 254 on a first surface of the core layer 250 and (ii) forming a dielectric layer 256 on a second surface of the core layer 250. Dielectric layers 254 and 256 can be formed using a deposition process. Dielectric layers 254 and 256 may comprise polyimide. However, different embodiments may use different materials for dielectric layers 254 and 256.

[0087] Phase 6 illustrates the state after the wafer is diced to form multiple inductor devices 205 (e.g., 205a, 205b, 205c). Each inductor device 205 includes a core layer 250, multiple interconnects 251, multiple interconnects 255, multiple interconnects 257, a dielectric layer 254, and a dielectric layer 256. The multiple interconnects 251, multiple interconnects 255, and multiple interconnects 257 may define an inductor (e.g., a solenoid inductor).

[0088] Different implementations may use different processes to form interconnects and / or (multiple) metal layers. In some implementations, chemical vapor deposition (CVD) and / or physical vapor deposition (PVD) processes are used to form (multiple) metal layers. For example, sputtering, spraying, and / or plating processes may be used to form (multiple) metal layers.

[0089] Exemplary sequence for fabricating substrates including capacitor devices and inductors

[0090] In some embodiments, fabricating a substrate that includes capacitor devices and inductors involves several processes. Figures 11A-11C The illustration shows an exemplary sequence for providing or manufacturing substrates including capacitor devices and inductors. In some embodiments, Figures 11A-11C The sequence can be used to provide or manufacture Figure 6 The substrate is 602. However, Figures 11A-11C The process can be used to manufacture any substrate described in this disclosure.

[0091] It should be noted that Figures 11A-11C The sequence can be combined to simplify and / or clarify the sequence used to provide or manufacture the substrate. In some embodiments, the order of the processes can be changed or modified. In some embodiments, one or more processes can be substituted or replaced without departing from the spirit of this disclosure.

[0092] like Figure 11A As shown, stage 1 illustrates the state after the carrier 1100 has been provided. The carrier 1100 may include a substrate.

[0093] Phase 2 illustrates the state after multiple capacitor devices 207 (e.g., 207a, 207b) have been placed on the carrier 1100. The multiple capacitor devices 207 can be placed using a pick-and-place process. The multiple capacitor devices 207 are placed on the carrier 1100 such that the substrate 270 of the capacitor devices 207 contacts the carrier 1100. In this example, capacitor 271 may be located near the carrier 1100. In some embodiments, one or more capacitor devices may be placed on the carrier 1100 such that the substrate 270 is positioned away from the carrier 1100. Therefore, the capacitor devices 207 may be placed upright and / or upside down on the carrier 1100. Figures 9A-9D The illustrations and descriptions provide examples of the processes used to manufacture capacitor devices.

[0094] Stage 3 illustrates the state after the encapsulation layer 203 is formed on the carrier 1100. The encapsulation can be formed using compression and transfer molding, sheet molding, or liquid molding processes. The encapsulation layer 203 can at least partially encapsulate multiple capacitor devices 207. In some embodiments, the encapsulation layer 203 can be formed on the multiple capacitor devices 207, and portions of the encapsulation layer 203 can be removed (e.g., ground) so that the top surface of the encapsulation layer 203 is coplanar with the multiple capacitor devices 207. The encapsulation layer 203 may include a mold, resin, and / or epoxy resin. The encapsulation layer 203 can be a component for encapsulating the layer 203. The encapsulation layer 203 can be photoetchable.

[0095] like Figure 11B As shown, stage 4 illustrates the state after the carrier 1100 has been decoupled from the encapsulation layer 203 and the plurality of capacitor devices 207. Decoupling the carrier 1100 may include removing, separating, grinding and / or dissolving the carrier 1100 using mechanical and / or chemical processes.

[0096] Stage 5 illustrates the state after the formation of multiple cavities 1101 in the encapsulation layer 203. The cavities 1101 can be formed using laser processes (e.g., laser ablation), photolithography processes (e.g., exposure and development), or etching processes.

[0097] Stage 6 illustrates the state after a plurality of interconnects 330 have been formed in cavity 1101. The interconnects 330 can be formed in cavity 1101 using a plating or bonding process. The interconnects 330 pass through encapsulation layer 203. The interconnects 330 may include vias (e.g., via interconnects).

[0098] Stage 7 illustrates the state after (i) forming a plurality of interconnects 1120 on a first surface of encapsulation layer 203 and (ii) forming a plurality of interconnects 1130 on a second surface of encapsulation layer 203. The plurality of interconnects 1120 and 1130 can be formed using patterning and plating processes. The plurality of interconnects 1120 and 1130 can be coupled to a plurality of interconnects 330. At least some of the interconnects from the plurality of interconnects 330, the plurality of interconnects 1120, and the plurality of interconnects 1130 can define inductors (e.g., can define inductor windings), such as inductors 605a and 605b. Some of the interconnects from the plurality of interconnects 1120 and 1130 can be coupled to capacitor devices 207a and 207b. For example, some of the interconnects from the plurality of interconnects 1120 and 1130 can be coupled to the interconnects of capacitor devices 207a and 207b.

[0099] like Figure 11CAs shown, stage 8 illustrates the state after (i) forming a dielectric layer 204 over a first surface of the encapsulation layer 203, capacitor devices (e.g., 207a, 207b), and multiple interconnects 1120, and (ii) forming a dielectric layer 206 over a second surface of the encapsulation layer 203, capacitor devices (e.g., 207a, 207b), and multiple interconnects 1130. Dielectric layers 204 and 206 can be formed using a deposition process. Dielectric layers 204 and 206 may comprise polyimide. However, different embodiments may use different materials for dielectric layers 204 and 206.

[0100] Stage 9 illustrates the formation of a plurality of cavities 1140 in dielectric layer 204 and a plurality of cavities 1160 in dielectric layer 206. Cavities 1140 and 1160 can be formed using laser processes (e.g., laser ablation), photolithography processes (e.g., exposure and development), or etching processes.

[0101] Stage 10 illustrates the state following (i) the formation of a plurality of interconnects 1142 in and / or on dielectric layer 204, and (ii) the formation of a plurality of interconnects 1162 in and / or on dielectric layer 206. Interconnects 1142 and 1162 can be formed using patterning and plating processes. Some interconnects in interconnect 1142 may be formed in cavity 1140. Some interconnects in interconnect 1162 may be formed in cavity 1160. Interconnects 1142 and 1162 may include vias, pads, and / or traces. Interconnects 1120 and 1142 may be represented by a plurality of interconnects 240. Interconnects 1130 and 1162 may be represented by a plurality of interconnects 260. Stage 10 may be illustrated. Figure 6 The substrate 602. Multiple interconnects (e.g., 1120, 1142) and / or multiple interconnects (1130, 1162) may include redistributed interconnects. Multiple interconnects (e.g., 1120, 1142) and / or multiple interconnects (1130, 1162) may be fabricated using a redistributed layer (RDL) fabrication process.

[0102] Exemplary sequence for fabricating substrates including capacitor devices and inductor devices.

[0103] In some embodiments, fabricating a substrate that includes capacitor devices and inductor devices involves several processes. Figures 12A-12D The illustration shows an exemplary sequence of substrates for providing or manufacturing capacitor and inductor devices. In some embodiments, Figures 12A-12D The sequence can be used to provide or manufacture Figure 3 Substrate 202. However, Figures 12A-12D The process can be used to manufacture any substrate described in this disclosure.

[0104] It should be noted that Figures 12A-12DThe sequence can be combined to simplify and / or clarify the sequence of providing or manufacturing the substrate. In some embodiments, the order of the processes can be changed or modified. In some embodiments, one or more processes can be substituted or replaced without departing from the spirit of this disclosure.

[0105] like Figure 12A As shown, stage 1 illustrates the state after the carrier 1100 has been provided. The carrier 1100 may include a substrate.

[0106] Phase 2 illustrates the state after multiple capacitor devices 207 (e.g., 207a, 207b) have been placed on the carrier 1100. The multiple capacitor devices 207 can be placed using a pick-and-place process. The multiple capacitor devices 207 are placed on the carrier 1100 such that the substrate 270 of the capacitor devices 207 contacts the carrier 1100. In this example, capacitor 271 may be located near the carrier 1100. In some embodiments, one or more capacitor devices may be placed on the carrier 1100 such that the substrate 270 is positioned away from the carrier 1100. Therefore, the capacitor devices 207 may be placed upright and / or upside down on the carrier 1100. Figures 9A-9D The illustrations and descriptions provide examples of the processes used to manufacture capacitor devices.

[0107] Phase 3 illustrates the state after multiple inductor devices 205 (e.g., 205a, 205b) are placed on the carrier 1100. The multiple inductor devices 205 can be placed using a pick-and-place process. Figures 10A-10B The illustrations and descriptions provide examples of the processes used to manufacture inductor devices.

[0108] like Figure 12B As shown, stage 4 illustrates the state after the encapsulation layer 203 is formed on the carrier 1100. The encapsulation layer 203 can be formed using compression and transfer molding, sheet molding, or liquid molding processes. The encapsulation layer 203 can at least partially encapsulate a plurality of capacitor devices 207 and a plurality of inductor devices 205. In some embodiments, the encapsulation layer 203 can be formed on the plurality of capacitor devices 207 and the plurality of inductor devices 205, and portions of the encapsulation layer 203 can be removed (e.g., ground) so that the top surface of the encapsulation layer 203 is coplanar with the plurality of capacitor devices 207 and the plurality of inductor devices 205. The encapsulation layer 203 may include a mold, resin, and / or epoxy resin. The encapsulation layer 203 can be a component for encapsulation. The encapsulation layer 203 can be photolithographically readable.

[0109] Phase 5 illustrates the state after the carrier 1100 has been decoupled from the encapsulation layer 203 and the plurality of capacitor devices 207 and the plurality of inductor devices 205. Decoupling the carrier 1100 may include removing, separating, grinding and / or dissolving the carrier 1100 using mechanical and / or chemical processes.

[0110] Stage 6 illustrates the state after the formation of multiple cavities 1101 in the encapsulation layer 203. The cavities 1101 can be formed using laser processes (e.g., laser ablation), photolithography processes (e.g., exposure and development), or etching processes.

[0111] like Figure 12C As shown, stage 7 illustrates the state after a plurality of interconnects 330 have been formed in cavity 1101. The interconnects 330 can be formed in cavity 1101 using a plating or bonding process. The interconnects 330 pass through encapsulation layer 203. The interconnects 330 may include vias (e.g., via interconnects).

[0112] Stage 8 illustrates the state after (i) forming a plurality of interconnects 1120 on the first surface of the encapsulation layer 203 and (ii) forming a plurality of interconnects 1130 on the second surface of the encapsulation layer 203. The plurality of interconnects 1120 and 1130 can be formed using patterning and plating processes. The plurality of interconnects 1120 and 1130 can be coupled to a plurality of interconnects 330. Some of the interconnects from the plurality of interconnects 1120 and 1130 can be coupled to capacitor devices 207a and 207b and inductor devices 205a and 205b. For example, some of the interconnects from the plurality of interconnects 1120 and 1130 can be coupled to the interconnects of capacitor devices 207a and 207b and the interconnects of inductor devices 205a and 205b. In some implementations, at least some of the interconnects from a plurality of interconnects 330, a plurality of interconnects 1120 and a plurality of interconnects 1130 may define an inductor (e.g., inductor 605a, inductor 605b).

[0113] like Figure 12D As shown, stage 9 illustrates the state after (i) forming a dielectric layer 204 over the first surfaces of the encapsulation layer 203, capacitor devices (e.g., 207a, 207b), inductor devices (e.g., 205a, 205b), and multiple interconnects 1120, and (ii) forming a dielectric layer 206 over the second surfaces of the encapsulation layer 203, capacitor devices (e.g., 207a, 207b), inductor devices (e.g., 205a, 205b), and multiple interconnects 1130. Dielectric layers 204 and 206 can be formed using a deposition process. Dielectric layers 204 and 206 may comprise polyimide. However, different embodiments may use different materials for dielectric layers 204 and 206.

[0114] Stage 10 illustrates the formation of a plurality of cavities 1140 in dielectric layer 204 and a plurality of cavities 1160 in dielectric layer 206. Cavities 1140 and 1160 can be formed using laser processes (e.g., laser ablation), photolithography processes (e.g., exposure and development), or etching processes.

[0115] Stage 11 illustrates the state following (i) the formation of a plurality of interconnects 1142 in and / or on dielectric layer 204, and (ii) the formation of a plurality of interconnects 1162 in and / or on dielectric layer 206. Interconnects 1142 and 1162 can be formed using patterning and plating processes. Some interconnects in interconnect 1142 may be formed in cavity 1140. Some interconnects in interconnect 1162 may be formed in cavity 1160. Interconnects 1142 and 1162 may include vias, pads, and / or traces. Interconnects 1120 and 1142 may be represented by a plurality of interconnects 240. Interconnects 1130 and 1162 may be represented by a plurality of interconnects 260. Stage 11 may be illustrated Figure 3 The substrate 202. Multiple interconnects (e.g., 1120, 1142) and / or multiple interconnects (1130, 1162) may include redistributed interconnects. Multiple interconnects (e.g., 1120, 1142) and / or multiple interconnects (1130, 1162) may be fabricated using a redistributed layer (RDL) fabrication process.

[0116] Exemplary flowchart of a method for manufacturing a substrate including capacitor devices and inductors

[0117] In some embodiments, fabricating a substrate that includes capacitor devices and inductors involves several processes. Figure 13 An exemplary flowchart of a method 1300 for providing or manufacturing a substrate including capacitor devices and inductors is illustrated. In some embodiments, Figure 13 Method 1300 can be used to provide or manufacture Figure 6 Substrate 602. However, method 1600 can be used to fabricate any substrate including capacitor devices and inductors (e.g., inductor devices).

[0118] It should be noted that Figure 13 The sequence can be combined to simplify and / or clarify the methods used to provide or manufacture a substrate. In some embodiments, the order of the processes can be changed or modified.

[0119] The method provides a carrier (e.g., 1100) at 1305. The carrier 1100 may include a substrate. Figure 12A Phase 1 illustrates an example of providing a carrier.

[0120] The method (at 1310) provides at least one capacitor device (e.g., 207) on a carrier. The capacitor device can be placed using a pick-and-place process. The capacitor device can be placed upright or inverted on the carrier. For example, capacitor device 207 can be placed on carrier 1100 such that the substrate 270 of capacitor device 207 contacts carrier 1100. In another example, capacitor device 207 can be placed on carrier 1100 such that the substrate 270 is positioned away from carrier 1100. Figure 12A Phase 2 is illustrated and described as an example of providing and placing at least one capacitor device on a carrier.

[0121] The method (at 1315) provides at least one inductor device (e.g., 205) on a carrier. The inductor device can be placed using a pick-and-place process. Figure 12A Phase 3 is illustrated and described as an example of providing and placing at least one inductor device on a carrier.

[0122] The method (at 1320) forms an encapsulation layer (e.g., 203) on a carrier and encapsulates (a plurality of) capacitor devices and (a plurality of) inductor devices. The encapsulation layer 203 can be formed using a compression and transfer molding process, a sheet molding process, or a liquid molding process. The encapsulation layer 203 can at least partially encapsulate at least one capacitor device 207 and at least one inductor device 205. In some embodiments, the encapsulation layer 203 can be formed on at least one capacitor device 207 and at least one inductor device 205, and portions of the encapsulation layer 203 can be removed (e.g., ground) so that the top surface of the encapsulation layer 203 is coplanar with at least one capacitor device 207 and at least one inductor device 205. The encapsulation layer 203 can include a mold, resin, and / or epoxy resin. The encapsulation layer 203 can be a component for encapsulation. The encapsulation layer 203 can be photoetchable. Figure 12B Stage 4 is illustrated and described as an example of forming an encapsulation layer.

[0123] Once the encapsulation layer 203 is formed, method 1300 can decouple the carrier (e.g., 1100) from the encapsulation layer 203, at least one capacitor device 207, and at least one inductor device. Decoupling the carrier 1100 may include using mechanical and / or chemical processes to remove, separate, grind, and / or dissolve the carrier 1100. Figure 12B Phase 5 is illustrated and described as an example of carrier decoupling.

[0124] The method (at 1325) forms interconnects (e.g., 330) in an encapsulation layer (e.g., 203). Interconnects can be formed after the encapsulation layer is formed and / or after decoupling of the carrier 1100. Forming interconnects in the encapsulation layer (e.g., 330) can include forming cavities in the encapsulation layer and filling the cavities with a conductive material. Interconnects can be formed in the encapsulation layer using plating and / or bonding processes. In some embodiments, some interconnects in the encapsulation layer can be configured to operate as inductors (e.g., 605a). Figures 12B-12C Stages 6-7 illustrate and describe examples of forming interconnects in the encapsulation layer.

[0125] The method (at 1330) forms interconnects (e.g., 1120, 1130) on and above the surface of the encapsulation layer (e.g., 203). Interconnects can be formed on a first surface and a second surface of the encapsulation layer. A plating process can be used to form the interconnects on the encapsulation layer. In some embodiments, some of the interconnects in and above the encapsulation layer can be configured to operate as inductors (e.g., 605a). Interconnects (e.g., 1120, 1130) can be coupled to interconnects in the encapsulation layer and to at least one capacitor device 207 and at least one inductor device 205. Figure 12C Stage 8 is illustrated and described as an example of forming interconnects on the surface of the encapsulation layer.

[0126] The method may (at 1335) form a dielectric layer (e.g., 204, 206) over (i) a first surface of the encapsulation layer and (ii) a second surface of the encapsulation layer. The method may also (at 1335) form additional interconnects (e.g., 1142, 1162) in and over the dielectric layer (e.g., 204, 206). Forming the additional interconnects may include forming cavities in the dielectric layer. Figure 12D Stages 9-11 illustrate and describe examples of forming dielectric layers and additional interconnects.

[0127] Once the substrate (e.g., 202, 402, 502, 602) is manufactured or provided, the power amplifier and at least one integrated device can be coupled to the substrate. For example, one or more reflow soldering processes can be used to couple the power amplifier and at least one integrated device via solder interconnects.

[0128] Exemplary output matching network

[0129] Figure 14 The diagram illustrates an exemplary frequency that can be filtered for use in two types of radio frequency communication. Figure 14 As shown, the first cellular communication protocol can operate in a frequency bandwidth that is narrower than the wider frequency bandwidth of the second cellular communication protocol. Figure 14In the example, the first cellular communication protocol can be a 4G communication protocol, and the second cellular communication protocol can be a 5G communication protocol. The first cellular communication protocol can operate in a frequency bandwidth (BW) of approximately 194 MHz (e.g., 2496 MHz–2690 MHz). The second cellular communication protocol can operate in a frequency bandwidth of approximately 600 MHz (e.g., 4400 MHz–5000 MHz). Figure 14 As shown, this means that a wireless device configured to operate using the second cellular communication protocol has three times more frequencies to consider than the first cellular communication protocol. Figure 14 As shown in the figure, filters (such as narrowband filters and wideband filters) need to be designed to properly handle the increased frequency bandwidth of 5G frequencies.

[0130] As mentioned above, the power amplifier is coupled to the antenna. In order to transfer as much power as possible between the power amplifier and the antenna, the impedance of the power amplifier must be matched as closely as possible to the impedance of the antenna. A matching network (e.g., an output matching network) can be used to ensure that the impedance of the power amplifier is closely matched to the impedance of the antenna, and vice versa.

[0131] Figure 15 The diagram 1500 illustrates a concept diagram including a power amplifier 1510, a matching network 1520, and an antenna 1530. The power amplifier 1510 is configured to be electrically coupled to the antenna 1530 via the matching network 1520. The matching network 1520 may be an output matching network. Figure 15 As shown, the power amplifier 1510, configured to operate a 5G communication protocol, can have an impedance of less than 10 ohms, while the antenna can have an impedance of 50 ohms. To bridge this impedance difference, a matching network 1520 is used. The matching network 1520 may include at least one capacitor and at least one inductor.

[0132] Figure 16 The circuit diagram of three matching networks (first matching network 1610, second matching network 1620 and third matching network 1630) is shown. Figure 16 The matching network shown can be implemented in matching network 1520 and / or any substrate described in this disclosure. The matching network can be defined by one or more combinations of capacitors and inductors.

[0133] The first matching network 1610 includes a first inductor 1611 and a first capacitor 1612. The first inductor 1611 may be configured to be electrically coupled to the first capacitor 1612. The first capacitor 1612 may be configured to be coupled to ground. The first inductor 1611 may be any of the inductors (e.g., 605a) and / or inductor devices (e.g., 205a) described in this disclosure. The first capacitor 1612 may be any of the capacitor devices (e.g., 207a) and / or capacitors (e.g., 271) described in this disclosure. The first matching network 1610 may be a first-order matching network.

[0134] The second matching network 1620 includes a first inductor 1611, a first capacitor 1612, a second inductor 1621, and a second capacitor 1622. The second inductor 1621 may be configured to be electrically coupled to the second capacitor 1622. The second capacitor 1622 may be configured to be coupled to ground. The second inductor 1621 may be configured to be electrically coupled to both the first inductor 1611 and the first capacitor 1612. The second inductor 1621 may be any of the inductors (e.g., 605a) and / or inductor devices (e.g., 205a) described in this disclosure. The second capacitor 1622 may be any of the capacitor devices (e.g., 207a) and / or capacitors (e.g., 271) described in this disclosure. The second matching network 1620 may be a second-order matching network.

[0135] The third matching network 1630 includes a first inductor 1611, a first capacitor 1612, a second inductor 1621, a second capacitor 1622, a third inductor 1631, and a third capacitor 1632. The third inductor 1631 may be configured to be electrically coupled to the third capacitor 1632. The third capacitor 1632 may be configured to be coupled to ground. The third inductor 1631 may be configured to be electrically coupled to the second inductor 1621 and the second capacitor 1622. The third inductor 1631 may be any of the inductors (e.g., 605a) and / or inductor devices (e.g., 205a) described in this disclosure. The third capacitor 1632 may be any of the capacitor devices (e.g., 207a) and / or capacitors (e.g., 271) described in this disclosure. The third matching network 1630 may be a third-order matching network.

[0136] Figure 17 The diagram illustrates how using different matching networks can help improve impedance matching for narrowband and wideband bandwidths. Figure 17 The illustration shows how various combinations of capacitors and inductors can help improve impedance matching across a wide frequency range. For example... Figure 17As shown, the insertion loss difference within the bandwidth (BW≈600MHz) is defined as Δ, and the value (Δ) is calculated as the difference between the maximum and minimum values ​​within the bandwidth. For a narrowband (NB) matched network, the insertion loss difference (Δ) is calculated as (0.42dB of the maximum insertion loss) minus (0.25dB of the minimum insertion loss), while for a wideband (BB) matched network, the insertion loss difference (Δ) is calculated as (0.39dB-0.34dB). Based on the calculated Δs (0.17dB for NB and 0.05dB for BB), we can see that Δ(BB) is less than Δ(NB). The matched networks described in this disclosure (such as those in at least...) Figure 16 The matching network described in [the diagram] can be used, and a lower value (Δ) is better for device performance. The attached diagram shows that for broadband applications, the BB matching network is superior to the NB matching network. The BB matching network requires more passive components (e.g., inductors and capacitors) than the NB matching network. Therefore, we may need more components to improve the matching flatness (Δ) with bandwidth. Figure 17 The illustrations show examples of why having more inductors and capacitors can be beneficial for filters. As stated above, this disclosure describes various structures and configurations that allow for the implementation of several inductors and capacitors with a small and compact form factor.

[0137] Exemplary electronic devices

[0138] Figure 18 The illustrations depict various electronic devices that can be integrated with any of the transistors, devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, intermediates, packages, and PoP stacks described above. For example, mobile phone device 1802, laptop computer device 1804, fixed-location terminal device 1806, or wearable device 1808 may include device 1800 as described herein. Device 1800 may be any of the devices and / or integrated circuit (IC) packages described herein. Figure 18 Devices 1802, 1804, 1806, and 1808 illustrated in the figure are merely exemplary. Other electronic devices may also feature device 1800, including but not limited to a group of devices (e.g., electronic devices) comprising: mobile devices, handheld personal communication system (PCS) units, portable data units such as personal digital assistants, devices supporting Global Positioning System (GPS), navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units such as watch readers, communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), or any other device or any combination thereof that stores or retrieves data or computer instructions.

[0139] exist Figures 2-8 , Figures 9A-9D , Figures 10A-10B , Figures 11A-11C , Figures 12A-12D and Figures 13-18 One or more of the components, processes, features, and / or functions illustrated in the diagram may be rearranged and / or combined into a single component, process, feature, or function, or embodied in several components, processes, or functions. Additional elements, components, processes, and / or functions may be added without departing from this disclosure. It should also be noted that... Figures 2-8 , Figures 9A-9D , Figures 10A-10B , Figures 11A-11C , Figures 12A-12D and Figures 13-18 The corresponding descriptions herein are not limited to dies and / or ICs. In some embodiments, Figures 2-8 , Figures 9A-9D , Figures 10A-10B , Figures 11A-11C , Figures 12A-12D and Figures 13-18 The descriptions and their corresponding information can be used to manufacture, create, provide, and / or produce devices and / or integrated devices. In some embodiments, a device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a stacked package (PoP) device, and / or a middleware.

[0140] Note that the accompanying drawings in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some cases, these drawings may not be drawn to scale. In some cases, not all components and / or parts may be shown for clarity. In some cases, the position, orientation, size, and / or shape of the various parts and / or components in the drawings may be exemplary. In some embodiments, the various components and / or parts in the drawings may be optional.

[0141] The term “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation or aspect described herein as “exemplary” is not necessarily to be construed as superior to or advantageous to other aspects of this disclosure. Similarly, the term “aspect” does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed. The term “coupling” is used herein to refer to direct or indirect coupling between two objects (e.g., mechanical coupling). For example, if object A is in physical contact with object B, and object B is in contact with object C, then objects A and C can still be considered coupled to each other—even if they are not in direct physical contact. The term “electrical coupling” can mean that two objects are directly or indirectly coupled together so that current (e.g., signal, power, ground) can propagate between the two objects. Electrically coupled objects may or may not have current propagating between them. Electromagnetic coupling can mean that a signal from one circuit and / or component affects a signal from another circuit and / or component. Electromagnetic coupling can cause crosstalk. Electromagnetic coupling can be a form of signal coupling. The use of the terms “first,” “second,” “third,” and “fourth” (and / or anything greater than fourth) is arbitrary. Any component described may be a first component, a second component, a third component, or a fourth component. For example, a component referred to as the second component may be a first component, a second component, a third component, or a fourth component. The terms “top” and “bottom” are arbitrary. A component located at the top may be located on top of a component located at the bottom. A top component may be considered a bottom component, and vice versa. The term “enclose” means that an object may partially enclose or completely enclose another object. The term “around” means that an object may partially surround or completely surround another object. Further note that the term “above” as used in the context of one component being above another component in this application may be used to mean a component on and / or in another component (e.g., on the surface of the component or embedded in the component). Thus, for example, a first component above a second component may mean (1) the first component is above the second component but does not directly contact the second component, (2) the first component is on the second component (e.g., on the surface of the second component), and / or (3) the first component is in (e.g., embedded in) the second component. As used in this disclosure, the terms "about 'X value'" or "approximately X value" mean within 10% of 'X value'. For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9 to 1.1.

[0142] In some embodiments, an interconnect is a device or package element or component that allows or facilitates an electrical connection between two points, elements, and / or assemblies. In some embodiments, an interconnect may include traces, vias, pads, pillars, redistributed metal layers, and / or under-bump metallization (UBM) layers / interconnects. In some embodiments, an interconnect may include a conductive material configured to provide an electrical path for signals (e.g., data signals), ground, and / or power. An interconnect may be part of a circuit. An interconnect may include more than one element or component. An interconnect may be defined by one or more interconnects. Different embodiments may use different processes and / or sequences to form interconnects. In some embodiments, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, spraying, and / or plating processes may be used to form interconnects.

[0143] Furthermore, it should be noted that the various disclosures contained herein can be described as processes, depicted as flowcharts, diagrams, structural diagrams, or block diagrams. Although flowcharts can describe operations as sequential processes, many operations can be performed in parallel or simultaneously. Moreover, the order of operations can be rearranged. A process terminates when its operations are completed.

[0144] The various features of this disclosure described herein can be implemented in different systems without departing from this disclosure. It should be noted that the foregoing aspects of this disclosure are merely illustrative and should not be construed as limiting the scope of this disclosure. The descriptions of various aspects of this disclosure are intended to be illustrative and not to limit the scope of the claims. Therefore, this teaching can be readily applied to other types of devices, and many alternatives, modifications, and variations will be apparent to those skilled in the art.

Claims

1. A substrate, comprising: Encapsulation layer; A capacitor device is located within the encapsulation layer, wherein the capacitor device comprises: Capacitor substrate; First capacitor metal layer; An insulating layer is coupled to the first capacitor metal layer; A second capacitor metal layer is coupled to the insulating layer such that the insulating layer is located between the first capacitor metal layer and the second capacitor metal layer; and At least one dielectric layer of a capacitor device; Inductor, located within the encapsulation layer; At least one first dielectric layer is coupled to a first surface of the encapsulation layer; and Multiple first interconnects are coupled to the first surface of the encapsulation layer. The plurality of first interconnects are located at least in the at least one first dielectric layer, and The plurality of first interconnects are coupled to the capacitor device and the inductor.

2. The substrate according to claim 1, further comprising: At least one second dielectric layer is coupled to the second surface of the encapsulation layer; as well as A plurality of second interconnects are coupled to the second surface of the encapsulation layer, wherein the plurality of second interconnects are located at least in the at least one second dielectric layer.

3. The substrate according to claim 2, further comprising a plurality of via interconnects located in the encapsulation layer.

4. The substrate of claim 3, wherein the inductor is defined by interconnects from the plurality of via interconnects, the plurality of first interconnects, and the plurality of second interconnects.

5. The substrate of claim 1, wherein the inductor comprises an inductor device, the inductor device comprising: Inductor core layer; Multiple vias are interconnected, passing through the inductor core layer; Multiple interconnects are coupled to the multiple via interconnects; as well as At least one dielectric layer is coupled to the inductor core layer.

6. The substrate of claim 1, wherein the at least one capacitor device dielectric layer of the capacitor device is different from the encapsulation layer of the substrate.

7. The substrate according to claim 1, The inductor and capacitor are configured to be electrically coupled together to operate as elements of the matching network of a power amplifier. The capacitor device is configured to be coupled to ground.

8. The substrate of claim 7, wherein the inductor is an inductor device.

9. The substrate according to claim 1, further comprising: A second capacitor device is located within the encapsulation layer; as well as The second inductor is located within the encapsulation layer. The inductor, the capacitor, the second inductor, and the second capacitor are configured to be electrically coupled together to operate as elements of the matching network of a power amplifier. The capacitor device and the second capacitor device are configured to be coupled to ground.

10. The substrate according to claim 9, wherein the inductor and / or the second inductor are both inductor devices.

11. The substrate according to claim 9, further comprising: A third capacitor device is located within the encapsulation layer; as well as The third inductor is located within the encapsulation layer. The inductor, capacitor, second inductor, second capacitor, third inductor, and third capacitor are configured to be electrically coupled together to operate as elements of the matching network of a power amplifier. The capacitor device, the second capacitor device, and the third capacitor device are configured to be coupled to ground.

12. The substrate of claim 1, wherein the substrate is included in a device selected from the group consisting of: entertainment units, navigation devices, mobile devices, fixed-location terminals, computers, Internet of Things (IoT) devices, and devices in motor vehicles.

13. A package comprising: Power amplifier; as well as A substrate, coupled to the power amplifier, wherein the substrate comprises: Encapsulation layer; A capacitor device is located within the encapsulation layer, wherein the capacitor device comprises: Capacitor substrate; First capacitor metal layer; An insulating layer is coupled to the first capacitor metal layer; A second capacitor metal layer is coupled to the insulating layer such that the insulating layer is located between the first capacitor metal layer and the second capacitor metal layer; and At least one dielectric layer of a capacitor device; Inductor, located within the encapsulation layer; At least one first dielectric layer is coupled to a first surface of the encapsulation layer; and Multiple first interconnects are coupled to the first surface of the encapsulation layer. The plurality of first interconnects are located at least in the at least one first dielectric layer. The plurality of first interconnects are coupled to the capacitor device and the inductor. The inductor and capacitor are configured to be electrically coupled together to operate as elements of the matching network of the power amplifier. The capacitor device is configured to be coupled to ground.

14. The package of claim 13, wherein the substrate further comprises: At least one second dielectric layer is coupled to the second surface of the encapsulation layer; as well as A plurality of second interconnects are coupled to the second surface of the encapsulation layer, wherein the plurality of second interconnects are located at least in the at least one second dielectric layer.

15. The package of claim 14, wherein the substrate further comprises a plurality of via interconnects located in the encapsulation layer.

16. The package of claim 15, wherein the inductor is defined by interconnects from the plurality of via interconnects, the plurality of first interconnects, and the plurality of second interconnects.

17. The package of claim 13, wherein the inductor comprises an inductor device, the inductor device comprising: Inductor core layer; Multiple vias are interconnected, passing through the inductor core layer; Multiple interconnects are coupled to the multiple via interconnects; as well as At least one dielectric layer is coupled to the inductor core layer.

18. The package of claim 13, wherein the capacitor device comprises: Multiple interconnects are coupled to the second capacitor metal layer. The capacitor device dielectric layer of the capacitor device is different from the encapsulation layer of the substrate, and The dielectric layer of the at least one capacitor device surrounds the first capacitor metal layer, the insulating layer, and the second capacitor metal layer.

19. The package of claim 13, wherein the substrate further comprises: A second capacitor device is located within the encapsulation layer; as well as The second inductor is located within the encapsulation layer. The inductor, the capacitor, the second inductor, and the second capacitor are configured to be electrically coupled together to operate as elements of the matching network of the power amplifier. The capacitor device and the second capacitor device are configured to be coupled to ground.

20. The package of claim 19, wherein the inductor and / or the second inductor are both inductor devices.

21. An apparatus comprising: Components used for encapsulation; A component for a capacitor is located within the component for encapsulation, wherein the component for a capacitor includes: Capacitor substrate; First capacitor metal layer; An insulating layer is coupled to the first capacitor metal layer; A second capacitor metal layer is coupled to the insulating layer such that the insulating layer is located between the first capacitor metal layer and the second capacitor metal layer; and At least one dielectric layer of a capacitor device; The components for inductors are located within the components for encapsulation; At least one first dielectric layer is coupled to a first surface of the component used for encapsulation; and Multiple first interconnects are coupled to the first surface of the component used for encapsulation. The plurality of first interconnects are located at least in the at least one first dielectric layer, and The plurality of first interconnects are coupled to the components for capacitors and the components for inductors.

22. The apparatus of claim 21, further comprising: At least one second dielectric layer is coupled to the second surface of the component used for encapsulation; as well as A plurality of second interconnects are coupled to the second surface of the component for encapsulation, wherein the plurality of second interconnects are located at least in the at least one second dielectric layer.

23. The apparatus of claim 22, further comprising a plurality of interconnected vias located in the encapsulation component.

24. The apparatus of claim 23, wherein the component for inductance is defined by interconnects from the plurality of via interconnects, the plurality of first interconnects, and the plurality of second interconnects.

25. The apparatus of claim 21, wherein the component for the inductor comprises: Inductor core layer; Multiple vias are interconnected, passing through the inductor core layer; Multiple interconnects are coupled to the multiple via interconnects; as well as At least one dielectric layer is coupled to the inductor core layer.

26. The apparatus of claim 21, wherein the dielectric layer of the at least one capacitor device of the component for capacitance is different from the encapsulation component of the substrate.

27. The apparatus according to claim 21, The components for inductors and components for capacitors are configured to be electrically coupled together to operate as elements of a matching network for power amplification components. The component for the capacitor is configured to be coupled to ground.

28. The apparatus of claim 21, further comprising: The component for the second capacitor is located within the component for encapsulation; as well as The component for the second inductor is located within the component for encapsulation. The components for the inductor, the components for the capacitor, the components for the second inductor, and the components for the second capacitor are configured to be electrically coupled together to operate as elements of a matching network for a power amplification component. The components for the capacitor and the components for the second capacitor are configured to be coupled to ground.

29. A method for manufacturing a substrate, comprising: Provide at least one capacitor device, wherein the at least one capacitor device comprises: Capacitor substrate; First capacitor metal layer; An insulating layer is coupled to the first capacitor metal layer; A second capacitor metal layer is coupled to the insulating layer such that the insulating layer is located between the first capacitor metal layer and the second capacitor metal layer; and At least one dielectric layer of a capacitor device; Provide at least one inductor device; An encapsulation layer is formed to encapsulate the at least one capacitor device and the at least one inductor device; At least one first dielectric layer is formed on the first surface of the encapsulation layer; and A plurality of first interconnects are formed on the first surface of the encapsulation layer. The plurality of first interconnects are located at least in the at least one first dielectric layer, and The plurality of first interconnects are coupled to the capacitor device and the inductor device.

30. The method of claim 29, further comprising: At least one second dielectric layer is formed on the second surface of the encapsulation layer; as well as A plurality of second interconnects are formed on the second surface of the encapsulation layer, wherein the plurality of second interconnects are located at least in the at least one second dielectric layer.

31. The method of claim 30, further comprising forming a plurality of interconnected vias in the encapsulation layer.

32. The method of claim 31, wherein forming the plurality of via interconnects comprises: An inductor is formed in the encapsulation layer.

33. The method of claim 29, wherein the inductor device comprises: Inductor core layer; Multiple vias are interconnected, passing through the inductor core layer; Multiple interconnects are coupled to the multiple via interconnects; as well as At least one dielectric layer is coupled to the inductor core layer.

34. The method of claim 29, wherein the at least one capacitor device dielectric layer of the capacitor device is different from the encapsulation layer of the substrate.

35. The method according to claim 29, The inductor and capacitor are configured to be electrically coupled together to operate as elements of the matching network of a power amplifier. The capacitor device is configured to be coupled to ground.

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