A semiconductor open / short circuit tester

Abstract

This invention discloses a semiconductor open / short circuit tester. The invention utilizes two multiplexers. One multiplexer's multiplexing terminal is connected to the Force signal of a parameter measurement unit channel, and the other multiplexer's multiplexing terminal is connected to the Sense signal of the same channel. The multiplexing terminals of the two multiplexers are connected sequentially to the corresponding test channels. The two multiplexers can be controlled independently or used in pairs. When controlled independently, each multiplexer can select different test channels. When used in pairs, both multiplexers simultaneously select the same test channel, effectively short-circuiting the Force and Sense signals of the selected channel. This enables remote SENSE, compensating for errors caused by cable and line voltage drops, resulting in more accurate voltage output and measurement. This improves the performance of the tester when test channel resources are plentiful and high voltage measurement accuracy is required.

Description

Technical Field

[0001] This invention relates to the field of semiconductor testing technology, and in particular to a semiconductor open / short circuit tester. Background Technology

[0002] As foundries handling the packaging and testing stages of chip manufacturing, semiconductor packaging and testing companies are typically responsible for the yield of the bonding process. Defects in the bonding process can be detected through open-circuit and short-circuit testing of the chip. Although full functional verification of the chip already includes open-circuit and short-circuit testing, semiconductor packaging and testing companies still prefer to perform relatively independent open-circuit and short-circuit tests in advance to optimize efficiency and distinguish responsibility through pre-screening.

[0003] Existing open / short circuit test principles, such as Figure 1 As shown, most functional pins of conventional semiconductor chips have electrostatic discharge (ESD) protection mechanisms, meaning each functional pin is connected to the chip's power supply pin and ground pin via a diode. Referring to Figure (a), if the test circuit is connected to a functional pin and ground pin, a forced current is applied, and the voltage of this functional pin is measured, a voltage of -0.7V will be measured under normal circumstances. Referring to Figure (b), if the test circuit is connected to a functional pin and power supply pin, a forced current is applied, and the voltage of this functional pin is measured, a voltage of +0.7V will be measured under normal circumstances. By performing the same test on all functional pins of the chip, the specific test results can be used to analyze whether there are any abnormal open circuits or short circuits inside the tested chip.

[0004] These diodes are part of the internal wafer circuitry of the chip and generally have a very low failure rate. The wire connections from the chip pins to the wafer circuitry's terminals are a result of the bonding process and are also a major source of failure. Therefore, open-circuit and short-circuit tests can be used to determine the yield rate of the bonding process.

[0005] The open / short circuit tester should provide multiple wiring channels to connect all pins of the chip under test (including function pins, power supply and ground pins), and the provided test circuit should be able to perform forced current sinking and current sourcing through these wiring channels, while also being able to test the voltage on the wiring channels.

[0006] Open-circuit and short-circuit testing of chips is relatively simple, but using general-purpose automated test machines specifically for this purpose is uneconomical. Packaging and testing companies require efficient and cost-effective dedicated open-circuit and short-circuit testing solutions. Therefore, designing a high-capacity, highly parallel, and low-cost open-circuit and short-circuit tester is a current market necessity. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to provide a high-capacity, high-parallelism, and low-cost semiconductor open-circuit and short-circuit tester.

[0008] To address the above problems, the present invention provides a semiconductor open / short circuit tester, comprising:

[0009] Main control backplane, wherein the main control backplane is provided with multiple card slots; and,

[0010] Multiple cards are inserted into the card slots, and each card includes a driver module and multiple switch array modules.

[0011] The drive module is equipped with multiple parameter measurement unit channels. Each parameter measurement unit channel is connected to a switch array module. Each switch array module is equipped with multiple test channels. Each switch array module includes two multiplexers and multiple single-pole single-throw analog switches. The multiplexing terminal of one multiplexer is connected to the Force signal of the parameter measurement unit channel, and the multiplexing terminal of the other multiplexer is connected to the Sense signal of the parameter measurement unit channel. The multiplexing terminals of the two multiplexers are connected sequentially and then connected to the corresponding test channels. One end of each single-pole single-throw analog switch is connected to the corresponding test channel, and the other end is grounded.

[0012] In one embodiment of the present invention, each driving module includes a multi-channel PMU chip and a multi-channel ADC chip, wherein the multi-channel PMU chip and the multi-channel ADC chip cooperate to form multiple parameter measurement units.

[0013] In one embodiment of the present invention, the control signals for each card slot include: one SPI bus for connecting the multi-channel PMU chip; one SPI bus for connecting the multi-channel ADC chip; multiple IIC buses for connecting multiple switch array modules respectively; multiple GO-NoGO comparator output signals, corresponding to the GO-NoGO results of the four parameter measurement unit channels respectively; and four closed-loop detection output lines.

[0014] In one embodiment of the present invention, each switch array module has 64 test channels, which are led out through 68-pin ribbon cables; the 64 ribbon cables connect the 64 test channels; 2 ribbon cables are closed-loop detection lines, including 1 closed-loop detection output line and 1 closed-loop detection input line; 1 ribbon cable is connected to the ground network of the switch array module, denoted as "power ground"; 1 ribbon cable passes through the switch array module and is connected to the drive module, denoted as "detection ground".

[0015] In one embodiment of the present invention, the "detection ground" is referred to as "remote detection ground" in the driving mode; the ground network of each switch array module outputs an independent signal to the driving module, which is referred to as "near-end detection ground" in the driving module. The driving module is provided with multiple single-pole double-throw switches. The fixed end of each single-pole double-throw switch is connected to the "remote detection ground" and "near-end detection ground" of a switch array module. By switching the active end of each single-pole double-throw switch, the "remote detection ground" or "near-end detection ground" is selected for each parameter measurement unit.

[0016] In one embodiment of the present invention, the testing machine is equipped with a detection logic for whether two closed-loop detection lines are short-circuited. By short-circuiting the two closed-loop detection lines on the test carrier board at the user end, the connection of the 68 ribbon cables is detected as normal and effective.

[0017] In one embodiment of the present invention, the 68 ribbon cables are specifically defined as follows: the first ribbon cable is a closed-loop detection output line, the second to the 65th ribbon cables are test channels 0 to 63, the 66th ribbon cable is a "power ground", the 67th ribbon cable is a closed-loop detection input line, and the 68th ribbon cable is a "detection ground"; or, the 68th ribbon cable is a closed-loop detection output line, the 67th to the 4th ribbon cables are test channels 0 to 63, the 3rd ribbon cable is a "power ground", the 2nd ribbon cable is a closed-loop detection input line, and the 1st ribbon cable is a "detection ground".

[0018] In one embodiment of the present invention, the switch array module uses a GPIO expansion chip to connect the control signals of the multiplexer and the single-pole single-throw analog switch, and the control terminal of each switch array module controls the GPIO expansion chip through a set of IIC interface buses.

[0019] In one embodiment of the present invention, the main control backplane is provided with an FPGA main control chip, the FPGA main control chip processes all hardware-level control logic, the FPGA main control chip uses independent IO pins to connect to the main control signals of multiple card slots respectively, the FPGA main control chip is connected to a computer system, and the computer system processes all software-level control logic.

[0020] In one embodiment of the present invention, the main control backplane is provided with 8 card slots, each card includes 1 driver module and 4 switch array modules, each driver module is provided with 4 parameter measurement unit channels, each switch array module is provided with 64 test channels, and the multiplexer is a 1:64 multiplexer, or an equivalent circuit of a 1:64 multiplexer.

[0021] The beneficial effects of this invention are:

[0022] The semiconductor open / short circuit tester of this invention uses two multiplexers. The multiplexing terminal of one multiplexer is connected to the Force signal of the parameter measurement unit channel, and the multiplexing terminal of the other multiplexer is connected to the Sense signal of the parameter measurement unit channel. The multiplexing terminals of the two multiplexers are connected sequentially to the corresponding test channels. The two multiplexers can be controlled independently or used in pairs.

[0023] When used independently, the two multiplexers can each select different test channels. When used in pairs, both multiplexers simultaneously select the same test channel. This is equivalent to short-circuiting the Force and Sense pins of the selected test channel, effectively treating the two test channels as a single test channel. This allows for remote Sensing, compensating for errors caused by cable and line voltage drops, and achieving more accurate voltage output and measurement. When test channel resources are plentiful and users have high requirements for voltage measurement accuracy, this can be used to improve the performance of the testing equipment.

[0024] Meanwhile, the semiconductor open / short circuit tester of the present invention has the advantages of large capacity, high parallelism, and low cost.

[0025] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0026] Figure 1 This is the schematic diagram for open / short circuit testing;

[0027] Figure 2 This is a schematic diagram of the overall structure of the semiconductor open / short circuit tester in an embodiment of the present invention;

[0028] Figure 3 This is a schematic diagram of the card insertion structure in an embodiment of the present invention;

[0029] Figure 4 This is a schematic diagram of the connection structure of a multi-channel PMU chip and multiple switch array modules in an embodiment of the present invention.

[0030] Marker explanation:

[0031] 1. Card slot; 2. Driver module; 3. Switch array module; 4. Single-pole single-throw analog switch; 5. Multiplexer; 6. Single-pole double-throw analog switch. Detailed Implementation

[0032] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, so that those skilled in the art can better understand and implement the present invention. However, the embodiments described are not intended to limit the present invention.

[0033] like Figure 2-4 As shown, this embodiment discloses a semiconductor open / short circuit tester, comprising:

[0034] The main control backplane and multiple plug-in cards are provided. The main control backplane has multiple plug-in card slots 1, and multiple plug-in cards are plugged into the plug-in card slots 1 one by one. The plug-in cards include a driver module 2 and multiple switch array modules 3.

[0035] The drive module 2 is equipped with multiple parameter measurement unit channels. Each parameter measurement unit channel is connected to a switch array module 3. Each switch array module 3 is equipped with multiple test channels. Each switch array module 3 includes two multiplexers 5 and multiple single-pole single-throw analog switches 4. The multiplexing terminal of one multiplexer 5 is connected to the Force signal of the parameter measurement unit channel, and the multiplexing terminal of the other multiplexer 5 is connected to the Sense signal of the parameter measurement unit channel. The multiplexing terminals of the two multiplexers 5 are connected one by one in sequence and then connected to the corresponding test channel. One end of each single-pole single-throw analog switch 4 is connected to the corresponding test channel, and the other end is grounded.

[0036] The semiconductor open / short circuit tester of the present invention uses two multiplexers 5. The multiplexing terminal of one multiplexer 5 is connected to the Force signal of the parameter measurement unit channel, and the multiplexing terminal of the other multiplexer is connected to the Sense signal of the parameter measurement unit channel. The multiplexing terminals of the two multiplexers 5 are connected one by one in sequence and then connected to the corresponding test channel. The two multiplexers 5 can be controlled independently or used in pairs.

[0037] When used independently, the two multiplexers can each select different test channels. When used in pairs, both multiplexers simultaneously select the same test channel. This is equivalent to short-circuiting the Force and Sense pins of the selected test channel, effectively treating the two test channels as a single test channel. This allows for remote Sensing, compensating for errors caused by cable and line voltage drops, and achieving more accurate voltage output and measurement. When test channel resources are plentiful and users have high requirements for voltage measurement accuracy, this can be used to improve the performance of the testing equipment.

[0038] In one embodiment, the main control backplane has eight card slots 1. Each card includes one driver module 2 and four switch array modules 3. Each driver module has four parameter measurement unit channels, and each switch array module 3 has 64 test channels. Each test channel can be connected to a parameter measurement unit, and each test channel can be individually shorted to the ground network. The multiplexer 5 is a 1:64 multiplexer, or an equivalent circuit of a 1:64 multiplexer. Each switch array module includes 64 single-pole single-throw analog switches 4.

[0039] Reference Figure 2 In one embodiment, each drive module 2 includes a multi-channel PMU chip and a multi-channel ADC chip, which work together to form multiple parameter measurement units. Furthermore, both the multi-channel PMU chip and the multi-channel ADC chip have 4 channels, and the main functions of the parameter measurement units include constant voltage output, constant current output, voltage measurement, current measurement, and a GO-NoGO comparator.

[0040] The numerous analog switches on the switch array module 3 require a large number of control signals. Optionally, GPIO expansion chips can be used on the switch array module 3 to connect the control signals of the multiplexer 5 and the single-pole single-throw analog switch 4. The control terminal of each switch array module 3 controls the GPIO expansion chip through a set of IIC interface buses.

[0041] In one embodiment, an FPGA main control chip is provided on the main control backplane. The FPGA main control chip handles all hardware-level control logic and is connected to a computer system, which handles all software-level control logic. The FPGA main control chip uses independent I / O pins to connect to the main control signals of the eight card slots 1. Since the eight cards do not share signal lines, they can operate independently and in parallel. Because each card has four PMU channels and four switch arrays, each can operate independently, a single test machine can have 32 test channels operating in parallel simultaneously.

[0042] The control signals for each card slot 1 include: one SPI bus for connecting to a multi-channel PMU chip; one SPI bus for connecting to a multi-channel ADC chip; multiple IIC buses connecting to multiple switch array modules 3; multiple GO-NoGO comparator output signals, corresponding to the GO-NoGO results of the four parameter measurement unit channels; and four closed-loop detection output lines. These signals are all single-ended, 3.3V-LVCMOS level, without high-speed or differential signals, thus simplifying the design and reducing production costs.

[0043] In one embodiment, each switch array module 3 has 64 test channels, which are led out through 68-pin ribbon cables; the 64 ribbon cables connect the 64 test channels; 2 ribbon cables are closed-loop detection lines, including 1 closed-loop detection output line and 1 closed-loop detection input line; 1 ribbon cable is connected to the ground network of the switch array module 3, denoted as "power ground"; 1 ribbon cable passes through the switch array module 3 and is connected to the drive module 2, denoted as "detection ground".

[0044] Reference Figure 4 In this context, the "detection ground" is denoted as "remote detection ground" on the drive module; each switch array module 3's ground network outputs an independent signal to the drive module 2, which is denoted as "near-end detection ground" in the drive mode. The drive module 2 is equipped with four single-pole double-throw switches 6. The fixed end of each single-pole double-throw switch 6 is connected to the "remote detection ground" and "near-end detection ground" of a switch array module 3. By switching the active end of each single-pole double-throw switch 6, the "remote detection ground" or "near-end detection ground" can be selected for each parameter measurement unit.

[0045] The testing machine is equipped with a detection logic to check whether two closed-loop detection lines are short-circuited. By short-circuiting the two closed-loop detection lines on the test carrier board at the user end, the connection of the 68 ribbon cables can be checked to see if it is normal and effective.

[0046] Optionally, the 68 ribbon cables are specifically defined as follows: the first ribbon cable is the closed-loop detection output line, the second to the 65th ribbon cables are test channels 0 to 63, the 66th ribbon cable is "power ground", the 67th ribbon cable is the closed-loop detection input line, and the 68th ribbon cable is "detection ground"; or, the 68th ribbon cable is the closed-loop detection output line, the 67th to the 4th ribbon cables are test channels 0 to 63, the 3rd ribbon cable is "power ground", the 2nd ribbon cable is the closed-loop detection input line, and the 1st ribbon cable is "detection ground".

[0047] The closed-loop detection output line is connected to the I / O pins of the FPGA main control chip inside the test machine. Since each card has four sets of closed-loop detection lines, the FPGA main control chip has four I / O signals connected to the user's test carriage board for each card. These signal lines can be used through FPGA programming to implement control logic on the carriage board, including user-customized functions.

[0048] In addition, by using the closed-loop detection output line and programming the FPGA, IIC bus control can be implemented to read information from the IIC chip on the test carrier board.

[0049] The semiconductor open / short circuit tester of this invention has the advantages of large capacity, high parallelism, and low cost.

[0050] The above embodiments are merely preferred embodiments provided to fully illustrate the present invention, and the scope of protection of the present invention is not limited thereto. Equivalent substitutions or modifications made by those skilled in the art based on the present invention are all within the scope of protection of the present invention. The scope of protection of the present invention is defined by the claims.

Claims

1. A semiconductor open circuit tester characterized by comprising: The application relates to a main control backboard and a plurality of plug-in cards. The main control backboard is provided with a plurality of plug-in card slots; and the plurality of plug-in cards are plugged into the plug-in card slots one by one, and the plug-in cards comprise driving modules and a plurality of switch array modules. The driving module is provided with a plurality of parameter measurement unit channels, each parameter measurement unit channel is connected with one switch array module, each switch array module is provided with a plurality of test channels, each switch array module comprises two multiplexers and a plurality of single-pole single-throw analog switches, the multiplexing end of one multiplexer is connected with a Force signal of the parameter measurement unit channel, the multiplexing end of the other multiplexer is connected with a Sense signal of the parameter measurement unit channel, the multiplexing ends of the two multiplexers are connected to corresponding test channels in sequence, and the two multiplexers can be independently controlled or used in pairs; when being independently controlled, the two multiplexers select different test channels respectively; when being used in pairs, the two multiplexers select the same test channel simultaneously; one end of each single-pole single-throw analog switch is connected with a corresponding test channel, and the other end is grounded; Each driving module comprises a multi-channel PMU chip and a multi-channel ADC chip, and the multi-channel PMU chip and the multi-channel ADC chip cooperate to form a plurality of parameter measurement units; The control signals of each plug-in card slot comprise: one group of SPI buses used for connecting the multi-channel PMU chip; one group of SPI buses used for connecting the multi-channel ADC chip; and a plurality of IIC buses respectively connected with the plurality of switch array modules; A plurality of GO-NoGO comparator output signals correspond to GO-NoGO results of four parameter measurement unit channels respectively; and four closed-loop detection output lines; Each switch array module is provided with 64 test channels and is led out through a 68-core flat cable; 64 flat cables are connected with the 64 test channels; two flat cables are closed-loop detection lines, comprising one closed-loop detection output line and one closed-loop detection input line; one flat cable is connected to a ground wire network of the switch array module and is recorded as a power supply ground; and one flat cable is connected to the driving module after penetrating through the switch array module and is recorded as a detection ground; The switch array module uses a GPIO expansion chip to connect the control signals of the multiplexers and the single-pole single-throw analog switches, and the control end of each switch array module controls the GPIO expansion chip through one group of IIC interface buses; The main control backboard is provided with an FPGA main control chip, the FPGA main control chip processes all control logics in a hardware layer, the FPGA main control chip is connected with a plurality of plug-in card slot control signals through independent IO pins, the FPGA main control chip is connected with a computer system, and the computer system processes all control logics in a software layer. ​ 2. A semiconductor open circuit tester as claimed in claim 1, wherein The detection ground is recorded as a far-end detection ground on the drive module; one independent signal is connected to the drive module from the ground network of each switch array module, and the signal is recorded as a near-end detection ground on the drive module; the drive module is provided with a plurality of single-pole double-throw switches; the fixed end of each single-pole double-throw switch is connected to the far-end detection ground and the near-end detection ground of one switch array module; and the active end of each single-pole double-throw switch is switched to select the far-end detection ground or the near-end detection ground for each parameter measurement unit.

3. A semiconductor open circuit tester as claimed in claim 1, wherein The tester is internally provided with two closed-loop detection lines for detecting whether the two closed-loop detection lines are short-circuited, and the two closed-loop detection lines are short-circuited on a test carrier plate at a user end to detect whether 68 row lines are normally and effectively connected.

4. A semiconductor open circuit tester as defined in claim 1, wherein Specific definitions of the 68 row lines are as follows: the first row line is a closed-loop detection output line, the second to 65th row lines are test channels 0 to 63, the 66th row line is a power ground, the 67th row line is a closed-loop detection input line, and the 68th row line is a detection ground; or the 68th row line is a closed-loop detection output line, the 67th to fourth row lines are test channels 0 to 63, the third row line is a power ground, the second row line is a closed-loop detection input line, and the first row line is a detection ground.

5. A semiconductor open circuit tester as defined in claim 1, wherein The main control backboard is provided with eight card slots, each card includes one drive module and four switch array modules, each drive module is provided with four parameter measurement unit channels, each switch array module is provided with 64 test channels, the multiplexer is a 1:64 multiplexer, or an equivalent circuit equivalent to the 1:64 multiplexer.

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