Control method for implementing neural network operation by NAND flash memory

Abstract

The application provides a control method for implementing neural network operation by NAND flash memory, comprising providing NAND flash memory, wherein the NAND flash memory comprises a plurality of memory blocks and a plurality of page buffers, the memory block comprises a plurality of synaptic strings, a plurality of bit lines and a plurality of word lines, the synaptic string comprises a plurality of series-connected memory cells, the synaptic string is connected to the bit line in one-to-one correspondence, the word line is connected to all the synaptic strings, the page buffer is connected to all the memory blocks, and one bit line is connected to only one page buffer, the weight data is written into the memory cell according to the relationship between the weight data and the feature data, the target voltage is applied to the memory cell through the word line, and the current of the memory block is sensed through the page buffer to obtain a convolution result, and the neural network operation is implemented by using the general NAND flash memory.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of NAND flash memory, in particular to a control method for implementing neural network operation by NAND flash memory. BACKGROUND

[0002] In the prior art, neural network operation is based on NOR memory architecture or ReRAM / PCM memory architecture, which requires specific memory array structures with different standard memory arrays and a large number of peripheral circuits to support neural network operation, resulting in high cost and unsuitable for mass production.

[0003] Therefore, it is necessary to provide a new control method for implementing neural network operation by NAND flash memory to solve the above problems in the prior art. SUMMARY

[0004] The present application aims to provide a control method for implementing neural network operation by NAND flash memory, which uses a general NAND flash memory to implement neural network operation.

[0005] To achieve the above-mentioned purpose, the control method for implementing neural network operation by NAND flash memory comprises the following steps:

[0006] S0: providing a NAND flash memory, the NAND flash memory comprising a plurality of memory blocks and a plurality of page buffers, the memory block comprising a plurality of synaptic strings, a plurality of bit lines and a plurality of word lines, the synaptic string comprising a plurality of series-connected memory cells, the synaptic string being connected one-to-one with the bit line, the word line connecting all the synaptic strings, the page buffer being connected with all the memory blocks, and one bit line being connected with only one page buffer;

[0007] S1: writing weight data into the memory cell according to the relationship between the weight data and feature data;

[0008] S2: applying a target voltage to the memory cell through the word line;

[0009] S3: sensing the current of the memory block through the page buffer to obtain a convolution result.

[0010] The control method for implementing neural network operation by NAND flash memory has the beneficial effect that the weight data is written into the memory cell according to the relationship between the weight data and feature data, a target voltage is applied to the memory cell through the word line, and the current of the memory block is sensed through the page buffer to obtain a convolution result, thus realizing neural network operation by using a general NAND flash memory.

[0011] Optionally, the feature data comprises a plurality of sub-feature data, and the weight data comprises a plurality of sub-weight data, each of the sub-feature data corresponding to one of the memory blocks, and each of the sub-feature data corresponding to at least one of the sub-weight data.

[0012] Optionally, the writing of the weight data into the memory unit according to the relationship between the weight data and the feature data comprises:

[0013] According to the correspondence between the sub-weight data and the sub-feature data, all the sub-weight data corresponding to one of the sub-feature data are written into different memory units of the memory block corresponding to the sub-feature data, and the different memory units are connected to the same word line.

[0014] Optionally, the target voltage comprises a plurality of sub-target voltages, and each of the sub-target voltages corresponds to one of the sub-feature data, and the applying of the target voltage to the memory unit through the word line comprises:

[0015] The sub-target voltage corresponding to one of the sub-feature data is applied to all the memory units of the memory block corresponding to the sub-feature data, and is maintained through the word line.

[0016] Optionally, the convolution result comprises a plurality of sub-convolution results, and the steps S1 to S3 are repeated to implement the next layer of convolution operation by taking the plurality of sub-convolution results as new feature data.

[0017] Optionally, the sensing of the current of the memory block by the page buffer to obtain the convolution result comprises:

[0018] The sensing time of the page buffer is divided into N segments;

[0019] The pre-charge voltage of the page buffer is discharged through the bit line until the pre-charge voltage of the page buffer is less than a threshold voltage, and the time is recorded as the Mth segment.

[0020] The convolution result is obtained according to M and N, and M and N are natural numbers greater than 0.

[0021] Optionally, the control method for implementing neural network operation by the NAND flash memory further comprises a calibration step, and the calibration step comprises:

[0022] The memory unit with known weight data and feature data is taken as a reference unit, the current of the reference unit sensed by the page buffer is taken as a reference, and the sensing time of the page buffer is calibrated. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1This is a flowchart of a control method for implementing neural network operations using NAND flash memory in some embodiments of the present invention;

[0024] Figure 2 This is a schematic diagram of the feature data model in some embodiments of the present invention;

[0025] Figure 3 This is a schematic diagram of the weight data model in some embodiments of the present invention;

[0026] Figure 4 This is a schematic diagram of the structure of NAND flash memory in some embodiments of the present invention;

[0027] Figure 5 This is a circuit diagram of a page buffer in some embodiments of the present invention;

[0028] Figure 6 As shown in some embodiments of the present invention Figure 5 The timing diagram of the page buffer is shown below;

[0029] Figure 7 This is a circuit diagram of a page buffer in some other embodiments of the present invention;

[0030] Figure 8 As shown in some embodiments of the present invention Figure 7 The timing diagram of the page buffer is shown. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without inventive effort are within the scope of protection of this invention. Unless otherwise defined, the technical or scientific terms used herein should have the ordinary meaning understood by those skilled in the art. The terms "comprising" and similar expressions used herein mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, but do not exclude other elements or objects.

[0032] To address the problems existing in the prior art, embodiments of the present invention provide a control method for implementing neural network operations using NAND flash memory. (Refer to...) Figure 1 The control method for implementing neural network operations using the NAND flash memory includes the following steps:

[0033] S0: providing a NAND flash memory, the NAND flash memory comprising a plurality of memory blocks and a plurality of page buffers, each of the memory blocks comprising a plurality of synaptic strings, a plurality of bit lines and a plurality of word lines, each of the synaptic strings comprising a plurality of storage cells connected in series, each of the synaptic strings being connected to one of the bit lines one-to-one, each of the word lines connecting all of the synaptic strings, and each of the page buffers being connected to all of the memory blocks and one of the bit lines;

[0034] S1: writing weight data into the storage cells according to a relationship between the weight data and feature data;

[0035] S2: applying a target voltage to the storage cells through the word lines;

[0036] S3: sensing a current of the memory block through the page buffer to obtain a convolution result.

[0037] In some embodiments, the feature data comprises a plurality of sub-feature data, and the weight data comprises a plurality of sub-weight data, each of the sub-feature data corresponding to one of the memory blocks, and each of the sub-feature data corresponding to at least one of the sub-weight data.

[0038] In some embodiments, the step of writing the weight data into the storage cells according to the relationship between the weight data and the feature data comprises: writing all of the sub-weight data corresponding to one of the sub-feature data into different storage cells of a memory block corresponding to the sub-feature data according to a corresponding relationship between the sub-weight data and the sub-feature data, and the different storage cells being connected to the same word line. Wherein, the sub-weight data corresponding to the sub-feature data whose result needs to be accumulated are written into different synaptic strings of the storage cells connected to a bit line of a same page buffer. And a plurality of sub-weight data whose results are associated are written into the storage cells of a plurality of memory blocks sharing a plurality of bit lines.

[0039] In some embodiments, the target voltage comprises a plurality of sub-target voltages, each of the sub-target voltages corresponding to one of the sub-feature data, and the step of applying the target voltage to the storage cells through the word lines comprises: applying a sub-target voltage corresponding to one of the sub-feature data to all of the storage cells of a memory block corresponding to the sub-feature data, and maintaining through the word line.

[0040] In some embodiments, the convolution result comprises a plurality of sub-convolution results, and the steps of S1 to S3 are repeated to implement a next layer convolution operation by taking the plurality of sub-convolution results as new feature data.

[0041] Figure 2 A model diagram of feature data in some embodiments of the present application. Figure 3A model diagram of weight data in some embodiments of the present application. Referring to Figure 2 and Figure 3 A1, A2, A3, to A23, A24, A25 are all sub-feature data, and W1, W2, W3 to W7, W8, W9 are all sub-weight data.

[0042] Referring to Figure 2 and Figure 3 When performing convolution operation, it includes 9 convolution operation processes, which are respectively:

[0043] A1xW1+A2xW2+A3xW3+A6xW4+A7xW5+A8xW6+A11xW7+A12xW8+A13xW9, to obtain a first sub-convolution result B1;

[0044] A2xW1+A3xW2+A4xW3+A7xW4+A8xW5+A9xW6+A12xW7+A13xW8+A14xW9, to obtain a second sub-convolution result B2;

[0045] A3+A4+A5+A8+A9+A10+A13+A14+A15, to obtain a third sub-convolution result B3;

[0046] A6+A7+A8+A11+A12+A13+A16+A17+A18, to obtain a fourth sub-convolution result B4;

[0047] A7+A8+A9+A12+A13+A14+A17+A18+A19, to obtain a fifth sub-convolution result B5;

[0048] A8+A9+A10+A13+A14+A15+A18+A19+A20, to obtain a sixth sub-convolution result B6;

[0049] A11+A12+A13+A16+A17+A18+A21+A22+A23, to obtain a seventh sub-convolution result B7;

[0050] A12+A13+A14+A17+A18+A19+A22+A23+A24, to obtain an eighth sub-convolution result B8;

[0051] A13+A14+A15+A18+A19+A20+A23+A24+A25, to obtain a ninth sub-convolution result B9. Among them, the sub-weight data W1 corresponds to the sub-feature data A1, the sub-weight data W1 and the sub-weight data W2 correspond to the sub-feature data A2, the sub-weight data W1, the sub-weight data W2 and the sub-weight data W3 correspond to the sub-feature data A3, the sub-weight data W2 and the sub-weight data W3 correspond to the sub-feature data A4, the sub-weight data W3 corresponds to the sub-feature data A5, the sub-weight data W1 and the sub-weight data W4 correspond to the sub-feature data A6, the sub-weight data W1, the sub-weight data W2, the sub-weight data W4 and the sub-weight data W5 correspond to the sub-feature data A7, the sub-weight data W1, the sub-weight data W2, the sub-weight data W3, the sub-weight data W4, the sub-weight data W5 and the sub-weight data W6 correspond to the sub-feature data A8, the sub-weight data W2, the sub-weight data W3, the sub-weight data W5, the sub-weight data W6 correspond to the sub-feature data A6, the sub-weight data W3 and the sub-weight data W6 correspond to the sub-feature data A10, the sub-weight data W1, the sub-weight data W4 and the sub-weight data W7 correspond to the sub-feature data A11, the sub-weight data W1, the sub-weight data W2, the sub-weight data W4, the sub-weight data W5 and the sub-weight data W8 correspond to the sub-feature data A12, the sub-weight data W1, the sub-weight data W2, the sub-weight data W3, the sub-weight data W4, the sub-weight data W5, the sub-weight data W6, the sub-weight data W7, the sub-weight data W8 and the sub-weight data W9 correspond to the sub-feature data A13, the sub-weight data W2, the sub-weight data W3, the sub-weight data W5, the sub-weight data W6, the sub-weight data W8, the sub-weight data W9 correspond to the sub-feature data A14, the sub-weight data W3, the sub-weight data W6 and the sub-weight data W9 correspond to the sub-feature data A15, the sub-weight data W4, the sub-weight data W7 correspond to the sub-feature data A16, the sub-weight data W4, the sub-weight data W5, the sub-weight data W7, the sub-weight data W8 correspond to the sub-feature data A17, the sub-weight data W4, the sub-weight data W5, the sub-weight data W6, the sub-weight data W7, the sub-weight data W8 and the sub-weight data W9 correspond to the sub-feature data A18, the sub-weight data W5, the sub-weight data W6, the sub-weight data W8, the sub-weight data W9 correspond to the sub-feature data A19, the sub-weight data W6, the sub-weight data W9 correspond to the sub-feature data A20, the sub-weight data W7 corresponds to the sub-feature data A21, the sub-weight data W7 and the sub-weight data W8 correspond to the sub-feature data A22, the sub-weight data W7, the sub-weight data W8 and the sub-weight data W9 correspond to the sub-feature data A23, the sub-weight data W8 and the sub-weight data W9 correspond to the sub-feature data A24, and the sub-weight data W9 corresponds to the sub-feature data A25.

[0052] Figure 4Figure 1 is a schematic diagram of the structure of a NAND flash memory according to some embodiments of the present application. Figure 4 The NAND flash memory comprises y memory blocks and m+2 page buffers, each of the memory blocks comprises m+2 synaptic strings, m+2 bit lines, three word lines, one drain side select gate line, one source side select gate line, the synaptic string comprises a drain side select gate, a source side select gate and three memory cells, the three memory cells are a first memory cell, a second memory cell and a third memory cell respectively, the drain side select gate, the first memory cell, the second memory cell, the third memory cell and the source side select gate are connected in series, the drain side select gate in the first synaptic string is connected with the first bit line, the drain side select gate in the second synaptic string is connected with the second bit line, and so on, the drain side select gate in the m+1 synaptic string is connected with the m+1 bit line, and the drain side select gate in the m+2 synaptic string is connected with the m+2 bit line.

[0053] Figure 2 is a schematic diagram of the structure of a NAND flash memory according to some embodiments of the present application. Figure 4 The first bit line of the first memory block block1, the first bit line of the second memory block, the first bit line of the yth memory block are all connected with the first page buffer, the second bit line of the first memory block, the second bit line of the second memory block, the second bit line of the yth memory block are all connected with the second page buffer, and so on, the m+1 bit line of the first memory block, the m+1 bit line of the second memory block, the m+1 bit line of the yth memory block are all connected with the m+1 page buffer, the m+2 bit line of the first memory block, the m+2 bit line of the second memory block, the m+2 bit line of the yth memory block are all connected with the m+2 page buffer.

[0054] Figure 3 is a schematic diagram of the structure of a NAND flash memory according to some embodiments of the present application. Figure 3 and Figure 4 The sub-weight data W1 is written into the second memory cell of the first synaptic string of the first memory block block1.

[0055] Figure 4 is a schematic diagram of the structure of a NAND flash memory according to some embodiments of the present application. Figure 3 and Figure 4 The sub-weight data W2 is written into the second memory cell of the first synaptic string of the second memory block, and the sub-weight data W1 is written into the second memory cell of the second synaptic string of the second memory block.

[0056] Figure 5 is a schematic diagram of the structure of a NAND flash memory according to some embodiments of the present application. Figure 3 and Figure 4 The sub-weight data W3 is written into the second memory cell of the first synaptic string of the third memory block, the sub-weight data W2 is written into the second memory cell of the second synaptic string of the third memory block, and the sub-weight data W1 is written into the second memory cell of the third synaptic string of the third memory block.

[0057] Figure 6 is a schematic diagram of the structure of a NAND flash memory according to some embodiments of the present application. Figure 3and Figure 4 sub-weight data W3 is written into the second memory cell of the second synapse string of the fourth memory block, and sub-weight data W2 is written into the second memory cell of the third synapse string of the fourth memory block.

[0058] Referring to Figure 3 and Figure 4 sub-weight data W3 is written into the second memory cell of the third synapse string of the fifth memory block.

[0059] Referring to Figure 3 and Figure 4 sub-weight data W4 is written into the second memory cell of the first synapse string of the sixth memory block, and sub-weight data W1 is written into the second memory cell of the fourth synapse string of the sixth memory block.

[0060] Referring to Figure 3 and Figure 4 sub-weight data W5 is written into the second memory cell of the first synapse string of the seventh memory block, sub-weight data W4 is written into the second memory cell of the second synapse string of the seventh memory block, sub-weight data W2 is written into the second memory cell of the fourth synapse string of the seventh memory block, and sub-weight data W1 is written into the second memory cell of the fifth synapse string of the seventh memory block.

[0061] Referring to Figure 3 and Figure 4 sub-weight data W6 is written into the second memory cell of the first synapse string of the eighth memory block, sub-weight data W5 is written into the second memory cell of the second synapse string of the eighth memory block, sub-weight data W4 is written into the second memory cell of the third synapse string of the eighth memory block, sub-weight data W3 is written into the second memory cell of the fourth synapse string of the eighth memory block, sub-weight data W2 is written into the second memory cell of the fifth synapse string of the eighth memory block, and sub-weight data W1 is written into the second memory cell of the sixth synapse string of the eighth memory block.

[0062] Referring to Figure 3 and Figure 4 sub-weight data W6 is written into the second memory cell of the second synapse string of the ninth memory block, sub-weight data W5 is written into the second memory cell of the third synapse string of the ninth memory block, sub-weight data W3 is written into the second memory cell of the fifth synapse string of the ninth memory block, and sub-weight data W2 is written into the second memory cell of the sixth synapse string of the ninth memory block.

[0063] Referring to Figure 3 and Figure 4The sub-weight data W6 is written into the second memory cell of the third synapse string of the tenth memory block, and the sub-weight data W3 is written into the second memory cell of the sixth synapse string of the tenth memory block.

[0064] With reference to Figure 3 and Figure 4 The sub-weight data W7 is written into the second memory cell of the first synapse string of the eleventh memory block, the sub-weight data W4 is written into the second memory cell of the fourth synapse string of the eleventh memory block, and the sub-weight data W1 is written into the second memory cell of the seventh synapse string of the eleventh memory block.

[0065] With reference to Figure 3 and Figure 4 The sub-weight data W8 is written into the second memory cell of the first synapse string of the twelfth memory block, the sub-weight data W7 is written into the second memory cell of the second synapse string of the twelfth memory block, the sub-weight data W5 is written into the second memory cell of the fourth synapse string of the twelfth memory block, the sub-weight data W4 is written into the second memory cell of the fifth synapse string of the twelfth memory block, the sub-weight data W2 is written into the second memory cell of the sixth synapse string of the twelfth memory block, and the sub-weight data W1 is written into the second memory cell of the seventh synapse string of the twelfth memory block.

[0066] With reference to Figure 3 and Figure 4 The sub-weight data W9 is written into the second memory cell of the first synapse string of the thirteenth memory block, the sub-weight data W8 is written into the second memory cell of the second synapse string of the thirteenth memory block, the sub-weight data W7 is written into the second memory cell of the third synapse string of the thirteenth memory block, the sub-weight data W6 is written into the second memory cell of the fourth synapse string of the thirteenth memory block, the sub-weight data W5 is written into the second memory cell of the fifth synapse string of the thirteenth memory block, the sub-weight data W4 is written into the second memory cell of the sixth synapse string of the thirteenth memory block, the sub-weight data W3 is written into the second memory cell of the seventh synapse string of the thirteenth memory block, the sub-weight data W2 is written into the second memory cell of the eighth synapse string of the thirteenth memory block, and the sub-weight data W1 is written into the second memory cell of the ninth synapse string of the thirteenth memory block.

[0067] With reference to Figure 3 and Figure 4The sub-weight data W9 is written into the second memory cell of the second synapse string of the fourteenth memory block, the sub-weight data W8 is written into the second memory cell of the third synapse string of the fourteenth memory block, the sub-weight data W6 is written into the second memory cell of the fifth synapse string of the fourteenth memory block, the sub-weight data W5 is written into the second memory cell of the sixth synapse string of the fourteenth memory block, the sub-weight data W3 is written into the second memory cell of the eighth synapse string of the fourteenth memory block, and the sub-weight data W2 is written into the second memory cell of the ninth synapse string of the fourteenth memory block.

[0068] Referring to Figure 3 and Figure 4 The sub-weight data W9 is written into the second memory cell of the third synapse string of the fifteenth memory block, the sub-weight data W6 is written into the second memory cell of the sixth synapse string of the fifteenth memory block, and the sub-weight data W3 is written into the second memory cell of the ninth synapse string of the fifteenth memory block.

[0069] Referring to Figure 3 and Figure 4 The sub-weight data W7 is written into the second memory cell of the fourth synapse string of the sixteenth memory block, and the sub-weight data W4 is written into the second memory cell of the seventh synapse string of the sixteenth memory block.

[0070] Referring to Figure 3 and Figure 4 The sub-weight data W8 is written into the second memory cell of the fourth synapse string of the seventeenth memory block, the sub-weight data W7 is written into the second memory cell of the fifth synapse string of the seventeenth memory block, the sub-weight data W5 is written into the second memory cell of the seventh synapse string of the seventeenth memory block, and the sub-weight data W4 is written into the second memory cell of the eighth synapse string of the seventeenth memory block.

[0071] Referring to Figure 3 and Figure 4 The sub-weight data W9 is written into the second memory cell of the fourth synapse string of the eighteenth memory block, the sub-weight data W8 is written into the second memory cell of the fifth synapse string of the eighteenth memory block, the sub-weight data W7 is written into the second memory cell of the sixth synapse string of the eighteenth memory block, the sub-weight data W6 is written into the second memory cell of the seventh synapse string of the eighteenth memory block, the sub-weight data W5 is written into the second memory cell of the eighth synapse string of the eighteenth memory block, and the sub-weight data W4 is written into the second memory cell of the ninth synapse string of the eighteenth memory block.

[0072] Referring to Figure 3 and Figure 4sub-weight data W9 is written into the second memory cell of the sixth synapse string of the twentieth memory block, and sub-weight data W9 is written into the second memory cell of the ninth synapse string of the twentieth memory block.

[0073] Referring to Figure 3 and Figure 4 sub-weight data W9 is written into the second memory cell of the sixth synapse string of the twentieth memory block, and sub-weight data W9 is written into the second memory cell of the ninth synapse string of the twentieth memory block.

[0074] Referring to Figure 3 and Figure 4 sub-weight data W7 is written into the second memory cell of the seventh synapse string of the twenty-first memory block.

[0075] Referring to Figure 3 and Figure 4 sub-weight data W8 is written into the second memory cell of the seventh synapse string of the twenty-second memory block, and sub-weight data W7 is written into the second memory cell of the eighth synapse string of the twenty-second memory block.

[0076] Referring to Figure 3 and Figure 4 sub-weight data W9 is written into the second memory cell of the seventh synapse string of the twenty-third memory block, sub-weight data W8 is written into the second memory cell of the eighth synapse string of the twenty-third memory block, and sub-weight data W7 is written into the second memory cell of the ninth synapse string of the twenty-third memory block.

[0077] Referring to Figure 3 and Figure 4 sub-weight data W9 is written into the second memory cell of the eighth synapse string of the twenty-fourth memory block, and sub-weight data W8 is written into the second memory cell of the ninth synapse string of the twenty-fourth memory block.

[0078] Referring to Figure 3 and Figure 4 sub-weight data W9 is written into the second memory cell of the ninth synapse string of the twenty-fifth memory block.

[0079] Referring to Figure 3 and Figure 4to all word lines of the first memory block, applying a second target voltage to all word lines of the second memory block, applying a third target voltage to all word lines of the third memory block, applying a fourth target voltage to all word lines of the fourth memory block, applying a fifth target voltage to all word lines of the fifth memory block, applying a sixth target voltage to all word lines of the sixth memory block, applying a seventh target voltage to all word lines of the seventh memory block, applying an eighth target voltage to all word lines of the eighth memory block, applying a ninth target voltage to all word lines of the ninth memory block, applying a tenth target voltage to all word lines of the tenth memory block, applying an eleventh target voltage to all word lines of the eleventh memory block, applying a twelfth target voltage to all word lines of the twelfth memory block, applying a thirteenth target voltage to all word lines of the thirteenth memory block, applying a fourteenth target voltage to all word lines of the fourteenth memory block, applying a fifteenth target voltage to all word lines of the fifteenth memory block, applying a sixteenth target voltage to all word lines of the sixteenth memory block, applying a seventeenth target voltage to all word lines of the seventeenth memory block, applying an eighteenth target voltage to all word lines of the eighteenth memory block, applying a nineteenth target voltage to all word lines of the nineteenth memory block, applying a twentieth target voltage to all word lines of the twentieth memory block, applying a twenty-first target voltage to all word lines of the twenty-first memory block, applying a twenty-second target voltage to all word lines of the twenty-second memory block, applying a twenty-third target voltage to all word lines of the twenty-third memory block, applying a twenty-fourth target voltage to all word lines of the twenty-fourth memory block, applying a twenty-fifth target voltage to all word lines of the twenty-fifth memory block.

[0080] The first target voltage is sub-feature data A1, the second target voltage is sub-feature data A2, the third target voltage is sub-feature data A3, the fourth target voltage is sub-feature data A4, the fifth target voltage is sub-feature data A5, the sixth target voltage is sub-feature data A6, the seventh target voltage is sub-feature data A7, the eighth target voltage is sub-feature data A8, the ninth target voltage is sub-feature data A9, the tenth target voltage is sub-feature data A10, the eleventh target voltage is sub-feature data A11, the twelfth target voltage is sub-feature data A12, the thirteenth target voltage is sub-feature data A13, the fourteenth target voltage is sub-feature data A14, the fifteenth target voltage is sub-feature data A15, the sixteenth target voltage is sub-feature data A16, the seventeenth target voltage is sub-feature data A17, the eighteenth target voltage is sub-feature data A18, the nineteenth target voltage is sub-feature data A19, the twentieth target voltage is sub-feature data A20, the twenty-first target voltage is sub-feature data A21, the twenty-second target voltage is sub-feature data A22, the twenty-third target voltage is sub-feature data A23, the twenty-fourth target voltage is sub-feature data A24, and the twenty-fifth target voltage is sub-feature data A25.

[0081] Referring to Figure 3 , the NAND flash memory further includes a data selector connected with the memory blocks to transmit signals to word lines, drain side select gate lines, and source side select gate lines of different memory blocks.

[0082] Referring to Figure 4 , Figure 3 and Figure 4, the page buffer opens all the drain side select transistors in the first to twenty-fifth memory blocks when the page buffer senses the current of the memory block, the current sensed by the first page buffer corresponds to A1xW1+A2xW2+A3xW3+A6xW4+A7xW5+A8xW6+A11xW7+A12xW8+A13xW9, to obtain a first sub-convolution result B1; the current sensed by the second page buffer corresponds to A2xW1+A3xW2+A4xW3+A7xW4+A8xW5+A9xW6+A12xW7+A13xW8+A14xW9, to obtain a second sub-convolution result B2; the current sensed by the third page buffer corresponds to A3+A4+A5+A8+A9+A10+A13+A14+A15, to obtain a third sub-convolution result B3; the current sensed by the fourth page buffer corresponds to A6+A7+A8+A11+A12+A13+A16+A17+A18, to obtain a fourth sub-convolution result B4; the current sensed by the fifth page buffer corresponds to A7+A8+A9+A12+A13+A14+A17+A18+A19, to obtain a fifth sub-convolution result B5; the current sensed by the sixth page buffer corresponds to A8+A9+A10+A13+A14+A15+A18+A19+A20, to obtain a sixth sub-convolution result B6; the current sensed by the seventh page buffer corresponds to A11+A12+A13+A16+A17+A18+A21+A22+A23, to obtain a seventh sub-convolution result B7; the current sensed by the eighth page buffer corresponds to A12+A13+A14+A17+A18+A19+A22+A23+A24, to obtain an eighth sub-convolution result B8; the current sensed by the ninth page buffer corresponds to A13+A14+A15+A18+A19+A20+A23+A24+A25, to obtain a ninth sub-convolution result B9.

[0083] Figure 3 The circuit schematic diagram of the page buffer in some embodiments of the present application is shown in FIG. 1. Referring to FIG. 1, Figure 4The page buffer comprises a first PMOS transistor MP0, a second PMOS transistor MP1, a first NMOS transistor MN0, a second NMOS transistor MN1, a third NMOS transistor MN2, a fourth NMOS transistor MN3, a fifth NMOS transistor MN4, a capacitor C and a cache, a source of the first PMOS transistor MP0 is connected to a power voltage vdd, a gate of the first PMOS transistor MP0 is connected to a first control signal prech_all, a drain of the first PMOS transistor MP0 is connected to a drain of the second NMOS transistor MN1 and a source of the second PMOS transistor MP1, a gate of the second NMOS transistor MN1 is connected to a second control signal blclamp2, a gate of the second PMOS transistor MP1 is connected to a third control signal blpre, a source of the second NMOS transistor MN1 is connected to a drain of the first NMOS transistor MN0 and a source of the third NMOS transistor MN2, a connection point is tdc, a gate of the first NMOS transistor MN0 is connected to a fourth control signal blclamp, a source of the first NMOS transistor MN0 is connected to a bit line BL, a gate of the third NMOS transistor MN2 is connected to a fifth control signal tciso, a drain of the second PMOS transistor MP1 is connected to a gate of the fourth NMOS transistor MN3, one end of the capacitor C and a drain of the third NMOS transistor MN2, a connection point is tc, the other end of the capacitor C is connected to ground, a source of the fourth NMOS transistor MN3 is connected to ground, a drain of the fourth NMOS transistor MN3 is connected to a source of the fifth NMOS transistor MN4, a drain of the fifth NMOS transistor MN4 is connected to the cache, and a gate of the fifth NMOS transistor MN4 is connected to a sixth control signal en.

[0084] Figure 3 The timing diagram of the page buffer shown in some embodiments of the present application is shown in FIG. 3. Figure 4 Figure 3 In FIG. 3, T1 represents the first stage, T2 represents the second stage, T3 represents the third stage, MN3 Vt represents the threshold voltage of the fourth NMOS transistor, pam cell represents that the storage unit is in the programming state, erase cell represents that the storage unit is in the erasing state, vblclamp represents the voltage when the fourth control signal is at the high level, vblclamp2 represents the voltage when the second control signal blclamp2 is at the high level, and vtciso represents the voltage when the fifth control signal is at the high level.

[0085] Figure 4 The circuit diagram of the page buffer in some other embodiments of the present application is shown in FIG. 4. Figure 3 ​The page buffer comprises a first PMOS transistor MP0, a second PMOS transistor MP1, a third PMOS transistor MP2, a fourth PMOS transistor MP3, a first NMOS transistor MN0, a second NMOS transistor MN1, a third NMOS transistor MN2, a capacitor C and a cache, a source of the first PMOS transistor MP0 is connected to a power supply voltage vdd, a gate of the first PMOS transistor MP0 is connected to a first control signal prech_all, a drain of the first PMOS transistor MP0 is connected to a drain of the second NMOS transistor MN1 and a source of the second PMOS transistor MP1, a gate of the second NMOS transistor MN1 is connected to a second control signal blclamp2, a gate of the second PMOS transistor MP1 is connected to a third control signal blpre, a source of the second NMOS transistor MN1 is connected to a drain of the first NMOS transistor MN0 and a source of the third NMOS transistor MN2, a connection point is tdc, a gate of the first NMOS transistor MN0 is connected to a fourth control signal blclamp, a source of the first NMOS transistor MN0 is connected to a bit line BL, a gate of the third NMOS transistor MN2 is connected to a fifth control signal tciso, the drain of the second PMOS transistor MP1 is connected to a gate of the third PMOS transistor MP3, one end of the capacitor C and a drain of the third NMOS transistor MN2, a connection point is tc, the other end of the capacitor C is connected to ground, a source of the third PMOS transistor MP2 is connected to the power supply voltage vdd, a drain of the third PMOS transistor MP2 is connected to a source of the fourth PMOS transistor MP3, a drain of the fourth PMOS transistor MP3 is connected to the cache, and a gate of the fourth PMOS transistor MP3 is connected to a sixth control signal enb.

[0086] Figure 4 The timing diagram of the page buffer shown in some embodiments of the present application is as follows. Figure 3 The timing diagram of the page buffer shown in some embodiments of the present application is as follows. Figure 4 In the timing diagram, T1 represents the first stage, T2 represents the second stage, T3 represents the third stage, MP2 Vt represents the threshold voltage of the third PMOS transistor, pam cell represents that a storage unit is in a programming state, erase cell represents that a storage unit is in an erasing state, vblclamp represents a voltage when the fourth control signal is at a high level, vblclamp2 represents a voltage when the second control signal blclamp2 is at a high level, and vtciso represents a voltage when the fifth control signal is at a high level.

[0087] In some embodiments, the sensing the current of the memory block by the page buffer to obtain the convolution result comprises: dividing the sensing time of the page buffer into N segments; discharging the pre-charge voltage of the page buffer by the bit line until the pre-charge voltage of the page buffer is less than a threshold voltage, and recording this time as the Mth segment; and obtaining the convolution result according to M and N, M and N being natural numbers greater than 0. For example, the pre-charge voltage of the page buffer is the voltage at the connection point tc, and the threshold voltage is the threshold voltage of the fourth NMOS transistor. In each segment before the Mth segment, the value is 0, and in each segment after the Mth segment, the value is 1. In some specific embodiments, for example, N is 10 and M is 5, and the sub-convolution result is 0000111111. Figure 3 Figure 4 Figure 3 Figure 4 Figure 3 Figure 4 Figure 3 Figure 4 Figure 3 Figure 4 Figure 3 Figure 4 Figure 3 Figure 4 Figure 3 Figure 4 Figure 3 Figure 4 Figure 3 Figure 4 Figure 3 Figure 4 Figure 3 Figure 4 Figure 3 Figure 4 Figure 3 Figure 4 Figure 3 Figure 4 Figure 3 Figure 4 Figure 3 Figure 4 Figure 3 Figure 4 Figure 3 Figure 4 Figure 3 Figure 4 Figure 3 Figure 4 Figure 3 Figure 4 Figure 3

[0088] In some embodiments, the control method for implementing neural network operation of the NAND flash further comprises a calibration step, and the calibration step comprises: taking a storage unit with known weight data and feature data as a reference unit, taking the current sensed by the page buffer of the reference unit as a reference, and calibrating the sensing time of the page buffer.

[0089] Although the embodiments of the present application have been described in detail above, it is obvious to those skilled in the art that various modifications and changes can be made to the embodiments without departing from the scope and spirit of the present application as described in the following claims. Moreover, the present application described herein can have other embodiments and can be implemented or realized in various ways.​

Claims

1. A control method for implementing neural network operations using NAND flash memory, characterized in that, Includes the following steps: S0: Provide NAND flash memory, the NAND flash memory including a plurality of storage blocks and a plurality of page buffers, the storage blocks including a plurality of synapse strings, a plurality of bit lines and a plurality of word lines, the synapse strings including a plurality of serially connected storage cells, the synapse strings being connected one-to-one with the bit lines, the word lines being connected to all the synapse strings, the page buffers being connected to all the storage blocks, and one bit line being connected to only one page buffer; S1: Write the weight data into the storage unit according to the relationship between the weight data and the feature data; S2: Apply a target voltage to the memory cell through the word line; S3: The current of the storage block is sensed through the page buffer to obtain the convolution result; The step of sensing the current of the memory block through the page buffer to obtain the convolution result includes: The sensing time of the page buffer is divided into N segments; The precharge voltage of the page buffer is discharged through the bit line until the precharge voltage of the page buffer is less than the threshold voltage, and this point is recorded as the Mth segment. The convolution result is obtained based on M and N, where M and N are natural numbers greater than 0.

2. The control method for implementing neural network operations using NAND flash memory according to claim 1, characterized in that, The feature data includes several sub-feature data, the weight data includes several sub-weight data, each sub-feature data corresponds to one of the storage blocks, and one sub-feature data corresponds to at least one sub-weight data.

3. The control method for implementing neural network operations using NAND flash memory according to claim 2, characterized in that, The step of writing the weight data into the storage unit according to the relationship between the weight data and the feature data includes: According to the correspondence between the sub-weight data and the sub-feature data, all the sub-weight data corresponding to a sub-feature data are written into different storage units of the storage block corresponding to the sub-feature data, and different storage units are connected to the same word line.

4. The control method for implementing neural network operations in NAND flash memory according to claim 3, characterized in that, The target voltage includes several sub-target voltages, each sub-target voltage corresponding one-to-one with the sub-feature data. Applying the target voltage to the memory cell through the word line includes: A sub-target voltage corresponding to the sub-feature data is applied to all the memory cells of the memory block corresponding to the sub-feature data and held through the word line.

5. The control method for implementing neural network operations using NAND flash memory according to claim 1, characterized in that, The convolution result includes several sub-convolution results. The several sub-convolution results are used as new feature data, and steps S1 to S3 are repeated to achieve the next layer of convolution operation.

6. The control method for implementing neural network operations using NAND flash memory according to claim 1, characterized in that, It also includes a calibration step, which includes: Using the storage unit containing known weight data and feature data as a reference unit, and taking the current of the reference unit sensed by the page buffer as a reference, the sensing time of the page buffer is calibrated.

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