Readout circuit architecture

Abstract

Embodiments of the present application relate to the field of semiconductor layout design, and particularly to a readout circuit architecture, including: a first NMOS layout, including a first N-type active layer and a first gate layer disposed separately on the first N-type active layer; a second NMOS layout, including a second N-type active layer and a second gate layer disposed separately on the second N-type active layer; a first PMOS layout, including a first P-type active layer and a third gate layer disposed separately on the first P-type active layer; a second PMOS layout, including a second P-type active layer and a fourth gate layer disposed separately on the second P-type active layer; a first processing structure layout, a first active layer and a first isolation gate; a second processing structure layout, a second active layer and a second isolation gate. Embodiments of the present application can eliminate offset noise in the readout circuit without introducing many offset cancellation MOS transistors, which is beneficial to improving the integration of DRAM.

Description

Technical Field

[0001] This application relates to the field of semiconductor circuit layout, and particularly to a readout circuit architecture. Background Art

[0002] Dynamic Random Access Memory (DRAM) writes data through the charge in the cell capacitor; the cell capacitor is connected to the bit line and the complementary bit line. In DRAM, when a read operation or a refresh operation is performed, the sense amplifier reads and amplifies the voltage difference between the bit line and the complementary bit line.

[0003] The semiconductor devices that make up the sense amplifier may have different device characteristics (e.g., threshold voltage) due to factors such as process variations and temperature. Different device characteristics will cause offset noise to be generated in the sense amplifier, and the offset noise will reduce the effective read margin of the sense amplifier and will also reduce the performance of DRAM.

[0004] The applicant has found that in the current process of eliminating the offset noise of DRAM, MOS transistors dedicated to offset cancellation need to be specially designed, thereby increasing the layout area required for the sense amplifier circuit, which is not conducive to the improvement of the integration of DRAM.

[0005] Therefore, how to eliminate the offset noise in the readout circuit without introducing too many offset cancellation MOS transistors is an urgent problem to be solved at present. Summary of the Invention

[0006] The embodiments of this application provide a readout circuit architecture, which can eliminate the offset noise in the readout circuit without introducing too many offset cancellation MOS transistors, and is conducive to the improvement of the integration of DRAM.

[0007] An embodiment of the present application provides a readout circuit architecture, including: a first NMOS layout, including a first N-type active layer discretely arranged in a first direction, and a first gate layer disposed on the first N-type active layer and discretely arranged; a second NMOS layout, including a second N-type active layer discretely arranged in the first direction, and a second gate layer disposed on the second N-type active layer and discretely arranged; a first PMOS layout, including a first P-type active layer discretely arranged in the first direction, and a third gate layer disposed on the first P-type active layer and discretely arranged; a second PMOS layout, including a second P-type active layer discretely arranged in the first direction, and a fourth gate layer disposed on the second P-type active layer and discretely arranged; a first processing structure layout, including a first active layer discretely arranged in the first direction and extending in a second direction, and a first isolation gate disposed on the first active layer and extending in the second direction; a second processing structure layout, including a second active layer discretely arranged in the first direction and extending in the second direction, and a second isolation gate disposed on the first active layer and extending in the second direction; the first direction and the second direction intersect.

[0008] During the offset cancellation process, the gate of the first PMOS transistor is connected to the complementary read bit line, and the drain is connected to the read bit line. After the first PMOS transistor is turned on, the first signal terminal is electrically connected to the read bit line, and the first signal terminal is used to receive the high level corresponding to logic "1", that is, the first signal terminal receives the internal power supply voltage of the chip. At this time, the turned-on first PMOS transistor affects the level of the read bit line based on the level and threshold voltage of the complementary read bit line. The gate of the second PMOS transistor is connected to the read bit line, and the drain is connected to the complementary read bit line. After the second PMOS transistor is turned on, the first signal terminal is electrically connected to the read bit line, and the first signal terminal is used to receive the high level corresponding to logic "1", that is, the first signal terminal is the internal power supply voltage of the chip. At this time, the turned-on second PMOS transistor affects the level of the complementary read bit line based on the level and threshold voltage of the read bit line. The difference in the threshold voltages of the first PMOS transistor and the second PMOS transistor will cause a difference in the levels of the read bit line and the complementary read bit line, that is, the offset noise of the first PMOS transistor and the second PMOS transistor is reflected through the levels of the read bit line and the complementary read bit line. The gate of the first NMOS transistor is connected to the complementary read bit line, and the drain is connected to the bit line; the gate of the second NMOS transistor is connected to the read bit line, and the drain is connected to the complementary bit line; due to the connection method of the first isolation MOS transistor <11> and the second isolation MOS transistor <12>, when the offset cancellation is in progress, the first isolation MOS transistor <11> and the second isolation MOS transistor <12> are not turned on, and the second signal terminal is also used to receive the high level corresponding to logic "1", that is, the first signal terminal receives the internal power supply voltage of the chip; so that the conduction difference between the first NMOS transistor and the second NMOS transistor does not affect the read bit line and the complementary read bit line, but directly adjusts the bit line voltage and the complementary bit line voltage. In addition, since the levels of the read bit line and the complementary read bit line have reflected the offset noise of the first PMOS transistor and the second PMOS transistor, and the conduction degree of the first NMOS transistor is determined based on the level of the complementary read bit line and the threshold voltage of the first NMOS transistor, and the conduction degree of the second NMOS transistor is determined based on the level of the read bit line and the threshold voltage of the second NMOS transistor; at this time, after the first NMOS transistor and the second NMOS transistor are turned on based on the complementary read bit line and the read bit line respectively, the adjusted bit line voltage and the complementary bit line reflect the offset noise of the first PMOS transistor and the second PMOS transistor, and at the same time reflect the offset noise of the first NMOS transistor and the second NMOS transistor, that is, the offset cancellation operation of the read circuit is completed. Therefore, the layout of the read circuit provided by the embodiments of the present application can avoid laying out offset cancellation MOS transistors, thereby reducing the layout area of the read circuit. Description of the Drawings

[0009] Figure 1 It is a schematic circuit structure diagram of the read circuit provided by the embodiments of the present application;

[0010] Figures 2 to 15 It is a schematic layout structure diagram of the read circuit provided by the embodiments of the present application. Detailed implementation manners

[0011] Semiconductor devices constituting a sense amplifier may have different device characteristics (e.g., threshold voltage) due to process variations, temperature, and other factors. Different device characteristics can cause offset noise in the sense amplifier, and the offset noise will reduce the effective read margin of the sense amplifier and degrade the performance of the DRAM.

[0012] Currently, in the process of eliminating the offset noise of the DRAM, a MOS transistor dedicated to offset cancellation needs to be specially designed, thereby increasing the layout area required for the sense amplifier circuit, which is not conducive to improving the integration degree of the DRAM.

[0013] The embodiment of the present application provides a read circuit architecture, including: a first NMOS layout, including a first N-type active layer discretely arranged in a first direction, and a first gate layer arranged discretely on the first N-type active layer; a second NMOS layout, including a second N-type active layer discretely arranged in the first direction, and a second gate layer arranged discretely on the second N-type active layer; a first PMOS layout, including a first P-type active layer discretely arranged in the first direction, and a third gate layer arranged discretely on the first P-type active layer; a second PMOS layout, including a second P-type active layer discretely arranged in the first direction, and a fourth gate layer arranged discretely on the second P-type active layer; a first processing structure layout, including a first active layer discretely arranged in the first direction and extending in a second direction, and a first isolation gate arranged on the first active layer and extending in the second direction; a second processing structure layout, including a second active layer discretely arranged in the first direction and extending in the second direction, and a second isolation gate arranged on the first active layer and extending in the second direction; the first direction and the second direction intersect.

[0014] Those of ordinary skill in the art can understand that in various embodiments of the present application, many technical details are proposed to help readers better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0015] Figure 1 It is a schematic circuit diagram of the read circuit provided in this embodiment. Figures 2 to 15 It is a schematic layout diagram of the read circuit provided in this embodiment. The read circuit architecture provided in each embodiment of the present application will be further described in detail below with reference to the accompanying drawings, specifically as follows:

[0016] It should be noted that, in this embodiment, an example is given where the first direction is perpendicular to the second direction. The first direction is horizontal (the extending direction of the storage array gap), and the second direction is vertical (the width direction of the storage array gap); since perpendicularity is a special case of intersection, in other embodiments, those skilled in the art can set the intersection manner of the first direction and the second direction at any angle, and this embodiment still applies.

[0017] Reference Figure 1 and Figure 2 , the readout circuit architecture includes:

[0018] The first NMOS layout includes a first N-type active layer 101 separately arranged in the first direction, and a first gate layer 102 separately arranged on the first N-type active layer 101; wherein, the first gate layer 102 is electrically connected to the complementary read bit line SABLB, and the first N-type active layers 101 on both sides of the first gate layer 102 are respectively electrically connected to the bit line BL and the second signal terminal.

[0019] The first NMOS layout is used to form the first NMOS transistor <n1>, the first NMOS transistor <n1>is connected between the second signal terminal and the bit line BL and has a control terminal connected to the complementary read bit line SABLB. Specifically, the first NMOS transistor <n1>The source electrode is connected to the second signal terminal, the drain electrode is connected to the bit line BL, and the gate electrode is connected to the complementary sense bit line SABLB.

[0020] The second NMOS layout includes a second N-type active layer 103 discretely arranged in the first direction and a second gate layer 104 arranged discretely on the second N-type active layer 103; wherein, the second gate layer 104 is electrically connected to the sense bit line SABL, and the second N-type active layers 103 on both sides of the second gate layer 104 are respectively electrically connected to the complementary bit line BLB and the second signal terminal.

[0021] The second NMOS layout is used to form a second NMOS transistor <n2>, the second NMOS transistor <n2>Connected between the second signal terminal and the complementary bit line BLB, and having a control terminal connected to the sense bit line SABL. Specifically, the second NMOS transistor <n2>Its source is connected to the second signal terminal, its drain is connected to the complementary bit line BLB, and its gate is connected to the sense bit line SABL.

[0022] The first PMOS layout includes a first P-type active layer 201 discretely arranged in the first direction, and a third gate layer 202 disposed on the first P-type active layer 201 and discretely arranged; wherein, the third gate layer 202 is electrically connected to the complementary sense bit line SABLB, and the first P-type active layers 201 on both sides of the third gate layer 202 are respectively electrically connected to the sense bit line SABL and the first signal terminal.

[0023] The first PMOS layout is used to form the first PMOS transistor <p1>, the first PMOS transistor <p1>Connected between the first signal terminal and the sense bit line SABL, and having a control terminal connected to the complementary sense bit line SABLB. Specifically, the first PMOS transistor <p1>The source electrode is connected to the first signal terminal, the drain electrode is connected to the readout bit line SABL, and the gate electrode is connected to the complementary readout bit line SABLB.

[0024] The second PMOS layout includes a second P-type active layer 203 arranged separately in the first direction, and a fourth gate layer 204 arranged separately on the second P-type active layer 203; wherein, the fourth gate layer 204 is electrically connected to the readout bit line SABL, and the second P-type active layers 203 on both sides of the fourth gate layer 204 are respectively electrically connected to the complementary readout bit line SABLB and the first signal terminal.

[0025] The second PMOS layout is used to form the second PMOS transistor <p2>, the second PMOS transistor <p2>is connected between the first signal terminal and the complementary read bit line SABLB, and has a control terminal connected to the read bit line SABL. Specifically, the second PMOS transistor <p2>Its source is connected to the first signal terminal, its drain is connected to the complementary read bit line SABLB, and its gate is connected to the read bit line SABL.

[0026] The layout of the first processing structure includes a first active layer 301 that is discretely arranged in the first direction and extends in the second direction, and a first isolation gate 311 that is disposed on the first active layer 301 and extends in the second direction; wherein, due to receiving an isolation signal (Isolation Signal, ISO), the first active layers 301 on both sides of the first isolation gate 311 are electrically connected to the bit line BL and the read bit line SABL respectively.

[0027] The first active layer 301 and the first isolation gate 311 are used to form a first isolation MOS transistor <11>. The source of the first isolation MOS transistor <11> is connected to the bit line BL, the drain is connected to the read bit line SABL, the gate is used to receive the isolation signal ISO, and the first isolation MOS transistor <11> is used to conduct according to the isolation signal to electrically connect the bit line BL and the read bit line SABL.

[0028] The layout of the second processing structure includes a second active layer 302 that is discretely arranged in the first direction and extends in the second direction, and a second isolation gate 312 that is disposed on the second active layer 302 and extends in the second direction; wherein, the second isolation gate 312 is used to receive the isolation signal ISO, and the second active layers 302 on both sides of the second isolation gate 312 are electrically connected to the complementary bit line BLB and the complementary read bit line SABLB respectively.

[0029] The second active layer 302 and the second isolation gate 312 are used to form a second isolation MOS transistor <12>. The source of the second isolation MOS transistor <12> is connected to the complementary bit line BLB, the drain is connected to the complementary read bit line SABLB, the gate is used to receive the isolation signal ISO, and the second isolation MOS transistor <12> is used to conduct according to the isolation signal to electrically connect the complementary bit line BLB and the complementary read bit line SABLB.

[0030] For the bit line BL and the complementary bit line BLB, the bit line BL is connected to the memory cell <01> of a memory array 400 in an adjacent memory array 400, and the complementary bit line BLB is connected to the memory cell <02> of another memory array 400 in the adjacent memory array 400.

[0031] During the offset cancellation process, both the first signal terminal and the second signal terminal are used to receive the high level corresponding to logic "1"; during the data readout process, the first signal terminal is used to receive the high level corresponding to logic "1", and the second signal terminal is used to receive the low level corresponding to logic "0". In this embodiment, the voltage of the first level signal (Positive Cell Storing Signal, PCS) is greater than the voltage of the second level signal (Negative Cell Storing Signal, NCS), that is, the first level signal PCS is the high level corresponding to logic "1", and the second level signal NCS is the low level corresponding to logic "0"; in other embodiments, it can also be set that the voltage of the first level signal is less than the voltage of the second level signal, that is, the first level signal is the low level corresponding to logic "0", and the second level signal is the high level corresponding to logic "1".

[0032] For the memory, before data readout, the memory pre-charges the bit line BL, complementary bit line BLB, sense bit line SABL, and complementary sense bit line SABLB to a preset voltage.

[0033] For the readout circuit of this embodiment, in the first readout stage, that is, the offset cancellation stage of the memory, the first level signal PCS is provided to the first signal terminal and the second signal terminal; the first PMOS transistor <p1>The gate of which is connected to the complementary read bit line SABLB, the drain is connected to the read bit line SABL, the source is connected to the first signal terminal, and the first PMOS transistor <p1>After the preset voltage based on the complementary read bit line SABLB is turned on, the first signal terminal is electrically connected to the read bit line SABL, and the read bit line SABL is pulled high under the action of the first level signal PCS; the second PMOS transistor <p2>The gate is connected to the sense bit line SABL, the drain is connected to the complementary sense bit line SABLB, the source is connected to the first signal terminal, and the second PMOS transistor <p2>After being turned on based on the preset voltage of the sense bit line SABL, the first signal terminal is electrically connected to the complementary sense bit line SABLB, and the complementary sense bit line SABLB is pulled high under the action of the first level signal PCS.

[0034] After the levels of the sense bit line SABL and the complementary sense bit line SABLB are pulled high, the first PMOS transistor <p1>and the second PMOS transistor <p2>Turn off. However, since the semiconductor devices that make up the sense amplifier may have different device characteristics (e.g., threshold voltage) due to factors such as process variations and temperature, that is, due to the influence of external factors or the formation process, the first PMOS transistor <p1>and the second PMOS transistor <p2>There are differences in the threshold voltages, that is, the first PMOS transistor <p1>and the second PMOS transistor <p2>Based on different conduction capabilities after being turned on by a preset voltage, the first PMOS transistor <p1>and the second PMOS transistor <p2>After conduction, there is a difference in the levels of the read bit line SABL and the complementary read bit line SABLB, that is, the first PMOS transistor <p1>and the second PMOS transistor <p2>The offset noise. Due to the connection manner of the first isolation MOS transistor <11> and the second isolation MOS transistor <12>, during the offset cancellation process, the first isolation MOS transistor <11> and the second isolation MOS transistor <12> are not conducting. At this time, the level of the sense bit line SABL is not synchronized to the bit line BL, and the level of the complementary sense bit line SABLB is not synchronized to the complementary bit line BLB.

[0035] After the levels of the sense bit line SABL and the complementary sense bit line SABLB are pulled high, due to the first NMOS transistor <n1>The gate of the first NMOS transistor is connected to the complementary read bit line SABLB, the drain is connected to the bit line BL, and the source is connected to the second signal terminal. <n1>Based on the conduction of the complementary read bit line SABLB after being pulled high, the first NMOS transistor <n1>After conduction, the bit line BL is electrically connected to the second signal terminal, and the bit line BL is pulled high under the action of the first-level signal PCS; due to the second NMOS transistor <n2>The gate of which is connected to the readout bit line SABL, the drain complementary bit line BLB, and the source is connected to the second signal terminal, the second NMOS transistor <n2>Based on the conduction of the read bit line SABL after being pulled high, the second NMOS transistor <n2>After conduction, the complementary bit line BLB is electrically connected to the second signal terminal, and the complementary bit line BLB is pulled high under the action of the first level signal PCS.

[0036] Since the semiconductor devices constituting the sense amplifier may have different device characteristics (e.g., threshold voltage) due to factors such as process variations and temperature, that is, due to the influence of external factors or the formation process, the first NMOS transistor <n1>and the second NMOS transistor <n2>There are differences in the threshold voltages, that is, the first NMOS transistor <n1>and the second NMOS transistor <n2>Based on different conduction capabilities after being turned on by a preset voltage, the first NMOS transistor <n1>and the second NMOS transistor <n2>After conduction, there is a difference in the levels of the bit line BL and the complementary bit line BLB, and the first NMOS transistor <n1>and the second NMOS transistor <n2>The turn-on voltage includes the first PMOS transistor <p1>and the second PMOS transistor <p2>offset noise, where the level difference between the bit line BL and the complementary bit line BLB includes the first PMOS transistor <p1>and the second PMOS transistor <p2>offset noise and the first NMOS transistor <n1>and the second NMOS transistor <n2>Offset noise. Assume that the first PMOS transistor <p1>and the first NMOS transistor <n1>Taking the <p2>and the second NMOS transistor <n2>The threshold voltages of all are less than that of the first PMOS transistor <p1>and the first NMOS transistor <n1>, after offset cancellation, based on the above discussion, the voltage of bit line BL is less than the voltage of complementary bit line BLB.

[0037] In the data sharing stage, the voltage of the target storage cell is shared onto bit line BL, and the voltage of the target storage cell is shared onto complementary bit line BLB. At this time, due to the execution of the offset cancellation process, the actual voltage of bit line BL is smaller than the theoretical voltage, so that in the second read stage, that is, in the actual sense amplifier stage, the first isolation MOS transistor <11> and the second isolation MOS transistor <12> are turned on, bit line BL is electrically connected to sense bit line SABL, and complementary bit line BLB is electrically connected to complementary sense bit line SABLB, enabling the second PMOS transistor with a relatively small threshold voltage originally <p2>and the second NMOS transistor <n2>The received gate voltage is relatively small, thereby achieving offset cancellation of the readout circuit.

[0038] In summary, the layout of the readout circuit provided in this embodiment can avoid the layout offset cancellation MOS transistor, thereby reducing the layout area of the readout circuit.

[0039] In one embodiment, referring to Figure 2 , the readout circuit architecture further includes:

[0040] The first processing structure layout further includes: a first precharge gate 321, disposed on the first active layer 301, extending in the first direction, and the first precharge gate 321 and the first isolation gate 311 are arranged in sequence in the second direction; wherein, the first precharge gate 321 is used to receive a precharge signal (Precharge Signal, PRE), and the first active layer 301 located on both sides of the first precharge gate 321 and far from the first isolation gate 311 is used to receive a preset voltage V BLP ; the first active layer 301 located on both sides of the first precharge gate 321 and shared with the first isolation gate 311 is connected to the bit line BL.

[0041] The first precharge gate 321 and the first active layer 301 are used to form a first precharge MOS transistor <21>, one terminal of the first precharge MOS transistor <21> is connected to the bit line BL, and the other terminal is used to receive the preset voltage V BLP , the control terminal is used to receive the precharge signal PRE, and the first precharge MOS transistor <21> is configured to conduct based on the precharge signal PRE. Specifically, in this embodiment, the source of the first precharge MOS transistor <21> is connected to the bit line BL, and the drain is used to receive the preset voltage V BLP , and the gate is used to receive the precharge signal PRE.

[0042] In this embodiment, the preset voltage V BLP = 1 / 2V DD , where V DD is the internal power supply voltage of the chip; in other embodiments, the preset voltage V BLP can be set according to specific application scenarios.

[0043] The second processing structure layout further includes: a second precharge gate 322 and a third precharge gate 323, disposed on the second active layer 302, extending in the first direction, and the second precharge gate 322, the second isolation gate 312, and the third precharge gate 323 are arranged in sequence in the second direction; wherein, the second precharge gate 322 is used to receive a precharge signal (Precharge Signal, PRE); the second active layer 302 located on both sides of the second precharge gate 322 and far from the second isolation gate 312 is used to receive the preset voltage V BLP ; The second active layer 302 located on both sides of the second precharge gate 322 and shared with the second isolation gate 312 is connected to the complementary bit line BLB; The third precharge gate 323 is used to receive a precharge signal (Precharge Signal, PRE); The second active layer 302 located on both sides of the third precharge gate 323 and far from the second isolation gate 312 is used to receive a preset voltage V BLP ; The second active layer 302 located on both sides of the third precharge gate 323 and shared with the second isolation gate 312 is connected to the sense bit line SABL or the complementary sense bit line SABLB.

[0044] The second precharge gate 322 and the second active layer 302 are used to form a second precharge MOS transistor <22>. One terminal of the second precharge MOS transistor <22> is connected to the complementary bit line BLB, and the other terminal is used to receive the preset voltage V BLP ; The control terminal is used to receive the precharge signal PRE. The second precharge MOS transistor <22> is configured to conduct based on the precharge signal PRE. Specifically, in this embodiment, the source of the second precharge MOS transistor <22> is connected to the complementary bit line BLB, and the drain is used to receive the preset voltage V BLP ; The gate is used to receive the precharge signal PRE.

[0045] In a specific example, the terminal of the first precharge MOS transistor <21> that receives the preset voltage V BLP and the terminal of the second precharge MOS transistor <22> that receives the preset voltage V BLP are connected. Specifically, the drain of the first precharge MOS transistor <21> and the drain of the second precharge MOS transistor <22> are connected to receive the preset voltage V BLP .

[0046] In a specific example, the control terminals of the first precharge MOS transistor <21> and the second precharge MOS transistor <22> are connected, that is, the gate of the first precharge MOS transistor <21> and the gate of the second precharge MOS transistor <22> are connected to receive the precharge signal PRE.

[0047] The third precharge gate 323 and the second active layer 302 are used to form a third precharge MOS transistor <23>. One terminal of the third precharge MOS transistor <23> is connected to the sense bit line SABL or the complementary sense bit line SABLB, and the other terminal is used to receive the preset voltage V BLP ; The control terminal is used to receive the precharge signal PRE. The third precharge MOS transistor <23> is configured to conduct based on the precharge signal PRE. Specifically, in this embodiment, the source of the third precharge MOS transistor <23> is connected to the sense bit line SABL or the complementary sense bit line SABLB, and the drain is used to receive the preset voltage V BLP , the gate is used to receive a pre-charge signal PRE.

[0048] Furthermore, the layout of the first processing structure further includes: an equalization gate 331, disposed on the first active layer 301, extending in a first direction, and the first pre-charge gate 321, the first isolation gate 311, and the equalization gate 331 are arranged in sequence in a second direction; wherein, the equalization gate 331 is used to receive an equalizing signal (Equalizing Signal, EQ); the first active layer 301 located on both sides of the equalization gate 331 and far from the first isolation gate 311 is connected to a complementary sense bit line SABLB; the first active layer 301 located on both sides of the equalization gate 331 and shared with the first isolation gate 311 is connected to SABL.

[0049] The equalization gate 331 and the first active layer 301 are used to form an equalization MOS transistor <31>, the equalization MOS transistor <31> is connected between the sense bit line SABL and the complementary sense bit line SABLB, and has a control terminal for receiving the equalizing signal EQ. Specifically, in this embodiment, the source of the equalization MOS transistor <31> is connected to the sense bit line SABL, the drain is connected to the complementary sense bit line SABLB, and the gate is used to receive the equalizing signal EQ.

[0050] During the offset cancellation process, the levels of the bit line BL and the sense bit line BLB are only affected by the first NMOS transistor <n1>and the second NMOS transistor <n2>The influence is that during the offset cancellation process, an equalization signal EQ can also be provided to turn on the equalization MOS transistor <31>, so that the read bit line SABL is electrically connected to the complementary read bit line SABLB to ignore the first PMOS transistor. <p1>and the second PMOS transistor <p2>The offset effect, thereby more accurately eliminating the first NMOS transistor <n1>and the second NMOS transistor <n2>Offset noise.

[0051] In another embodiment, with reference to Figure 3 and Figure 4 , the readout circuit architecture further includes:

[0052] With reference to Figure 3 , the first processing structure layout further includes: a first precharge gate 321 and a third precharge gate 323, which are disposed on the first active layer 301, extend in the first direction, and the first precharge gate 321, the first isolation gate 311, and the third precharge gate 323 are arranged in sequence in the second direction; wherein, the first precharge gate 321 is used to receive a precharge signal PRE, and the first active layer 301 on both sides of the first precharge gate 321 and away from the first isolation gate 311 is used to receive a preset voltage V BLP ; the first active layer 301 on both sides of the first precharge gate 321 and sharing the first isolation gate 311 is connected to the bit line BL; the third isolation gate 323 is used to receive the precharge signal PRE, and the first active layer 301 on both sides of the third precharge gate 323 and away from the first isolation gate 311 is used to receive the preset voltage V BLP ; the first active layer 301 on both sides of the third precharge gate 323 and sharing the first isolation gate 311 is connected to the readout bit line SABL or the complementary readout bit line SABLB. The first precharge gate 321 and the first active layer 301 are used to form a first precharge MOS transistor <21>, and the third precharge gate 323 and the first active layer 301 are used to form a third precharge MOS transistor <23>.

[0053] Furthermore, the first processing structure layout further includes: an equalization gate 331, which is disposed on the first active layer 301, extends in the first direction, and the first precharge gate 321, the first isolation gate 311, the equalization gate 331, and the third precharge gate 323 are arranged in sequence in the second direction; wherein, the equalization gate 331 is used to receive an equalization signal EQ; the first active layer 301 on both sides of the equalization gate 331 and sharing the third precharge gate 323 is connected to the readout bit line SABL; the first active layer 301 on both sides of the equalization gate 331 and sharing the first isolation gate 311 is connected to the complementary readout bit line SABLB. The equalization gate 331 and the first active layer 301 are used to form an equalization MOS transistor <31>.

[0054] The second processing structure layout further includes: a second precharge gate 322, which is disposed on the second active layer 302, extends in the first direction, and the second precharge gate 322 and the second isolation gate 312 are arranged in sequence in the second direction; wherein, the second precharge gate 322 is used to receive the precharge signal PRE; the second active layer 302 on both sides of the second precharge gate 322 and away from the second isolation gate 312 is used to receive the preset voltage V BLP ; The second active layer 302, which is located on both sides of the second precharge gate 322 and shares the second isolation gate 312, is connected to the complementary bit line BLB. The second precharge gate 322 and the second active layer 302 are used to form the second precharge MOS transistor <22>.

[0055] Reference Figure 4 , the layout of the first processing structure can be set such that the first isolation gate 311, the first precharge gate 321, the third precharge gate 323, and the equalization gate 331 are arranged in sequence in the second direction, and the layout of the second processing structure can be set such that the second isolation gate 312 and the second precharge gate 322 are arranged in sequence in the second direction.

[0056] In one example, reference Figures 5 to 7 , in the first direction, the first active layers 301 for electrically connecting the preset voltage V BLP are interconnected, and the second active layers 302 for electrically connecting the preset voltage V BLP are interconnected.

[0057] Specifically, reference Figure 5 , in the first active layer 301, among the multiple first precharge MOS transistors <21> arranged in the first direction, the active regions for connecting the preset voltage V BLP are interconnected. In the second active layer 302, among the multiple second precharge MOS transistors <22> arranged in the first direction, the active regions for connecting the preset voltage V BLP are interconnected; among the multiple third precharge MOS transistors <23> arranged in the first direction, the active regions for connecting the preset voltage V BLP are interconnected.

[0058] Specifically, reference Figure 6 , in the first active layer 301, among the multiple first precharge MOS transistors <21> arranged in the first direction, the active regions for connecting the preset voltage V BLP are interconnected; among the multiple third precharge MOS transistors <23> arranged in the first direction, the active regions for connecting the preset voltage V BLP are interconnected. In the second active layer 302, among the multiple second precharge MOS transistors <22> arranged in the first direction, the active regions for connecting the preset voltage V BLP are interconnected.

[0059] Specifically, reference Figure 7 , in the first active layer 301, among the multiple first precharge MOS transistors <21> and the multiple third precharge MOS transistors <23> arranged in the first direction, the active regions for connecting the preset voltage V BLP The active regions are interconnected. In the second active layer 302, among the multiple second pre-charge MOS transistors <22> arranged in the first direction, those for connecting to the preset voltage V BLP The active regions are interconnected.

[0060] In addition, this embodiment also provides various arrangement methods for the layout of the first processing structure, the layout of the second processing structure, the layout of the first NMOS, the layout of the second NMOS, the layout of the first PMOS, and the layout of the second PMOS.

[0061] Refer to Figures 2 to 7 , the first layout method is that in the second direction, the layout of the first processing structure, the layout of the first NMOS, the layout of the first PMOS, the layout of the second PMOS, the layout of the second NMOS, and the layout of the second processing structure are arranged in sequence.

[0062] Refer to Figures 8 to 10 , the second layout method is that in the second direction, the layout of the first processing structure, the layout of the first PMOS, the layout of the first NMOS, the layout of the second NMOS, the layout of the second PMOS, and the layout of the second processing structure are arranged in sequence.

[0063] It should be noted that this method is also applicable to the way of electrically connecting the first active layer 301 for connecting to the preset voltage V BLP which are interconnected, and the second active layer 302 for connecting to the preset voltage V BLP which are interconnected. However, no corresponding drawings are given in this embodiment, and those skilled in the art can reasonably deduce it based on the content disclosed in the first layout method.

[0064] Refer to Figure 11 and Figure 12 , the third layout method is that in the second direction, the layout of the first NMOS, the layout of the first processing structure, the layout of the first PMOS, the layout of the second PMOS, the layout of the second processing structure, and the layout of the second NMOS are arranged in sequence.

[0065] The fourth layout method is that in the second direction, the layout of the first PMOS, the layout of the first processing structure, the layout of the first NMOS, the layout of the second NMOS, the layout of the second processing structure, and the layout of the second PMOS are arranged in sequence.

[0066] Refer to Figure 13 , the fifth layout method is that in the second direction, the layout of the first PMOS, the layout of the first NMOS, the first processing structure, the second processing structure, the layout of the second NMOS, and the layout of the second PMOS are arranged in sequence.

[0067] Refer to Figure 14 , the sixth layout method is that in the second direction, the first NMOS layout, the first PMOS layout, the first processing structure, the second processing structure, the second PMOS layout, and the second NMOS layout are arranged in sequence.

[0068] It should be noted that in the fifth and sixth layout methods, the first active layer and the second active layer are connected. Further, referring to Figure 15 , the fifth and sixth layout methods are still applicable to the connection method in which the first active layers for electrically connecting the preset voltage V BLP are connected to each other, and the second active layers for electrically connecting the preset voltage V BLP are connected to each other.

[0069] It should be noted that the connection methods of the specific "source" and "drain" defined by the above transistors do not constitute a limitation on this embodiment. In other embodiments, the connection method of replacing the "source" with the "drain" and the "drain" with the "source" can be adopted.

[0070] During the offset cancellation process, the gate of the first PMOS transistor is connected to the complementary read bit line, and the drain is connected to the read bit line. After the first PMOS transistor is turned on, the first signal terminal is electrically connected to the read bit line, and the first signal terminal is used to receive the high level corresponding to logic "1", that is, the first signal terminal receives the internal chip power supply voltage. At this time, the turned-on first PMOS transistor affects the level of the read bit line based on the level and threshold voltage of the complementary read bit line; the gate of the second PMOS transistor is connected to the read bit line, and the drain is connected to the complementary read bit line. After the second PMOS transistor is turned on, the first signal terminal is electrically connected to the read bit line, and the first signal terminal is used to receive the high level corresponding to logic "1", that is, the first signal terminal is the internal chip power supply voltage. At this time, the turned-on second PMOS transistor affects the level of the complementary read bit line based on the level and threshold voltage of the read bit line. The threshold voltage difference between the first PMOS transistor and the second PMOS transistor will cause a level difference between the read bit line and the complementary read bit line, that is, through the levels of the read bit line and the complementary read bit line, the offset noise of the first PMOS transistor and the second PMOS transistor is reflected. The gate of the first NMOS transistor is connected to the complementary read bit line, and the drain is connected to the bit line; the gate of the second NMOS transistor is connected to the read bit line, and the drain is connected to the complementary bit line; due to the connection method of the first isolation MOS transistor <11> and the second isolation MOS transistor <12>, when the offset cancellation is in progress, the first isolation MOS transistor <11> and the second isolation MOS transistor <12> are not turned on, and the second signal terminal is also used to receive the high level corresponding to logic "1", that is, the first signal terminal receives the internal chip power supply voltage; so that the conduction difference between the first NMOS transistor and the second NMOS transistor does not affect the read bit line and the complementary read bit line, but directly adjusts the bit line voltage and the complementary bit line voltage. In addition, since the levels of the read bit line and the complementary read bit line have reflected the offset noise of the first PMOS transistor and the second PMOS transistor, and the conduction degree of the first NMOS transistor is determined based on the level of the complementary read bit line and the threshold voltage of the first NMOS transistor, and the conduction degree of the second NMOS transistor is determined based on the level of the read bit line and the threshold voltage of the second NMOS transistor; at this time, after the first NMOS transistor and the second NMOS transistor are turned on based on the complementary read bit line and the read bit line respectively, the adjusted bit line voltage and the complementary bit line reflect the offset noise of the first PMOS transistor and the second PMOS transistor, and at the same time reflect the offset noise of the first NMOS transistor and the second NMOS transistor, that is, the offset cancellation operation of the read circuit is completed. Therefore, the layout of the read circuit provided in this embodiment can avoid laying out the offset cancellation MOS transistors, thereby reducing the layout area of the read circuit.

[0071] It should be noted that, in order to highlight the innovative part of this application, units that are not closely related to solving the technical problems proposed in this application are not introduced in this embodiment. However, this does not mean that there are no other units in this embodiment. Those of ordinary skill in the art can understand that the above embodiments are specific embodiments for implementing this application, and in actual applications, various changes can be made to them in form and details without departing from the spirit and scope of this application.

[0072] Those of ordinary skill in the art can understand that the above embodiments are specific embodiments for implementing this application, and in actual applications, various changes can be made to them in form and details without departing from the spirit and scope of this application.

Claims

1. A readout circuit architecture, characterized in that, Including: The first NMOS layout includes a first N-type active layer discretely arranged in a first direction, and a first gate layer arranged discretely on the first N-type active layer; The second NMOS layout includes a second N-type active layer discretely arranged in a first direction, and a second gate layer arranged discretely on the second N-type active layer; The first PMOS layout includes a first P-type active layer discretely arranged in a first direction, and a third gate layer arranged discretely on the first P-type active layer; The second PMOS layout includes a second P-type active layer discretely arranged in a first direction, and a fourth gate layer arranged discretely on the second P-type active layer; The first processing structure layout includes a first active layer discretely arranged in a first direction and extending in a second direction, and a first isolation gate arranged on the first active layer and extending in the second direction; The second processing structure layout includes a second active layer discretely arranged in a first direction and extending in a second direction, and a second isolation gate arranged on the first active layer and extending in the second direction; The first direction and the second direction intersect; The first processing structure layout further includes: a first pre-charge gate arranged on the first active layer and extending in the first direction, and the first pre-charge gate and the first isolation gate are arranged in sequence in the second direction; an equalization gate arranged on the first active layer and extending in the first direction, and the first pre-charge gate, the first isolation gate and the equalization gate are arranged in sequence in the second direction; The second processing structure layout further includes: a second pre-charge gate and a third pre-charge gate arranged on the second active layer and extending in the first direction, and the second pre-charge gate, the second isolation gate and the third pre-charge gate are arranged in sequence in the second direction; or, The first processing structure layout further includes: a first pre-charge gate and a third pre-charge gate arranged on the first active layer and extending in the first direction, and the first pre-charge gate, the first isolation gate and the third pre-charge gate are arranged in sequence in the second direction; An equalization gate arranged on the first active layer and extending in the first direction, and the first pre-charge gate, the first isolation gate, the equalization gate and the third pre-charge gate are arranged in sequence in the second direction; The second processing structure layout further includes: a second pre-charge gate arranged on the second active layer and extending in the first direction, and the second pre-charge gate and the second isolation gate are arranged in sequence in the second direction.

2. The readout circuit architecture according to claim 1, characterized in that, In the first direction, the first active layers for electrically connecting a preset voltage are interconnected.

3. The readout circuit architecture according to claim 1, characterized in that, In the first direction, the second active layers for electrically connecting a preset voltage are interconnected.

4. The readout circuit architecture according to claim 1, characterized in that, In the second direction, the first processing structure layout, the first NMOS layout, the first PMOS layout, the second PMOS layout, the second NMOS layout and the second processing structure layout are arranged in sequence.

5. The readout circuit architecture according to claim 1, characterized in that, In the second direction, the layout of the first processing structure, the layout of the first PMOS, the layout of the first NMOS, the layout of the second NMOS, the layout of the second PMOS, and the layout of the second processing structure are arranged in sequence.

6. The readout circuit architecture according to claim 1, characterized in that, In the second direction, the layout of the first NMOS, the layout of the first processing structure, the layout of the first PMOS, the layout of the second PMOS, the layout of the second processing structure, and the layout of the second NMOS are arranged in sequence.

7. The readout circuit architecture according to claim 1, characterized in that, In the second direction, the layout of the first PMOS, the layout of the first processing structure, the layout of the first NMOS, the layout of the second NMOS, the layout of the second processing structure, and the layout of the second PMOS are arranged in sequence.

8. The readout circuit architecture according to claim 1, characterized in that, In the second direction, the layout of the first PMOS, the layout of the first NMOS, the first processing structure, the second processing structure, the layout of the second NMOS, and the layout of the second PMOS are arranged in sequence.

9. The readout circuit architecture according to claim 1, characterized in that, In the second direction, the layout of the first NMOS, the layout of the first PMOS, the first processing structure, the second processing structure, the layout of the second PMOS, and the layout of the second NMOS are arranged in sequence.

10. The readout circuit architecture according to claim 8 or 9, characterized in that, The first active layer and the second active layer are connected.

11. The readout circuit architecture according to claim 1, characterized in that, The first direction and the second direction are perpendicular to each other.

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