Storage Circuit and Memory

Abstract

Embodiments of the present application relate to the field of semiconductors, and provide a storage circuit and a memory. The storage circuit may at least include: a plurality of storage blocks, each of the storage blocks including a first storage sub-block, a second storage sub-block, and a third storage sub-block arranged in sequence. The second storage sub-block includes a first storage portion and a second storage portion. The first storage sub-block and the first storage portion are used to store high-order bytes, and the second storage portion and the third storage sub-block are used to store low-order bytes. In the arrangement direction of the storage sub-blocks, the block selection addresses of different storage portions arranged side by side are different. Embodiments of the present application are beneficial to improving the integration degree and capacity of the storage circuit without changing the external dimensions.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductors, and particularly to a storage circuit and a memory. Background Art

[0002] DRAM (Dynamic Random Access Memory) is an essential component in most electronic systems as a high-speed and large-capacity data storage medium. The smallest storage unit in DRAM consists of a capacitor and a transistor. The operation mechanism of DRAM is divided into Read and Write. During the read operation, the bit line (BL) is first charged to half of the operating voltage (VDD / 2), and then the transistor is turned on through the word line (WL), causing a charge sharing phenomenon between the capacitor and the bit line. If the internal stored value of the capacitor is 1, the voltage of the bit line will be raised above half of the operating voltage due to charge sharing. If the internal stored value of the capacitor is 0, the voltage of the bit line will be pulled below half of the operating voltage. After obtaining the voltage of the bit line, it needs to be amplified by an amplifier to determine the internal stored value of the capacitor. During the write operation, the transistor is controlled to turn on through the word line. If a 1 needs to be written, the voltage of the bit line is raised to the operating voltage to store the corresponding charge in the capacitor. If a 0 needs to be written, the voltage of the bit line is lowered to a low level to discharge the charge in the capacitor. Summary of the Invention

[0003] The embodiments of the present application provide a storage circuit and a memory, which are at least beneficial to improving the integration and capacity of the storage circuit without changing the external dimensions.

[0004] According to some embodiments of the present application, on the one hand, the embodiments of the present application provide a storage circuit, including: a plurality of storage blocks, each of the storage blocks includes a first storage sub-block, a second storage sub-block, and a third storage sub-block arranged in sequence. The second storage sub-block includes a first storage part and a second storage part. The first storage sub-block and the first storage part are used to store high-order bytes, and the second storage part and the third storage sub-block are used to store low-order bytes. In the arrangement direction of the storage sub-blocks, the block selection addresses of different storage parts arranged side by side are different.

[0005] In addition, the number of storage segments in the first storage sub-block is the same as the number of storage segments in the third storage sub-block, and the number of storage segments in the first storage part is the same as the number of storage segments in the second storage part.

[0006] In addition, the sum of the number of storage segments in the first storage part and the second storage part is equal to the number of storage segments in the first storage sub-block.

[0007] In addition, the memory segment storing the high-order byte and the memory segment storing the low-order byte include the same number of word lines.

[0008] In addition, the first memory sub-block includes a third memory portion and a fourth memory portion, the third memory sub-block includes a fifth memory portion and a sixth memory portion, the third memory portion, the first memory portion, and the fifth memory portion are arranged side by side, the fourth memory portion, the second memory portion, and the sixth memory portion are arranged side by side, the third memory portion and the first memory portion include the same number of word lines, and the second memory portion and the sixth memory portion include the same number of word lines.

[0009] In addition, the memory circuit includes: a first row decoder and a second row decoder, the first row decoder is located between the third memory portion and the first memory portion, the second row decoder is located between the fourth memory portion and the second memory portion, the first row decoder is configured to activate the word lines of the third memory portion, and the second row decoder is configured to activate the word lines of the fourth memory portion and the second memory portion.

[0010] In addition, the memory circuit further includes: a first switch circuit, a second switch circuit, and a third switch circuit, the first switch circuit is connected in series between the first row decoder and the third memory portion, the second switch circuit is connected in series between the second row decoder and the fourth memory portion, the third switch circuit is connected in series between the second row decoder and the second memory portion, the first switch circuit and the second switch circuit are configured to receive a first flag signal and conduct, the third switch circuit is configured to receive a second flag signal and conduct, the first flag signal indicates reading the high-order byte, and the second flag signal indicates reading the low-order byte.

[0011] In addition, the memory circuit further includes: a sense amplifier configured to amplify the read signal of the bit line to form a first amplified signal, the sense amplifier includes a first sense amplifier, a second sense amplifier, a third sense amplifier, and a fourth sense amplifier, the first sense amplifier is configured to amplify the read signal of the bit line in the first memory portion, the second sense amplifier is configured to amplify the read signal of the bit line in the second memory portion, the third sense amplifier is configured to amplify the read signal of the bit line in the third memory portion, and the fourth sense amplifier is configured to amplify the read signal of the bit line in the fourth memory portion; a first control unit and a second control unit, the first control unit is located between the first sense amplifier and the third sense amplifier, the second control unit is located between the second sense amplifier and the fourth sense amplifier, the first control unit is configured to control the third sense amplifier, and the second control unit is configured to control the fourth sense amplifier and the second sense amplifier.

[0012] In addition, the storage circuit further includes: a fourth switch circuit, a fifth switch circuit, and a sixth switch circuit. The fourth switch circuit is connected to the first control unit and the third sense amplifier. The fifth switch circuit is connected to the second control unit and the fourth sense amplifier. The sixth switch circuit is connected to the second control unit and the second sense amplifier. The fifth switch circuit and the sixth switch circuit are configured to receive a first flag signal and turn on. The fourth switch circuit is configured to receive a second flag signal and turn on. The first flag signal indicates reading a high-order byte, and the second flag signal indicates reading a low-order byte.

[0013] In addition, both the first control unit and the second control unit are located between the first storage sub-block and the second storage sub-block.

[0014] In addition, the storage circuit further includes: a third row decoder and a fourth row decoder. The third row decoder is located between the first storage unit and the fifth storage unit. The fourth row decoder is located between the second storage unit and the sixth storage unit. The third row decoder is configured to activate word lines in the first storage unit and the fifth storage unit. The fourth row decoder is configured to activate word lines in the sixth storage unit.

[0015] In addition, the storage circuit further includes: local input / output lines, a main amplifier, and global input / output lines. The local input / output lines are configured to transmit the readout signal amplified by the sense amplifier, denoted as a first amplified signal. The main amplifier is configured to receive and amplify the first amplified signal to obtain a second amplified signal. The main amplifier is further configured to transmit the second amplified signal to the global input / output lines.

[0016] In addition, the local input / output lines include a first local input / output line and a third local input / output line. The first local input / output line is connected to the first storage sub-block. The third local input / output line is connected to the third storage sub-block. The global input / output lines include a high-order global input / output line and a low-order global input / output line. Further included is: a seventh switch circuit configured to connect the first local input / output line and the high-order global input / output line and to receive the first flag signal and turn on, where the first flag signal indicates reading a high-order byte; an eighth switch circuit configured to connect the third local input / output line and the low-order global input / output line and to receive the second flag signal and turn on, where the second flag signal indicates reading a low-order byte.

[0017] In addition, the local input / output line further includes a second local input / output line, which is connected to the second storage sub-block; it further includes: a selector, one end of which is connected to the second local input / output line, and is configured to receive the first flag signal or the second flag signal. If the first flag signal is received, the second local input / output line is connected to the high-order global input / output line. If the second flag signal is received, the second local input / output line is connected to the low-order global input / output line.

[0018] According to some embodiments of the present application, on the other hand, an embodiment of the present application further provides a memory, including the above storage circuit.

[0019] The technical solutions provided by the embodiments of the present application have at least the following advantages:

[0020] In the above technical solution, three storage sub-blocks are arranged side by side. The storage sub-block in the middle position can share the same row decoder with the adjacent storage sub-blocks, without introducing an additional row decoder, which is beneficial to improving the capacity of the storage block with a smaller circuit area without increasing the number of storage segments in the storage sub-block. In addition, the second storage sub-block in the middle position is used to store high-order bytes and low-order bytes, and the storage sub-blocks on both sides are used to store high-order bytes or low-order bytes. In this way, the storage segments for storing high-order bytes and the storage segments for storing low-order bytes can share the same row decoder, avoiding the situation where the shared row decoder activates the wrong word line, which is beneficial to improving the reading accuracy of the storage circuit. In addition, in the arrangement direction of the storage sub-blocks, the block selection addresses of different storage parts arranged side by side are different, which is beneficial to further avoiding the situation where the shared row decoder activates the wrong word line. Description of the Drawings

[0021] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplary illustrations do not limit the embodiments. Unless otherwise stated, the drawings in the figures do not constitute a proportional limitation.

[0022] Figures 1 to 4 It is a schematic structural diagram of the storage circuit provided by the embodiment of the present application. Detailed Embodiments

[0023] The following will elaborate on each embodiment of the present application in conjunction with the drawings. However, those of ordinary skill in the art can understand that in each embodiment of the present application, many technical details are proposed for the convenience of readers to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed by the present application can still be implemented.

[0024] Figures 1 to 4 It is a schematic structural diagram of the storage circuit provided by the embodiment of the present application.

[0025] Reference Figures 1 to 2 Figures 1 to 2 , the storage circuit includes: a plurality of storage blocks 10, each storage block 10 includes a first storage sub-block 11, a second storage sub-block 12, and a third storage sub-block 13 arranged in sequence. The second storage sub-block 12 includes a first storage portion 121 and a second storage portion 122. The first storage sub-block 11 and the first storage portion 121 are used to store high-order bytes, and the second storage portion 122 and the third storage sub-block 13 are used to store low-order bytes. In the arrangement direction of the storage sub-blocks, the block selection addresses of different storage portions arranged side by side are different.

[0026] Hereinafter, embodiments of the present application will be described in more detail with reference to the accompanying drawings.

[0027] Reference Figure 1 Figure 1 , the storage circuit may include a plurality of storage blocks 10. As the capacity of the storage circuit changes, the capacity, quantity, and arrangement of the storage blocks 10 will also change accordingly. Taking the capacity of the storage circuit as 16G and the capacity of each storage block 10 as 1G as an example, the storage circuit includes 16 storage blocks 10 (BK0~BK15), and the arrangement of the storage blocks 10 is 4×4. In addition, each storage block has a corresponding row decoder (not shown) and a column decoder YDEC. The row decoder is used to receive the row address signal and activate the corresponding word line, and the column decoder is used to obtain the readout signal of the bit line at a specific column address. The readout signal is amplified by the sense amplifier and then input into the local input / output line.

[0028] It should be noted that the storage circuit structure provided by the embodiments of the present application is applicable not only to capacities of 16G and below, but also to capacities above 16G. Among them, adjacent storage blocks 10 share the same peripheral circuit area 14. The peripheral circuit area 14 may include a decoding circuit, and the decoding circuit is connected to the word line driver. The word line driver is used to drive the word lines in the storage block 10. In the case of a 4×4 arrangement, two peripheral circuit areas 14 are provided in each row; in addition, the peripheral circuit area 14 and the column decoder YEDC are located on different sides of the storage block 10.

[0029] In addition, the storage circuit further includes a cross-point area circuit XP located between four storage blocks 10 adjacent to each other (such as BK0, BK1, BK4, and BK5). Structures such as a pull-up drive circuit, a local equalization circuit, an input / output equalization circuit, a pre-charge circuit, and an equalization drive circuit can be provided in the cross-point area circuit XP. The pull-up drive circuit is used to provide an operating voltage for the first electrode line to activate the sense amplifier; the local equalization circuit is connected in series between the first electrode line and the second electrode line and is used to connect or disconnect the first electrode line and the second electrode line. If the first electrode line and the second electrode line are connected, the sense amplifier cannot be activated; the input / output equalization circuit and the pre-charge circuit are connected in series between the bit line pairs. The pre-charge circuit is used to raise the voltage of the bit line pairs to half of the operating voltage, and the input / output equalization circuit is used to share the charge of the bit line pairs. The equalization drive circuit is used to activate the input / output equalization circuit and the pre-charge circuit.

[0030] In some embodiments, the number of storage segments in the first storage sub-block 11 is the same as the number of storage segments in the third storage sub-block 13, and the number of storage segments in the first storage unit 121 is the same as the number of storage segments in the second storage unit 122. In this way, it is beneficial to make the number of storage segments storing high-order bytes equal to the number of storage segments storing low-order bytes, ensure that the storage block can effectively store high-order bytes and low-order bytes with the same number of bits, avoid redundancy in the storage segments storing high-order bytes or low-order bytes, and improve the utilization rate of the storage block.

[0031] Taking Figure 2 the illustrated embodiment as an example, the first storage sub-block 11 includes 32 storage segments (SEG0U to SEG31U corresponding to 1U to 32U), where "U" indicates that the storage segment stores high-order bytes. The third storage sub-block 13 also includes 32 storage segments (SEG16L to SEG47L corresponding to 17L to 48L), where "L" indicates that the storage segment stores low-order bytes; correspondingly, the first storage unit 121 includes 16 storage segments (SEG0L to SEG15L corresponding to 1L to 16L), and the second storage unit 122 also includes 16 storage segments (SEG32U to SEG47U corresponding to 33U to 48U), where "U" indicates that the storage segment stores high-order bytes. It should be noted that as the capacity of the storage circuit and the storage block changes, the number of storage segments included in each storage sub-block will also change. For example, if the capacity of each storage block doubles, the number of storage segments included in each storage sub-block doubles.

[0032] In addition, when the number of high-order byte storage segments is the same as that of low-order byte storage segments, if the number of word lines included in each storage segment is the same, the high-order byte storage segment and the low-order byte storage segment include the same number of word lines. It should be noted that in different memories, the number of storage units included in the storage segment can be different. In some embodiments, the sum of the number of storage segments of the first storage unit 121 and the second storage unit 122 is equal to the number of storage segments of the first storage sub-block 11. That is to say, the number of storage segments of the first storage sub-block 11, the second storage sub-block 12, and the third storage sub-block 13 is the same.

[0033] As Figure 2 shown, the first storage sub-block 11, the second storage sub-block 12, and the third storage sub-block 13 all include 48 storage segments; in some other embodiments, the sum of the number of storage segments of the first storage unit 121 and the second storage unit 122 can also be less than the number of storage segments of the first storage sub-block 11. In this way, all the storage segments in the second storage sub-block 12 can also share the row decoder with the first storage sub-block 11 or the third storage sub-block 13.

[0034] In some embodiments, the logical start address of the storage segments in the first storage sub-block 11, the start logical address of the storage segments in the second storage sub-block 12, and the start logical address of the third storage sub-block 13 are sequentially postponed. Among them, the start logical address of the storage segments in the second storage unit 122 is later than the start logical address of the storage segments in the first storage unit 121. Since the physical address of the storage unit in the storage segment = the start address of the segment where it is located + the offset within the segment, the physical address of the storage unit in the second storage unit 122 is later than the physical address of the storage unit in the first storage unit 121. The physical addresses of the storage units in the first storage sub-block 11 and the storage units in the second storage unit 122 are not continuous. Correspondingly, the physical addresses of the storage units in the first storage unit 121 and the storage units in the third storage sub-block 13 are not continuous.

[0035] In some embodiments, the first storage sub-block 11 includes a third storage unit 111 and a fourth storage unit 112, the third storage sub-block 13 includes a fifth storage unit 131 and a sixth storage unit 132. The third storage unit 111, the first storage unit 121, and the fifth storage unit 131 are arranged side by side. Among them, the fourth storage unit 112, the second storage unit 122, and the sixth storage unit 132 are arranged side by side. Among them, the first storage unit 121 and the third storage unit 111 include the same number of word lines, and the second storage unit 122 and the sixth storage unit 132 include the same number of word lines. In this way, it is beneficial to enable the first storage unit 121 and the second storage unit 122 to share the same row decoder with the storage units in the adjacent storage sub-blocks.

[0036] Further, the number of word lines in the first storage unit 121 is equal to the number of word lines in the second storage unit 122, and the number of word lines in the first storage unit 121, the third storage unit 111, and the fifth storage unit 131 is the same, and the number of word lines in the second storage unit 122, the fourth storage unit 112, and the sixth storage unit 132 is the same.

[0037] In some embodiments, referring to Figure 3 , the storage circuit includes: a first row decoder 21 and a second row decoder 22. The first row decoder 21 is located between the third storage unit 111 and the first storage unit 121, and the second row decoder 22 is located between the fourth storage unit 112 and the second storage unit 122. The first row decoder 21 is configured to activate the word lines in the third storage unit 111 and the first storage unit 121, and the second row decoder 22 is configured to activate the word lines in the fourth storage unit 112. Using the same row decoder to activate the word lines in different storage sub-blocks is beneficial to saving circuit area and simplifying the storage circuit; in addition, setting the shared row decoder between the corresponding two storage units is beneficial to shortening the circuit connection distance, avoiding the relatively long RC delay caused by the large wire resistance, and improving the reading speed of the storage circuit; at the same time, the two storage units provided with the shared row decoder are respectively used to store the high-order byte and the low-order byte, which is beneficial to avoiding the row decoder from activating the wrong word line after receiving the row address.

[0038] It should be noted that the logical address of the storage segment is composed of the most significant bit and the block selection address, and the most significant bit is the leftmost bit RA of the row address <n>, the block selection address is the other bits RA of the row address <n-1:0>, reference Figure 2 , the Most Significant Bit (MSB) of the memory segment storing the high-order byte is 0, the Most Significant Bit of the memory segment storing the low-order byte is 1, and the block selection addresses of different memory blocks storing the same type of byte (high-order byte or low-order byte) are different, such as SEG0~SEG47, and the block selection addresses of different memory blocks storing different types of bytes may be the same, such as SEG0~SEG47.

[0039] In some embodiments, the memory circuit further includes: a first switch circuit 31, a second switch circuit 32, and a third switch circuit 33. The first switch circuit 31 is connected to the first row decoder 21 and the third memory unit 111, the second switch circuit 32 is connected to the second row decoder 22 and the fourth memory unit 112, and the third switch circuit 33 is connected to the first row decoder 21 and the first memory unit 121. The first switch circuit 31 and the second switch circuit 32 are configured to receive the first flag signal 41 and turn on, and the third switch circuit is configured to receive the second flag signal 42 and turn on. The first flag signal 41 indicates reading the high-order byte, and the second flag signal 42 indicates reading the low-order byte. Connecting the switch circuits in series between the row decoder and the memory unit to turn on the row decoder and the memory unit storing the corresponding byte when reading the corresponding byte is beneficial to further avoid the row decoder from activating the wrong word line and improve the accuracy of data reading of the memory circuit.

[0040] In some embodiments, the memory circuit further includes: a third row decoder 23 and a fourth row decoder 24. The third row decoder 23 is located between the fifth memory unit 131 and the first memory unit 121, and the fourth row decoder 24 is located between the sixth memory unit 132 and the second memory unit 122. The third row decoder 23 is configured to activate the word lines of the fifth memory unit 131, and the fourth row decoder 24 is configured to activate the word lines in the second memory unit 122 and the sixth memory unit 132. Among them, the switch circuit connected in series between the third row decoder 23 and the fifth memory unit 131 turns on when receiving the second flag signal 42, the switch circuit connected in series between the fourth row decoder 24 and the sixth memory unit 132 turns on when receiving the second flag signal 42, and the switch circuit connected in series between the fourth row decoder 24 and the second memory unit 122 turns on when receiving the first flag signal 41. Similar to the first row decoder 21 and the corresponding switch circuit, the setting of the fourth row decoder 24 is beneficial to simplify the circuit and improve the reading speed of the memory circuit; in addition, the first row decoder 21 and the fourth row decoder 24 with similar connection relationships and functions are set at the same time.

[0041] Accordingly, the storage circuit further includes: a first sense amplifier 141, a second sense amplifier 142, a third sense amplifier 43, and a fourth sense amplifier 44. The first sense amplifier 141 is configured to amplify the read signal of the bit line in the first storage unit 121. The second sense amplifier 142 is configured to amplify the read signal of the bit line in the second storage unit 122. The third sense amplifier 43 is configured to amplify the read signal of the bit line in the third storage unit 111. The fourth sense amplifier 44 is configured to amplify the read signal of the bit line in the fourth storage unit 112. The first control unit 51 and the second control unit 52 are provided. The first control unit 51 is located between the first sense amplifier 141 and the third sense amplifier 43. The second control unit 52 is located between the second sense amplifier 142 and the fourth sense amplifier 44. The first control unit 51 is configured to control the first sense amplifier 141 and the third sense amplifier. The second control unit 52 is configured to control the fourth sense amplifier 44. Similar to the setting of the first row decoder 21, the first control unit 51 is provided to be connected to and control two adjacent sense amplifiers, which is beneficial to simplifying the circuit and shortening the RC delay. At the same time, the connection relationship between the first control unit 51 and the first row decoder 21 and their respective adjacent components is similar, which is beneficial to simplifying the layout design of the storage circuit.

[0042] Among them, both the first row decoder 21 and the first control unit 51 are located between the first storage unit 121 and the third storage unit 111 and their corresponding sense amplifiers. Both the first control unit 51 and the second control unit 52 are located between the first storage sub-block 11 and the second storage sub-block 12.

[0043] In some embodiments, the storage circuit further includes: a fourth switch circuit 34, a fifth switch circuit 35, and a sixth switch circuit 36. The fourth switch circuit 34 is connected to the first control unit 51 and the first sense amplifier 141. The fifth switch circuit 35 is connected to the first control unit 51 and the third sense amplifier 43. The sixth switch circuit 36 is connected to the second control unit 52 and the fourth sense amplifier 44. The fifth switch circuit 35 and the sixth switch circuit 36 are configured to receive the first flag signal 41 and conduct. The fourth switch circuit 34 is configured to receive the second flag signal 42 and conduct. The first flag signal 41 is used to represent reading the high-order byte. The second flag signal 42 represents reading the low-order byte. Similarly to the setting of the above switch circuit, by setting the switch circuit, the first control unit 51 is connected to the corresponding sense amplifier at the appropriate time, which is beneficial to ensuring that the first control unit 51 is ready to control the corresponding sense amplifier, and then accurately amplifying the tiny read signal on the corresponding bit line, ensuring the accuracy of data reading of the storage circuit.

[0044] In some embodiments, the storage circuit further includes: a third row decoder 23 and a fourth row decoder 24. The third row decoder 23 is located between the first storage unit 121 and the fifth storage unit 131, and the fourth row decoder 24 is located between the second storage unit 122 and the sixth storage unit 132. The third row decoder 23 is configured to activate the word lines in the fifth storage unit 131, and the fourth row decoder 24 is configured to activate the word lines in the second storage unit 122 and the sixth storage unit 132.

[0045] Correspondingly, the storage circuit further includes a fifth sense amplifier 45 and a sixth sense amplifier 46. The fifth sense amplifier 45 is configured to amplify the read signal of the bit line in the fifth storage unit 131, and the sixth sense amplifier 46 is configured to amplify the read signal of the bit line in the sixth storage unit 132. In addition, the storage circuit further includes a third control unit 53 and a fourth control unit 54. The third control unit 53 is connected to the fifth sense amplifier 45 through a corresponding switch circuit to adjust it when the storage circuit reads the low byte. The fourth control unit 54 is respectively connected to the second sense amplifier 142 and the sixth sense amplifier 46 through different switch circuits to adjust the second sense amplifier 142 when reading the high byte and to adjust the sixth sense amplifier 46 when reading the low byte.

[0046] In some embodiments, referring to Figure 4 , the storage circuit further includes: a local input / output line LIO, a main amplifier 60, and a global input / output line GIO. The local input / output line LIO is configured to transmit the read signal amplified by the sense amplifier. The main amplifier 60 is configured to receive and amplify the read signal output by the local input / output line LIO, and transmit the read signal amplified again to the global input / output line GIO.

[0047] It can be understood that each local input / output line LIO corresponds to a bit line. The number of bit lines in the storage block 10 is the same as the number of columns of the storage array in the storage block 10. That is to say, the more columns the storage array has, the more bit lines there are in the storage block 10. Similarly, the number of bit lines in each storage sub-block is the same as the number of columns of the storage array in that storage sub-block. In addition, each local input / output line LIO corresponds to a main amplifier 60. The main amplifier 60 is configured to receive and amplify the read signal output by the corresponding local input / output line LIO, and is connected to the corresponding global input / output line GIO according to the byte type stored in the storage sub-block.

[0048] In multi-byte data, bytes are divided into high-order bytes and low-order bytes. To ensure the accuracy of data reading, generally, high-order bytes are transmitted by high-order global input / output lines UGIO, and low-order bytes are transmitted by low-order global input / output lines LGIO. In some embodiments, each of the first storage sub-block 11, the second storage sub-block 12, and the third storage sub-block 13 contains 128 bit lines. The global input / output line GIO is used to transmit 16 bytes of data, where the first 8 bytes are high-order bytes and the last 8 bytes are low-order bytes. Since each byte is 8 bits, the global input / output line GIO is used to transmit 128 bits of data.

[0049] Among them, the local input / output line LIO includes a first local input / output line LIO1 and a third local input / output line LIO3. The first local input / output line LIO1 is connected to the first storage sub-block 11, and the third local input / output line LIO3 is connected to the third storage sub-block 13. The global input / output line GIO includes a high-order global input / output line UGIO and a low-order global input / output line LGIO. In addition, the storage circuit further includes: a seventh switching circuit 37, configured to connect the first local input / output line LIO1 and the high-order global input / output line UGIO, and to receive the first flag signal 41 and conduct; an eighth switching circuit 38, configured to connect the third local input / output line LIO3 and the low-order global input / output line LGIO, and to receive the second flag signal 42 and conduct.

[0050] In addition, the local input / output line LIO further includes a second local input / output line LIO2, and the second local input / output line LIO2 is connected to the second storage sub-block 12. The storage circuit further includes: a selector 39, one end of which is connected to the second local input / output line LIO2, and is configured to receive the first flag signal 41 or the second flag signal 42. If the first flag signal 41 is received, it connects the second local input / output line LIO and the high-order global input / output line UGIO; if the second flag signal 42 is received, it connects the second local input / output line LIO and the low-order global input / output line LGIO.

[0051] In some embodiments, a main input / output line and a cross-point area circuit XP are also connected in series between the local input / output line LIO and the main amplifier 60. After the read signal of the bit line is amplified by the sense amplifier and activated by the column selection signal, it is sequentially transmitted to the local input / output line LIO, the cross-point area circuit, the main input / output line, and the main amplifier 60. After the main amplifier 60 amplifies the read signal of the bit line for the second time, it is transmitted to the data segment via the receiving amplifier, the multiplexer, and the output buffer. Among them, the receiving amplifier is activated by the corresponding start signal to amplify the tiny signal generated on the global input / output line; the multiplexer is a parallel-to-serial conversion circuit that transmits multiple stored information read from the memory array to the output buffer in time series, and the output order is controlled by the corresponding data output start signal group.

[0052] Correspondingly, in the write operation, the data signal to be stored is input from the data terminal and is transmitted to the input buffer together with the data input start signal. The data in the input buffer is transmitted to the word line driver via the demultiplexer, the global write driver, and the global input / output line GIO. Correspondingly, the demultiplexer is a circuit that performs serial-to-parallel conversion on the data information continuously input in time series. The correspondence between the input data signal and the global input / output line GIO is controlled by the data input start signal to make it consistent with the output order in the above read operation.

[0053] Specifically, the selector 39 may include a first switch 391 and a second switch 392. One ends of the first switch 391 and the second switch 392 are both connected to the main amplifier 60 for receiving the re-amplified read signal. The other end of the first switch 391 is connected to the upper global input / output line UGIO for receiving the first flag 41 and conducting. The other end of the second switch 392 is connected to the lower input / output line LGIO for receiving the flag signal 42 and conducting.

[0054] In the embodiment of the present application, three storage sub-blocks are arranged side by side. The storage sub-block in the middle position can share the same row decoder with the adjacent storage sub-blocks, without introducing an additional row decoder, which is beneficial to improving the capacity of the storage block with a small circuit area without increasing the number of storage segments in the storage sub-block; in addition, the second storage sub-block in the middle position is used to store high-order bytes and low-order bytes, and the storage sub-blocks on both sides are used to store high-order bytes or low-order bytes. In this way, the storage segments storing high-order bytes and the storage segments storing low-order bytes can share the same row decoder, avoiding the shared row decoder from activating the wrong word line, which is beneficial to improving the reading accuracy of the storage circuit.

[0055] The embodiment of the present application further provides a memory, including the above storage circuit. The memory including the above storage circuit can have a smaller volume and a larger capacity, ensuring the effective progress of package testing.

[0056] Those of ordinary skill in the art can understand that the above embodiments are specific embodiments for implementing the present application. In actual applications, various changes can be made in form and details without departing from the spirit and scope of the present application. Any person skilled in the art can make their respective changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application should be subject to the scope defined by the claims. < / n>

Claims

1. A storage circuit, characterized in that, Comprising: A plurality of memory blocks, each of the memory blocks including a first memory sub-block, a second memory sub-block, and a third memory sub-block arranged in sequence. The second memory sub-block includes a first memory portion and a second memory portion. The first memory sub-block and the first memory portion are used for storing high-order bytes, and the second memory portion and the third memory sub-block are used for storing low-order bytes. In the arrangement direction of the memory sub-blocks, the block selection addresses of different memory portions arranged side by side are different.

2. The storage circuit according to claim 1, characterized in that, The number of storage segments in the first memory sub-block is the same as the number of storage segments in the third memory sub-block, and the number of storage segments in the first memory portion is the same as the number of storage segments in the second memory portion.

3. The storage circuit according to claim 2, characterized in that, The sum of the number of storage segments in the first memory portion and the second memory portion is equal to the number of storage segments in the first memory sub-block.

4. The storage circuit according to claim 2, characterized in that, The storage segments storing the high-order bytes and the storage segments storing the low-order bytes include the same number of word lines.

5. The storage circuit according to claim 1, characterized in that, The first memory sub-block includes a third memory portion and a fourth memory portion, and the third memory sub-block includes a fifth memory portion and a sixth memory portion. The third memory portion, the first memory portion, and the fifth memory portion are arranged side by side, and the fourth memory portion, the second memory portion, and the sixth memory portion are arranged side by side. The third memory portion and the first memory portion include the same number of word lines, and the second memory portion and the sixth memory portion include the same number of word lines.

6. The storage circuit according to claim 5, characterized in that, Comprising: A first row decoder and a second row decoder. The first row decoder is located between the third memory portion and the first memory portion, and the second row decoder is located between the fourth memory portion and the second memory portion. The first row decoder is used for activating the word lines of the third memory portion, and the second row decoder is used for activating the word lines of the fourth memory portion and the second memory portion.

7. The storage circuit according to claim 6, characterized in that, Further comprising: A first switch circuit, a second switch circuit, and a third switch circuit. The first switch circuit is connected in series between the first row decoder and the third memory portion, the second switch circuit is connected in series between the second row decoder and the fourth memory portion, and the third switch circuit is connected in series between the second row decoder and the second memory portion. The first switch circuit and the second switch circuit are used for receiving a first flag signal and conducting, and the third switch circuit is used for receiving a second flag signal and conducting. The first flag signal indicates reading high-order bytes, and the second flag signal indicates reading low-order bytes.

8. The storage circuit according to claim 5, characterized in that, Further comprising: A sense amplifier for amplifying the read signal of the bit line to form a first amplified signal. The sense amplifier includes a first sense amplifier, a second sense amplifier, a third sense amplifier, and a fourth sense amplifier. The first sense amplifier is used for amplifying the read signal of the bit line in the first memory portion, the second sense amplifier is used for amplifying the read signal of the bit line in the second memory portion, the third sense amplifier is used for amplifying the read signal of the bit line in the third memory portion, and the fourth sense amplifier is used for amplifying the read signal of the bit line in the fourth memory portion; A first control unit and a second control unit, the first control unit being located between the first sense amplifier and the third sense amplifier, the second control unit being located between the second sense amplifier and the fourth sense amplifier, the first control unit being configured to control the third sense amplifier, and the second control unit being configured to control the fourth sense amplifier and the second sense amplifier.

9. The storage circuit according to claim 8, characterized in that, Further comprising: A fourth switch circuit, a fifth switch circuit, and a sixth switch circuit, the fourth switch circuit connecting the first control unit and the third sense amplifier, the fifth switch circuit connecting the second control unit and the fourth sense amplifier, the sixth switch circuit connecting the second control unit and the second sense amplifier, the fifth switch circuit and the sixth switch circuit being configured to receive a first flag signal and turn on, and the fourth switch circuit being configured to receive a second flag signal and turn on, the first flag signal indicating reading a high-order byte, and the second flag signal indicating reading a low-order byte.

10. The storage circuit according to claim 8, characterized in that, Both the first control unit and the second control unit are located between the first memory sub-block and the second memory sub-block.

11. The storage circuit according to claim 5, characterized in that, Comprising: A third row decoder and a fourth row decoder, the third row decoder being located between the first memory unit and the fifth memory unit, the fourth row decoder being located between the second memory unit and the sixth memory unit, the third row decoder being configured to activate word lines in the first memory unit and the fifth memory unit, and the fourth row decoder being configured to activate word lines in the sixth memory unit.

12. The storage circuit according to claim 1, characterized in that, Further comprising: Local input / output lines, a main amplifier, and global input / output lines, the local input / output lines being configured to transmit a readout signal amplified by a sense amplifier, denoted as a first amplified signal, the main amplifier being configured to receive and amplify the first amplified signal to obtain a second amplified signal, and the main amplifier being further configured to transmit the second amplified signal to the global input / output lines.

13. The storage circuit according to claim 12, characterized in that, The local input / output lines include a first local input / output line and a third local input / output line, the first local input / output line being connected to the first memory sub-block, the third local input / output line being connected to the third memory sub-block, the global input / output lines including a high-order global input / output line and a low-order global input / output line; further comprising: A seventh switch circuit, configured to connect the first local input / output line and the high-order global input / output line, and configured to receive a first flag signal and turn on, the first flag signal indicating reading a high-order byte; An eighth switch circuit, configured to connect the third local input / output line and the low-order global input / output line, and configured to receive a second flag signal and turn on, the second flag signal indicating reading a low-order byte.

14. The storage circuit according to claim 13, characterized in that, The local input / output lines further include a second local input / output line, the second local input / output line being connected to the second memory sub-block; further comprising: A selector, one end of which is connected to the second local input / output line, is configured to receive the first flag signal or the second flag signal. If the first flag signal is received, it connects the second local input / output line to the high-order global input / output line; if the second flag signal is received, it connects the second local input / output line to the low-order global input / output line.

15. A memory, characterized in that, Comprising the storage circuit according to any one of claims 1-14.

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