Surface treatment method for gallium oxide-based semiconductor substrate and semiconductor device

Abstract

In a surface treatment method for a gallium oxide-based semiconductor substrate, the surface of the gallium oxide-based semiconductor substrate is planarized by dry etching at a self-bias voltage of 150 V or greater. After the surface of the gallium oxide-based semiconductor substrate is planarized, the surface of the gallium oxide-based semiconductor substrate is cleaned with a chemical solution containing H2SO4 to expose a stepped structure on the surface of the gallium oxide-based semiconductor substrate.

Description

Technical Field

[0001] The present disclosure relates to a surface treatment method for a gallium oxide-based semiconductor substrate and a semiconductor device using the gallium oxide-based semiconductor substrate. Background Art

[0002] W. Li et al., “2.44 kV Ga2O3 vertical trench Schottky barrier diodes with very low reverse leakage current”, IEEE International Electron Devices Meeting Tech. Dig., 2018, pp. 193-196, discloses the device structure of Schottky barrier diodes manufactured using a gallium oxide substrate. Summary of the Invention

[0003] It is necessary to improve device characteristics by suppressing interface states on the surface of a gallium oxide-based semiconductor substrate. For example, when a Schottky junction is formed, when the interface state density increases, the Schottky barrier height ΦB decreases, causing an increase in leakage current.

[0004] A surface treatment method for a gallium oxide-based semiconductor substrate according to a first aspect of the present disclosure includes: flattening the surface of the gallium oxide-based semiconductor substrate by performing dry etching at a self-bias voltage of 150 V or greater; and after flattening the surface of the gallium oxide-based semiconductor substrate, exposing a step terrace structure on the surface of the gallium oxide-based semiconductor substrate by cleaning the surface of the gallium oxide-based semiconductor substrate with a chemical solution containing H2SO4.

[0005] A thin film of an altered layer can be formed on the surface of a semiconductor substrate based on gallium oxide. If there is an area where the altered layer cannot be removed during dry etching, the altered layer acts as a mask and etching does not proceed, resulting in a large surface roughness. The inventors have found that by setting the self-bias voltage of the dry etching to 150V or higher, the altered layer can be properly removed. Therefore, the flatness after etching can be improved. The inventors also found that by cleaning the surface after dry etching with a chemical solution containing H2SO4, a step-step structure can be exposed on the surface. As a result, an ideal surface state with high flatness and no interface layer can be achieved, thereby suppressing the generation of interface states. Therefore, the device characteristics can be improved.

[0006] A semiconductor device according to a second aspect of the present disclosure includes a gallium oxide-based semiconductor substrate and a metal layer disposed on a surface of the gallium oxide-based semiconductor substrate. A stepped structure is exposed on the surface of the gallium oxide-based semiconductor substrate at an interface between the gallium oxide-based semiconductor substrate and the metal layer.

[0007] A semiconductor device according to a third aspect of the present disclosure includes a gallium oxide-based semiconductor substrate, an insulating film disposed on a surface of the gallium oxide-based semiconductor substrate, and an electrode disposed on a surface of the insulating film. A stepped structure is exposed on the surface of the gallium oxide-based semiconductor substrate at an interface between the gallium oxide-based semiconductor substrate and the insulating film. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description made with reference to the accompanying drawings. In the accompanying drawings:

[0009] Figure 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment;

[0010] Figure 2 is a schematic diagram of a dry etching apparatus;

[0011] Figure 3 is a flow chart illustrating a method for manufacturing a semiconductor device;

[0012] Figure 4 is a cross-sectional view near the front surface of the gallium oxide layer before a planarization process is performed;

[0013] Figure 5 is a cross-sectional view near the front surface of the gallium oxide layer after a planarization process;

[0014] Figure 6 is a scanning electron microscope (SEM) observation image of the nanopillars;

[0015] Figure 7 is the correlation graph of antenna power and self-bias voltage;

[0016] Figure 8 is the correlation diagram between bias power and self-bias voltage;

[0017] Figure 9 is an atomic force microscope (AFM) observation image of the front surface of the gallium oxide layer after dry etching; and

[0018] Figure 10 This is an AFM observation image of the front surface of the gallium oxide layer after cleaning. DETAILED DESCRIPTION

[0019] Figure 1 A schematic cross-sectional view of a semiconductor device 1 according to an embodiment is shown. The semiconductor device 1 is a Schottky barrier diode. The semiconductor device 1 includes a semiconductor substrate 10. The semiconductor substrate 10 has a structure in which a gallium oxide layer 12 having n-type conductivity is stacked on a gallium oxide substrate 11 having n-type conductivity. The semiconductor substrate 10 is an example of a semiconductor substrate based on gallium oxide. The gallium oxide layer 12 is a layer epitaxially grown by hydride vapor phase epitaxy (HVPE). The front surfaces of the gallium oxide substrate 11 and the gallium oxide layer 12 are (001) planes. A cathode electrode 21 is provided on the rear surface of the semiconductor substrate 10. The cathode electrode 21 has a structure in which titanium (Ti) and gold (Au) are stacked. An anode electrode 22 is provided on the front surface 12s of the semiconductor substrate 10. The anode electrode 22 is made of nickel (Ni).

[0020] Figure 2 A schematic diagram of a dry etching device 30 used in this embodiment is shown. The dry etching device 30 is an inductively coupled plasma (ICP) etching device. The interior of a chamber 31 is depressurized by a vacuum pump 32. In the chamber 31, a bias electrode 34 and a wafer 35 are accommodated. The bias electrode 34 is connected to a bias radio frequency (RF) power supply 33. An induction coil 37 is provided at the upper portion of the chamber 31. The induction coil 37 is connected to an antenna RF power supply 38. Etching gas is supplied to the chamber 31 via a gas supply pipe 36. In this embodiment, BCl3 and Cl2 are supplied in a switchable manner.

[0021] When antenna power is applied to the induction coil 37, plasma PL is generated directly below the induction coil 37. When bias power is applied to the bias electrode 34, a self-bias voltage Vds, which is a negative direct current (DC) voltage, is generated. A sheath SH is generated between the plasma PL and the wafer 35. The strong electric field generated in the sheath SH can accelerate ions toward the wafer 35.

[0022] The self-bias voltage is the voltage of the sheath SH. In other words, the self-bias voltage is the potential difference between the plasma PL and the wafer 35. The self-bias voltage is determined by various parameters, such as the power of the bias RF power supply 33 and the antenna RF power supply 38, as well as the type of etching gas. The self-bias voltage can be measured in any dry etching equipment. It can also be monitored during etching. Therefore, the self-bias voltage is a general and universal indicator for defining etching conditions.

[0023] Next, we will refer to Figure 3 The flowchart of FIG. 1 describes a surface treatment method of a semiconductor substrate 10 used in the semiconductor device 1. In S0, the semiconductor substrate 10 is set in a chamber 31 of a dry etching apparatus 30.

[0024] In S1 to S3, a planarization process for planarizing the front surface 12s of the semiconductor substrate 10 is performed. The planarization process includes the first to third processes. In the planarization process, dry etching is performed with a self-bias voltage of 150V or greater. Therefore, a flat surface without unevenness can be formed while maintaining the etching rate. Chlorine-containing gas is used for dry etching. In this embodiment, the power of the antenna RF power supply 38 is 800W, the pressure in the chamber 31 is 1Pa, the total flow rate is 30sccm, and the etching time is 10 minutes. Each of the first to third processes will be described below.

[0025] In S1, a first process of dry etching is performed using BCl 3 at a self-bias voltage of 150 V or more. A thin film of a degenerated layer may be formed on the front surface 12s of the semiconductor substrate 10. In the first process, the degenerated layer may be effectively removed by bonding boron atoms to oxygen atoms of gallium oxide.

[0026] In S2, a second dry etching process is performed using Cl2 gas at a self-bias voltage of 150 V or greater. Since the etching gas does not contain boron, bonding between boron atoms and oxygen atoms does not occur. Therefore, although the etching rate is reduced, the processing flatness can be improved.

[0027] In S3, a third dry etching process is performed using BCl3 at a self-bias voltage of 150V or greater. A small amount of silicon atoms is present in chamber 31 and the atmosphere. When silicon atoms adsorb on oxygen adsorption sites in gallium oxide, the resistance of gallium oxide increases. Therefore, by finishing with a boron-containing etching gas, the oxygen adsorption sites can be terminated with boron atoms. This can suppress the adsorption of silicon atoms on oxygen adsorption sites.

[0028] Note that S1 to S3 can be performed continuously by switching the etching gas.

[0029] In S4, the semiconductor substrate 10 on which the planarization process has been performed is taken out of the chamber 31. Then, the front surface 12s of the semiconductor substrate 10 is cleaned with a chemical solution containing sulfuric acid (H2SO4). As a result, a step-step structure (i.e., a flat surface at the atomic level) can be exposed on the front surface 12s of the semiconductor substrate 10. In this embodiment, a sulfuric acid-hydrogen peroxide mixture (SPM) treatment is performed in which sulfuric acid and a hydrogen peroxide solution are mixed.

[0030] If chlorine is present on the front surface 12s of the semiconductor substrate 10, a surface state is formed. In this case, the Schottky barrier height ΦB is reduced, which causes reverse leakage. In this embodiment, the chlorine remaining on the front surface 12s of the semiconductor substrate 10 is removed by the cleaning process in S4. Therefore, the formation of the surface state can be suppressed.

[0031] In S5, a metal layer (anode electrode 22) is formed on the front surface 12s. In this embodiment, a nickel layer is formed. As a result, the Figure 1 The semiconductor device 1 shown in FIG.

[0032] The reason why a self-bias voltage of 150 V or more is required will be explained below. Figure 4 A cross-sectional view near the front surface 12s of the gallium oxide layer 12 before the planarization process (S1 to S3) is performed is shown. A thin film of a modified layer 12a may be formed on the front surface 12s. The modified layer 12a is a layer that has been altered from gallium oxide due to adsorption of various elements and damage during processing. If there is an area where the modified layer 12a cannot be removed during the dry etching of S1 to S3, the remaining modified layer 12a becomes a mask and stops etching. As a result, as shown in FIG. Figure 5 As shown, nanocolumns NC (columnar impurities) are formed at the remaining portion of the altered layer 12a.

[0033] Figure 6 An SEM observation image of the nanocolumns NC is shown. When the nanocolumns NC are formed, the flatness of the front surface 12s is extremely deteriorated.

[0034] Therefore, the present inventors have experimentally determined the range of the self-bias voltage in which the nanocolumns NC are not formed. Figure 7 and Figure 8 The experimental results are shown. Figure 7 The horizontal axis is the antenna power of the antenna RF power supply 38, and the vertical axis is the self-bias voltage. Figure 7 In the experiment, the bias power of the bias RF power supply 33 is fixed at 30W. Figure 8 The horizontal axis is bias power, and the vertical axis is self-bias voltage. Figure 8 In the experiment, the antenna power is fixed at 800W. Figure 7 and Figure 8 In the experiment, BCl3 was used as the etching gas and the total pressure was set to 1Pa.

[0035] exist Figure 7 and Figure 8 The planarization step (S1 to S3) is performed under the conditions shown by the curve. Then, it is confirmed whether nanocolumns NC are generated. Figure 7 and Figure 8 The white circles in the figure represent the conditions under which nanopillar NCs are not formed, and the dotted circles represent the conditions under which nanopillar NCs are formed.

[0036] like Figure 7 As shown in FIG, it can be seen that the self-bias voltage increases with decreasing antenna power, and no nanocolumn NC is formed in the region where the self-bias voltage is 150 V or greater (see region R1). Figure 8As shown, it can be seen that the self-bias voltage increases with the increase of the bias power, and no nanocolumn NC is formed in the region where the self-bias voltage is 150 V or greater (see region R2).

[0037] From the above, the present inventors have found that the altered layer 12a can be appropriately removed by setting the self-bias voltage of the dry etching to 150 V or higher (see Figure 4 and 5 As a result, the formation of nanocolumns NC can be prevented, thereby improving the flatness after etching. Since the flatness of the junction interface between the front surface 12s of the gallium oxide layer 12 and the anode electrode 22 can be increased, the electric field can be suppressed. Therefore, leakage current can be suppressed.

[0038] Figure 9 and Figure 10 An AFM observation image of the front surface 12s of the gallium oxide layer 12 is shown. The plane orientation is the (001) plane. Figure 9 This is an image after dry etching in S3. Figure 10 This is the image after cleaning in S4. Figure 9 and Figure 10 Have the same magnification.

[0039] exist Figure 9 The arithmetic mean roughness Ra of the surface after dry etching is 0.30 nm. Figure 10 The arithmetic mean roughness Ra of the surface after the intermediate cleaning was 0.17 nm. This result shows that the surface roughness can be reduced by the cleaning process.

[0040] exist Figure 9 In , no regularity is observed on the surface. On the other hand, in Figure 10 In the lattice structure, a step-ladder structure is observed. A step-ladder structure is a structure in which ST and step-TE are repeated, ST is a step portion of one or more atoms, and step-TE is flat at the atomic level.

[0041] Based on the above, the present inventors have discovered that by cleaning the front surface 12s of the gallium oxide layer 12 after dry etching with a chemical solution containing H2SO4, a step-and-stair structure can be exposed on the front surface 12s. The surface on which the step-and-stair structure is exposed is in an ideal surface state with extremely high flatness and no interface layer. As a result, the generation of interface states can be suppressed, making it possible to suppress the reduction of the Schottky barrier height ΦB (1.09 eV after dry etching, 1.15 eV after cleaning). Therefore, leakage current can be suppressed.

[0042] Although specific examples of the present disclosure have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in this specification includes various modifications and variations of the above-mentioned specific examples. In addition, the technical elements described in this specification or the drawings may be technically applicable alone or in various combinations, and are not limited to the combinations described in this specification at the time of filing. In addition, the technology shown in this specification or the drawings can achieve multiple objectives simultaneously, and achieving one of these objectives itself has technical applicability.

[0043] (Variant)

[0044] The technology disclosed in this specification can be applied to various device structures, not limited to Schottky barrier diodes. For example, the technology can be applied to a field effect transistor (FET) structure using an insulating film. In this case, the electrode is provided on the front surface 12c of the gallium oxide layer 12 via the insulating film. At the interface between the gallium oxide layer 12 and the insulating film, the following structure can be achieved, in which a stepped structure is exposed on the front surface 12c of the gallium oxide layer 12. As a result, the generation of interface states can be suppressed, thereby suppressing leakage current and on-resistance. Therefore, the device characteristics can be improved.

[0045] The etching gas used in S1 and S3 is not limited to BCl3. Any gas can be used as long as it contains boron and chlorine. The etching gas used in S2 is not limited to Cl2. Any gas type can be used as long as it contains chlorine and does not contain boron.

[0046] The step structure of the gallium oxide layer 12 may be varied. The technology of this specification is applicable to both the α-type and the β-type.

[0047] The gallium oxide layer 12 may be a mixed crystal gallium oxide containing at least one of indium, aluminum, and zinc. In other words, the gallium oxide layer 12 may be a mixed crystal gallium oxide containing at least indium, a mixed crystal gallium oxide containing at least aluminum, or a mixed crystal gallium oxide containing at least zinc. Examples of mixed crystal gallium oxide include (InAlGa)2O3, (AlGa)2O3, InGaO3(ZnO), and the like.

Claims

1. A surface treatment method for a gallium oxide-based semiconductor substrate, comprising: planarizing the surface of the gallium oxide-based semiconductor substrate by dry etching at a self-bias voltage of 150 V or greater; and After planarizing the surface of the gallium oxide-based semiconductor substrate, the step-and-stair structure on the surface of the gallium oxide-based semiconductor substrate is exposed by cleaning the surface of the gallium oxide-based semiconductor substrate with a chemical solution containing H 2 SO 4 .

2. The surface treatment method according to claim 1, wherein The planarizing includes performing the dry etching using a chlorine-containing gas.

3. The surface treatment method according to claim 2, wherein The planarization includes: A first step of dry etching using a gas containing boron and chlorine; After the first step, performing a second step of dry etching using a gas containing chlorine and not containing boron; and After the second step, a third step of dry etching is performed using a gas containing boron and chlorine.

4. The surface treatment method according to claim 3, wherein The first step uses a gas containing BCl3, The second step uses a gas containing Cl2, and The third step uses a gas containing BCl 3 .

5. The surface treatment method according to any one of claims 1 to 4, wherein The gallium oxide-based semiconductor substrate is a mixed crystal gallium oxide substrate containing at least one of indium, aluminum, and zinc.

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