Method of forming a semiconductor structure and semiconductor structure

Abstract

The present disclosure provides a semiconductor structure forming method and a semiconductor structure. The semiconductor structure forming method comprises: providing a plurality of first core particles, a through silicon via structure is arranged in each first core particle, the plurality of first core particles are vertically stacked to form a core particle stack structure, part of the through silicon via structure forms a first shielding structure, and the first shielding structure is arranged at an edge region of the core particle stack structure; and forming a second shielding structure, the second shielding structure surrounds the core particle stack structure along a circumferential direction of the core particle stack structure, and the second shielding structure covers a sidewall of each first core particle in the core particle stack structure. In the semiconductor structure forming method of the present disclosure, the first shielding structure is formed in the core particle stack structure, and the second shielding structure is formed at a circumferential edge of the core particle stack structure, thereby providing a good shielding effect for the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for forming a semiconductor structure and a semiconductor structure. Background Technology

[0002] As Dynamic Random Access Memory (DRAM) becomes smaller, in order to further improve the integration of integrated circuits (ICs), through-silicon via (TSV) structures are formed on multiple chips, and electrical interconnection between different chips is achieved through subsequent redistribution layers (RDLs) to stack multiple chips.

[0003] Stacked chips are often used in high-speed broadband communications, but the wide communication bandwidth may cause interference to the signal transmission of stacked chips. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] This disclosure provides a method for forming a semiconductor structure and the semiconductor structure itself.

[0006] The first aspect of this disclosure provides a method for forming a semiconductor structure, the method comprising the following steps:

[0007] Multiple first chips are provided, and each first chip has a through-silicon via structure.

[0008] Multiple first chips are vertically stacked to form a chip stack structure, and a portion of the through-silicon via structure forms a first shield structure. The first shield structure is disposed in the edge region of the chip stack structure.

[0009] A second shielding structure is formed along the circumference of the core stack structure, the second shielding structure surrounds the core stack structure, and the second shielding structure covers the sidewall of each of the first core particles in the core stack structure.

[0010] According to some embodiments of this disclosure, providing the first core chip includes:

[0011] Provide initial cores;

[0012] A first through-silicon via structure is formed, wherein the first through-silicon via structure is disposed in the central region of the initial core;

[0013] A second through-silicon via (TSV) structure is formed, which is disposed around the central region of the initial core in the edge region of the initial core. The second TSV structure surrounds the first TSV structure one or more times, and the second TSV structure includes a first shielding layer.

[0014] According to some embodiments of this disclosure, forming the chip stack structure includes:

[0015] A first pad is formed, the first pad is disposed on the first side of the first chip, and the first pad covers the first through-silicon via structure exposed on the first side of the first chip.

[0016] A second pad is formed, which is disposed on the second side of the first chip opposite to the first surface, and the second pad covers the first through-silicon via structure exposed on the second side of the first chip.

[0017] Multiple first chips are vertically stacked in order with their first and second sides facing each other to form the chip stack structure. The first and second pads of adjacent first chips are bonded together to form a first cavity between adjacent first chips. The second through-silicon via structure forms the first shielding structure.

[0018] According to some embodiments of this disclosure, forming the core-particle stack structure further includes:

[0019] A third pad is formed, which covers the second through-silicon via structure exposed on the first side of the first chip, and a second shielding layer is covered on the outside of the third pad;

[0020] A fourth pad is formed, which covers the second through-silicon via structure exposed on the second side of the first die, and a third shielding layer is covered on the outside of the fourth pad;

[0021] In the chip stack structure, the third and fourth pads of adjacent first chips are bonded together, and the vertically connected second through-silicon via structure, the third pad, and the fourth pad together form the first shielding structure.

[0022] According to some embodiments of this disclosure, forming the core-particle stack structure further includes:

[0023] A first dielectric layer is formed, and the first dielectric layer fills the first cavity.

[0024] According to some embodiments of this disclosure, along the circumferential direction of the core stack structure, the second shielding structure further covers the sidewall of each of the first dielectric layers in the core stack structure.

[0025] According to some embodiments of this disclosure, forming the second shielding structure includes:

[0026] A shielding material is deposited, the shielding material covering the sidewalls of the core-particle stack structure and the top surface of the core-particle stack structure;

[0027] The shielding material covering the top surface of the core stack structure is removed, and the remaining shielding material forms the second shielding structure.

[0028] According to some embodiments of this disclosure, the method for forming the semiconductor structure further includes:

[0029] An isolation layer is formed, which covers the top surface of the core particle stack structure;

[0030] The shielding material covers the isolation layer.

[0031] According to some embodiments of this disclosure, removing the shielding material covering the top surface of the core stack structure includes:

[0032] Remove the isolation layer and the shielding material covering the isolation layer.

[0033] A second aspect of this disclosure provides a semiconductor structure, the semiconductor structure comprising:

[0034] A chip stacking structure, the chip stacking structure comprising at least a plurality of stacked first chips, each first chip having a through-silicon via structure, the first chips being vertically stacked through the through-silicon via structure;

[0035] A first shielding structure is disposed in the chip stack structure, the first shielding structure includes at least a portion of the through-silicon via structure, and the first shielding structure is disposed in the edge region of the chip stack structure;

[0036] A second shielding structure is disposed around the circumferential edge of the core stack structure, and the second shielding structure covers the sidewall of each of the first core particles in the core stack structure.

[0037] According to some embodiments of this disclosure, the through-silicon via structure includes a plurality of first through-silicon via structures and a plurality of second through-silicon via structures;

[0038] Multiple first through-silicon via (TSV) structures are disposed in the central region of the first chip, and multiple second TSV structures are disposed around the first TSV structure in the edge region of the first chip. The multiple second TSV structures are disposed in one or more rings around the first TSV structure, and a first shielding layer is disposed in the second TSV.

[0039] According to some embodiments of this disclosure, the chip stack structure further includes:

[0040] A first pad is disposed on a first surface of the first chip, and the first pad covers the first through-silicon via structure exposed on the first surface of the first chip.

[0041] The second pad is disposed on the second side opposite to the first side of the first chip, and the second pad covers the first through-silicon via structure exposed on the second side of the first chip.

[0042] In the chip stacking structure, multiple first chips are vertically stacked in an order in which the first face and the second face are arranged opposite each other. The first pads and the second pads of adjacent first chips are bonded together. A first cavity is provided between adjacent first chips. The second through-silicon via structure is configured as the first shielding structure.

[0043] According to some embodiments of this disclosure, the chip stack structure further includes:

[0044] The third pad covers the second through-silicon via structure exposed on the first side of the first chip, and the outer side of the third pad is covered with a second shielding layer;

[0045] The fourth pad covers the second through-silicon via structure exposed on the second side of the first die, and the outer side of the fourth pad is covered with a third shielding layer;

[0046] In the chip stack structure, the third and fourth pads of adjacent first chips are bonded together, and the vertically connected second through-silicon via structure, the third pad, and the fourth pad together form the first shielding structure.

[0047] According to some embodiments of this disclosure, the chip stack structure further includes:

[0048] A first dielectric layer fills the first cavity.

[0049] According to some embodiments of this disclosure, along the circumferential direction of the core stack structure, the second shielding structure further covers the sidewall of each of the first dielectric layers in the core stack structure.

[0050] In the semiconductor structure formation method and semiconductor structure provided in this disclosure, a first shielding structure is formed in the chip stack structure, and a second shielding structure is formed at the circumferential edge of the chip stack structure, providing a good shielding effect for the semiconductor structure.

[0051] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0052] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of these embodiments. In these drawings, similar reference numerals are used to denote similar elements. The drawings described below are some embodiments of the present disclosure, but not all embodiments. Other drawings will be readily available to those skilled in the art based on these drawings without inventive effort.

[0053] Figure 1 This is a flowchart illustrating a method for forming a semiconductor structure according to an exemplary embodiment.

[0054] Figure 2 This is a flowchart illustrating a method for forming a semiconductor structure according to an exemplary embodiment, showing the provision of an initial core.

[0055] Figure 3 This is a flowchart illustrating a method for forming a chip stack structure in a semiconductor structure according to an exemplary embodiment.

[0056] Figure 4 This is a flowchart illustrating a method for forming a second shielding structure in a semiconductor structure according to an exemplary embodiment.

[0057] Figure 5 This is a flowchart illustrating a method for forming a semiconductor structure according to an exemplary embodiment.

[0058] Figure 6 This is a schematic diagram of an initial die provided in a method for forming a semiconductor structure according to an exemplary embodiment.

[0059] Figure 7 This is a schematic diagram illustrating the formation of a first opening and a second opening in a method for forming a semiconductor structure according to an exemplary embodiment.

[0060] Figure 8 yes Figure 7 The top view of the structure shown in the figure.

[0061] Figure 9 This is a schematic diagram illustrating the formation of a first barrier layer and a second barrier layer in a method for forming a semiconductor structure according to an exemplary embodiment.

[0062] Figure 10 This is a schematic diagram illustrating the formation of a shielding layer in a method for forming a semiconductor structure according to an exemplary embodiment.

[0063] Figure 11This is a schematic diagram illustrating the formation of a first shielding layer in a method for forming a semiconductor structure according to an exemplary embodiment.

[0064] Figure 12 This is a schematic diagram illustrating the formation of a first through-silicon via (TSV) structure and a second TSV structure in a method for forming a semiconductor structure according to an exemplary embodiment.

[0065] Figure 13 This is a schematic diagram illustrating the process of forming a first core by etching back an initial core in a method for forming a semiconductor structure according to an exemplary embodiment.

[0066] Figure 14 yes Figure 13 A top view of the first core particle formed in the process.

[0067] Figure 15 This is a schematic diagram of a first chip formed in a method for forming a semiconductor structure according to an exemplary embodiment.

[0068] Figure 16 This is a schematic diagram illustrating the formation of a first pad and a third pad in a method for forming a semiconductor structure according to an exemplary embodiment.

[0069] Figure 17 This is a schematic diagram illustrating the formation of a second and a fourth pad in a method for forming a semiconductor structure according to an exemplary embodiment.

[0070] Figure 18 This is a schematic diagram illustrating a method for forming a chip stack structure in accordance with an exemplary embodiment of a semiconductor structure.

[0071] Figure 19 This is a schematic diagram illustrating a method for forming a chip stack structure in accordance with an exemplary embodiment of a semiconductor structure.

[0072] Figure 20 This is a schematic diagram illustrating the formation of an isolation layer in a method for forming a semiconductor structure according to an exemplary embodiment.

[0073] Figure 21 This is a schematic diagram illustrating the deposition of a shielding layer material in a method for forming a semiconductor structure according to an exemplary embodiment.

[0074] Figure 22 This is a schematic diagram illustrating the formation of a second shielding layer in a method for forming a semiconductor structure according to an exemplary embodiment.

[0075] Figure label:

[0076] 10. Initial core; 11. Central region of the initial core; 12. Edge region of the initial core;

[0077] 20. First opening;

[0078] 30. Second opening;

[0079] 40. First mask layer; 41. First pattern;

[0080] 50. Shielding layer;

[0081] 60. Isolation layer;

[0082] 100. Chip stack structure; 110. First chip; 1101. First surface of the first chip; 1102. Second surface of the first chip; 111. Central region of the first chip; 112. Edge region of the first chip; 115. First space; 120. First dielectric layer; 130. First pad; 140. Second pad; 150. Third pad; 151. Second shielding layer; 160. Fourth pad; 161. Third shielding layer; 170. Substrate;

[0083] 200. Through-silicon via (TSV) structure; 210. First TSV structure; 211. First barrier layer; 212. First conductive layer; 220. Second TSV structure; 221. Second barrier layer; 222. First shielding layer; 223. Second conductive layer;

[0084] 400. First shielding structure;

[0085] 500. Second shielding structure. Detailed Implementation

[0086] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0087] This disclosure provides an exemplary embodiment of a method for forming a semiconductor structure, such as... Figure 1 As shown, Figure 1 A flowchart illustrating a method for forming a semiconductor structure according to an exemplary embodiment of the present disclosure is shown. Figures 6-22 The diagram below illustrates the various stages of a semiconductor structure formation process. Figures 6-22 The methods for forming semiconductor structures are introduced.

[0088] This embodiment does not limit the semiconductor structure. The following will use dynamic random access memory as an example of semiconductor structure, but this embodiment is not limited to this. The semiconductor structure in this embodiment can also be other structures.

[0089] like Figure 1 As shown, an exemplary embodiment of this disclosure provides a method for forming a semiconductor structure, comprising the following steps:

[0090] Step S100: Provide a plurality of first chips, wherein the first chips are provided with through silicon via structures.

[0091] like Figure 13 , Figure 14 , Figure 15 As shown, the first core 110 includes a central region 111 and an edge region 112, with the edge region 112 located in the region surrounding the central region 111.

[0092] Each first chip 110 has a plurality of through-silicon via (TSV) structures 200. Some TSV structures 200 are located in the central region 111 of the first chip 110, and others are located in the edge region 112 of the first chip 110. The TSV structures 200 in each first chip 110 are located in the same position and arranged in the same way.

[0093] Step S200: Multiple first chips are vertically stacked to form a chip stack structure, and a portion of the through-silicon via structure forms a first shield structure. The first shield structure is disposed in the edge region of the chip stack structure.

[0094] like Figure 18 As shown, refer to Figure 14 Multiple first chips 110 are vertically stacked and connected by identically arranged through-silicon vias (TSVs) 200 to form a chip stack structure 100. The TSVs 200 of the multiple first chips 110 are vertically connected, and some of the vertically connected TSVs 200 form a first shielding structure 400. In this embodiment, the TSVs 200 disposed in the edge region 112 of the first chips 110 are vertically connected to form the first shielding structure 400. The first shielding structure 400 is disposed in the edge region of the chip stack structure 100 and surrounds the central region of the chip stack structure 100.

[0095] In this embodiment, in the chip stack structure 100, the via structures 200 in each first chip 110 are positioned and arranged in the same way. That is, with the top surface of the chip stack structure 100 as the projection surface, the projections of the via structures 200 corresponding to the first chips 110 in the chip stack structure 100 overlap on the top surface of the chip stack structure 100.

[0096] Step S300: Form a second shielding structure. Along the circumference of the core-particle stacking structure, the second shielding structure surrounds the core-particle stacking structure and covers the sidewall of each first core particle in the core-particle stacking structure.

[0097] like Figure 22 As shown, the second shielding structure 500 is disposed around the circumferential outer edge of the core stack structure 100, and the second shielding structure 500 at least covers the sidewall of each first core 110 in the core stack structure 100.

[0098] In this embodiment, a semiconductor structure is formed within a die stack structure, creating a first shielding structure. A second shielding structure is positioned around the die stack structure along its circumferential direction. The first shielding structure is positioned along the outer edge of the die stack structure in its edge region, and the second shielding structure is positioned along the outer edge of the die stack structure on its outer side. The first and second shielding structures form a multi-ring shielding structure around the central region of the die stack structure at the circumferential edge of the semiconductor structure. When interfering electromagnetic waves exist in the working environment of the semiconductor structure, the first and second shielding structures shield the interfering electromagnetic waves at the circumferential edge of the conductor structure, preventing interference to the central region of the die stack structure. Therefore, the semiconductor structure formed in this embodiment has excellent anti-electromagnetic interference performance.

[0099] According to an exemplary embodiment of this disclosure, this embodiment is a further explanation of step S100 in the above embodiment.

[0100] like Figure 2 As shown, a first core is provided, comprising:

[0101] S110: Provides initial cores.

[0102] like Figure 6 As shown, the initial chip 10 can be a semiconductor chip, and the initial chip 10 can include one or more semiconductor materials selected from silicon, germanium, silicon-germanium compounds and silicon-carbon compounds.

[0103] S120: Forming a first through-silicon via structure, the first through-silicon via structure is located in the central region of the initial core.

[0104] like Figure 7 , Figure 8 As shown, multiple first openings 20 are formed, and the multiple first openings 20 are respectively disposed in the central region 11 of the initial core 10. Figure 9 As shown, a first barrier layer 211 is formed by depositing barrier material, and the first barrier layer 211 covers the first opening 20. (As shown...) Figure 12 As shown, refer to Figure 9A first conductive layer 212 is formed by depositing conductive metal to fill the first opening 20, and a first barrier layer 211 and a first conductive layer 212 form a first through-silicon via structure 210. In this embodiment, the barrier material can be tantalum (Ta) or tantalum compounds, and the conductive metal can be copper or copper compounds.

[0105] S130: Forming a second through-silicon via (TSV) structure, the second TSV structure is disposed around the central region of the initial core in the edge region of the initial core, the second TSV structure surrounds the first TSV structure one or more times, and the second TSV structure includes a first shielding layer.

[0106] like Figure 7 As shown, multiple second openings 30 are formed, as referenced. Figure 8 Multiple second openings 30 are respectively disposed in the edge region 12 of the initial core 10. In this embodiment, the multiple second openings 30 are uniformly disposed in the edge region 12 of the initial core 10, surrounding the central region 11 of the initial core 10. Figure 9 As shown, a deposited barrier material covers the second opening 30 to form a second barrier layer 221. (As illustrated...) Figure 11 As shown, refer to Figure 9 A shielding material is deposited, and the shielding material covers the second barrier layer 221 to form the first shielding layer 222. For example... Figure 12 As shown, refer to Figure 11 A conductive metal is deposited to fill the second opening 30, forming a second conductive layer 223, thus forming a second through-silicon via structure 220. For example... Figure 12 As shown, along the radial direction of the second through-silicon via (TSV) structure 220, the TSV structure 220 includes, from the outside to the inside, a second barrier layer 221, a first shielding layer 222, and a second conductive layer 223. In this embodiment, the barrier material can be tantalum (Ta) or tantalum compounds. The shielding material can be one or more of the following mixed metallic materials: aluminum (Al), tungsten (W), aluminum compounds, or tungsten compounds. The conductive metal can be copper or copper compounds.

[0107] In this embodiment, steps S120 and S130 can be performed simultaneously, such as... Figure 6 As shown, refer to Figure 8 A first mask layer 40 is formed on the initial die 10, covering the top surface of the initial die 10. The first mask layer 40 includes a first pattern 41, which exposes a portion of the top surface of the central region 11 and a portion of the top surface of the edge region 12 of the initial die 10. A plurality of through-silicon vias (TSVs) are formed by removing the exposed portions of the initial die 10 according to the first mask layer 40. Figure 7 As shown, refer to Figure 8The through-silicon via (TSV) opening located in the central region 11 of the initial core 10 is used as the first opening 20, and the TSV opening located in the edge region 12 of the initial core 10 is used as the second opening 30.

[0108] like Figure 9 As shown, refer to Figure 7 A barrier material is deposited, which covers the first opening 20 to form a first barrier layer 211, and the barrier material covers the second opening 30 to form a second barrier layer 221. For example... Figure 10 As shown, refer to Figure 9 This forms a shielding layer 50, which covers the top surface of the initial core 10 and fills the first opening 20. (Example:) Figure 11 As shown, refer to Figure 10 A first shielding layer 222 is formed in the second opening 30 by depositing shielding material, and the first shielding layer 222 covers the second barrier layer 221.

[0109] like Figure 12 As shown, refer to Figure 11 The shielding layer 50 is removed, and conductive material is deposited to fill the first opening 20 and the second opening 30, forming a first through-silicon via structure 210 and a second through-silicon via structure 220, respectively. For example... Figure 13 As shown, refer to Figure 12 The back side of the initial die 10 is etched back to expose the first through-silicon via (TSV) structure 210 and the second TSV structure 220, and etching is stopped to form the first die 110. For example... Figure 14 As shown, a second through-silicon via structure 220 is disposed in the edge region 112 of the first core 110, and a first shielding layer 222 is disposed in the second through-silicon via structure 220.

[0110] In other embodiments of this application, when forming the second through-silicon via structure 220, a shielding material can be deposited to fill the second opening 30, such as... Figure 15 As shown, the formed second through-silicon via structure 220 does not include the second conductive layer 223.

[0111] In this embodiment, a first shielding layer is provided in the second through-silicon via structure. Multiple second through-silicon via structures are arranged in the edge region of the first core to form a first shielding structure surrounding the central region of the first core. This shielding structure can shield the semiconductor structure's working environment from interference to the core stack structure. Furthermore, the shielding material in the first shielding layer of the second through-silicon via structure is a low-resistivity metal material such as aluminum or tungsten. When the semiconductor structure is exposed to a high-frequency interfering electromagnetic field, the eddy currents generated by the shielding material in the first shielding layer can cancel the interfering electromagnetic waves, thus achieving the effect of shielding the interfering electromagnetic waves and preventing the first through-silicon via structure in the central region of the first core from being subjected to electromagnetic interference.

[0112] According to an exemplary embodiment of this disclosure, this embodiment is a further explanation of step S200 in the above embodiment.

[0113] like Figure 3 As shown, a core-particle stack structure is formed, comprising:

[0114] S210: Form a first pad, the first pad is disposed on the first side of the first chip, the first pad covers the first through-silicon via structure exposed on the first side of the first chip.

[0115] like Figure 16 As shown, refer to Figure 13 The first pad 130 can be connected to the first through-silicon via structure 210 by soldering, and the first pad 120 forms a protrusion relative to the first surface 1101 of the first chip 110.

[0116] S220: Form a second pad, which is disposed on the second side of the first chip opposite to the first surface, and the second pad covers the first through-silicon via structure exposed on the second side of the first chip.

[0117] like Figure 17 As shown, refer to Figure 16 The second pad 140 can be connected to the first through-silicon via structure 210 by soldering, and the second pad 140 forms a protrusion on the second surface 1102 relative to the first chip 110.

[0118] S230: Multiple first chips are vertically stacked in order of their first and second sides being arranged opposite each other to form a chip stack structure. The first and second pads of adjacent first chips are bonded together to form a first cavity between adjacent first chips. The second through-silicon via structure forms a first shielding structure.

[0119] like Figure 18 As shown, refer to Figure 17 A substrate 170 is provided, and a plurality of first core particles 110 are stacked sequentially on the substrate 170 with the same arrangement direction. The plurality of first core particles 110 are stacked vertically in an order in which the first surface 1101 and the second surface 1102 are arranged opposite each other to form a core particle stack structure 100. The first pads 130 and the second pads 140 of adjacent first core particles 110 are bonded together.

[0120] like Figure 18 As shown, the first through-silicon via structure 210, the first pad 130 and the second pad 140 in the chip stack structure 100 form a metal interconnect. Along the stacking direction of the first chip 110, the second through-silicon via structures 210 of the first chip 110 form a first shielding structure 400 disposed in the chip stack structure 100 along the outer edge of the chip stack structure 100.

[0121] S240: Form a first dielectric layer, which fills the first cavity.

[0122] like Figure 19 As shown, refer to Figure 18 A first dielectric layer 120 is formed between adjacent first core particles 110 by depositing dielectric material through atomic layer deposition (ALD) or chemical vapor deposition (CVD) to fill the first space 115 between adjacent first core particles 110. The dielectric material can be silicon dioxide.

[0123] In the chip stacking structure formed in this embodiment, the second through-silicon via (TSV) structures in multiple first chips form a first shielding structure surrounding the central region of the chip stacking structure. The first TSV structure, the first pad, and the second pad form a metal interconnect in the central region of the chip stacking structure. When transmitting communication signals in the metal interconnect in the central region of the chip stacking structure, the first shielding structure can provide a good anti-interference effect for the metal interconnect, preventing the information transmitted in the semiconductor structure from being interfered with.

[0124] According to an exemplary embodiment of this disclosure, this embodiment is a further explanation of step S200 in the above embodiment.

[0125] In addition to steps S210 to S240 in the above embodiments, the step of forming the core stack structure also includes:

[0126] S250: A third pad is formed, which covers the second through-silicon via structure exposed on the first side of the first die, and a second shielding layer is covered on the outside of the third pad.

[0127] like Figure 16 As shown, refer to Figure 13 The third pad 150 can be connected to the second through-silicon via structure 220 via soldering. The third pad 150 forms a protrusion relative to the first surface 1101 of the first chip 110. In this embodiment, the shielding material in the second shielding layer 151 is the same as the material in the first shielding layer 222. In this embodiment, step S250 can be performed simultaneously with step S210.

[0128] S260: A fourth pad is formed, which covers the second through-silicon via structure exposed on the second side of the first die, and a third shielding layer is covered on the outside of the fourth pad.

[0129] like Figure 17 As shown, refer to Figure 16The fourth pad 160 can be connected to the second through-silicon via structure 220 via soldering. The fourth pad 160 forms a protrusion on the second surface 1102 relative to the first core 110. The shielding material in the third shielding layer 161 is the same as the material in the first shielding layer 222. In this embodiment, step S260 can be performed simultaneously with step S220.

[0130] like Figure 18 As shown, in the chip stack structure 100 formed by stacking multiple first chips 110, the third pads 150 and fourth pads 160 of adjacent first chips 110 are bonded together, and the vertically connected second through-silicon via structure 220, third pads 150 and fourth pads 160 together form a first shielding structure 400.

[0131] In this embodiment, in the chip stack structure, the vertically connected second through-silicon via structure, third pad and fourth pad also form a metal interconnect, and the first shielding structure has a better shielding effect in the circumferential direction of the edge region of the chip stack structure.

[0132] According to an exemplary embodiment of this disclosure, this embodiment is a further explanation of step S300 in the above embodiment.

[0133] like Figure 4 As shown, a second shielding structure is formed, comprising:

[0134] S310: Deposited shielding material, which covers the sidewalls and top surface of the core-particle stack structure.

[0135] like Figure 21 As shown, refer to Figure 19 A shielding material is deposited using atomic layer deposition (ALD) to cover the sidewalls and top surface of the core stack structure 100. The deposited shielding material can be one or more of the following metallic materials: aluminum (Al), tungsten (W), aluminides, or tungsten compounds. The shielding material covering the core stack structure 100 used to form the second shielding structure 500 may be the same as or different from the shielding material in the first shielding layer 222 of the second through-silicon via structure 220. In this embodiment, the shielding material used to form the second shielding structure 500 and the shielding material in the first shielding layer 222 are selected from different shielding metals.

[0136] S320: Remove the shielding material covering the top surface of the core stack structure; the remaining shielding material forms a second shielding structure.

[0137] like Figure 22 As shown, refer to Figure 21The shielding material covering the top surface of the chip stack structure 100 is removed by dry etching or wet etching process, and the shielding material covering the sides of the chip stack structure 100 is retained to form a second shielding structure 500. Along the circumference of the chip stack structure 100, the second shielding structure 500 covers the sidewalls of each first chip 110 and each first dielectric layer 120 in the chip stack structure 100.

[0138] In this embodiment, the semiconductor structure forms a second shielding structure around the core-particle stack structure. The first and second shielding structures form shielding regions at the edges of the semiconductor structure. When the semiconductor structure is exposed to low-frequency electromagnetic interference, the first and second shielding structures can confine the interference electromagnetic waves within the shielding regions, preventing them from spreading to the central region of the core-particle stack structure. The semiconductor structure formed in this embodiment exhibits good shielding effects against both low-frequency and high-frequency electromagnetic waves.

[0139] This disclosure provides an exemplary embodiment of a method for forming a semiconductor structure, such as... Figure 5 As shown, this embodiment provides a method for forming a semiconductor structure, which includes the following steps:

[0140] Step S10: Provide multiple first chips, each of which has a through-silicon via structure.

[0141] Step S20: Multiple first chips are vertically stacked to form a chip stack structure, and a portion of the through-silicon via structure forms a first shield structure. The first shield structure is set in the edge region of the chip stack structure.

[0142] Step S30: Form an isolation layer that covers the top surface of the core stack structure.

[0143] like Figure 20 As shown, refer to Figure 19 The isolation layer 60 may include a photoresist.

[0144] Step S40: Form a second shielding structure. Along the circumference of the core-particle stacking structure, the second shielding structure surrounds the core-particle stacking structure and covers the sidewall of each first core particle in the core-particle stacking structure.

[0145] The methods for forming steps S10 and S20 in this embodiment are the same as those for steps S100 and S200 in the above embodiments, and will not be repeated here.

[0146] In this embodiment, before forming the second shielding structure 500, as follows: Figure 19 As shown, refer to Figure 18An isolation layer 60 is formed on the top surface of the core stack structure 100. When removing the shielding material covering the top surface of the core stack structure 100 in step S40, the isolation layer 60 and the shielding material covering the isolation layer 60 can be removed directly. The operation of removing the shielding material covering the core stack structure 100 is simpler.

[0147] According to an exemplary embodiment of this disclosure, this embodiment provides a semiconductor structure, such as... Figure 22 As shown, refer to Figure 13 , Figure 14 The semiconductor structure in this embodiment includes: a chip stack structure 100, a first shielding structure 400 disposed in the chip stack structure 100, and a second shielding structure 500 disposed around the circumferential edge of the chip stack structure 100.

[0148] The chip stack structure 100 includes at least a plurality of stacked first chips 110, each first chip 110 having a through-silicon via (TSV) structure 200, and the first chips 110 are vertically stacked through the TSV structures 200. A first shielding structure 400 is disposed at the edge region of the chip stack structure 100, and the first shielding structure 400 includes at least a portion of the TSV structures 200. A second shielding structure 500 is disposed around the circumferential edge of the chip stack structure 100, and the second shielding structure 500 covers the sidewalls of each first chip 110 in the chip stack structure 100.

[0149] In this embodiment, the semiconductor structure has a first shielding structure 400 and a second shielding structure 500 surrounding the chip stacking structure 100. The two shielding structures are formed at the edge of the semiconductor structure, providing a better shielding effect to prevent the central region of the chip stacking structure 100 from being interfered with.

[0150] According to an exemplary embodiment, most of the semiconductor structure in this embodiment is the same as that in the above embodiments. The difference between this embodiment and the above embodiments is that, Figure 22 As shown, refer to Figure 14 The through-silicon via (TSV) structure 200 includes a plurality of first TSV structures 210 and a plurality of second TSV structures 220. The plurality of first TSV structures 210 are disposed in the central region 111 of the first core 110, and the plurality of second TSV structures 220 are disposed around the first TSV structures 210 in the edge region 112 of the first core 110. The plurality of second TSV structures 220 surround the first TSV structures 110 in one or more rings, and a first shielding layer 222 is disposed in the second TSV structure 220.

[0151] In this embodiment, a plurality of second through-silicon via (TSV) structures 220 can be uniformly disposed in the edge region 112 of the first chip 110, forming one or more annular structures surrounding the first TSV structure 110. In other embodiments of this disclosure, the plurality of second TSV structures 220 can also be discretely disposed in the edge region 112 of the first chip 110. When the top view of the first chip 110 is square or rectangular, the plurality of second TSV structures 220 can also be disposed at the four vertices of the first chip 110 to increase the area of ​​the central region 111 of the first chip 110.

[0152] In this embodiment, as Figure 22 As shown, refer to Figure 17 The chip stack structure 100 further includes: a first pad 130 and a third pad 150 disposed on a first surface 1101 of the first chip 110, and a second pad 140 and a fourth pad 160 disposed on a second surface 1102 of the first chip 110. The first pad 130 covers the first through-silicon via (TSV) structure 210 exposed on the first surface 1101 of the first chip 110; the third pad 150 covers the second TSV structure 220 exposed on the first surface 1101 of the first chip 110, as shown below. Figure 17 The outer side of the third pad 150 is covered by a second shielding layer 151. The second pad 140 covers the first through-silicon via structure 210 exposed on the second side of the first chip 110, and the fourth pad 160 covers the second through-silicon via structure 220 exposed on the second side of the first chip 110, as shown in the figure. Figure 17 The outer side of the fourth pad 160 is covered by a third shielding layer 161.

[0153] In the chip stacking structure 100, multiple first chips 110 are vertically stacked in an order in which the first surface 1101 and the second surface 1102 are arranged opposite each other. The first pads 130 and second pads 140 of adjacent first chips 110 are bonded together, and the third pads 150 and fourth pads 160 are bonded together. (Refer to...) Figure 18 A first cavity 115 is provided between adjacent first cores 110, and the second through-silicon via structures 220 of the multiple first cores 110 form a first shielding structure 400 surrounding the central region of the core stack structure 100.

[0154] In this embodiment, as Figure 22 As shown, according to Figure 18 The core stack structure 100 further includes: a first dielectric layer 120, which fills the first cavity 115.

[0155] In this embodiment, as Figure 22 As shown, the vertically connected second through-silicon via structure 220, third pad 150 and fourth pad 160 are collectively configured as the first shielding structure 400.

[0156] According to an exemplary embodiment, most of the semiconductor structure in this embodiment is the same as that in the above embodiments. The difference between this embodiment and the above embodiments is that, Figure 22 As shown, along the circumference of the core stack structure 100, the second shielding structure 500 also covers the sidewalls of each first dielectric layer 120 in the core stack structure 100.

[0157] The semiconductor structure disclosed herein includes a first shielding structure disposed along the outer edge of the chip stack structure and a second shielding structure disposed around the circumferential outer edge of the chip stack structure. The first shielding structure and the second shielding structure form a multi-ring shielding structure around the central region of the chip stack structure at the circumferential edge of the semiconductor structure, which has a good anti-interference effect.

[0158] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0159] In the description of this specification, references to the terms "embodiment," "exemplary embodiment," "some implementation," "illustrated implementation," "example," etc., refer to specific features, structures, materials, or characteristics described in connection with an implementation or example that are included in at least one implementation or example of this disclosure.

[0160] In this specification, the illustrative expressions of the terms used do not necessarily refer to the same implementation or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more implementations or examples.

[0161] In the description of this disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0162] It is understood that the terms "first," "second," etc., as used in this disclosure may be used to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another.

[0163] In one or more accompanying drawings, the same elements are represented by similar reference numerals. For clarity, many parts in the drawings are not drawn to scale. Furthermore, certain well-known parts may not be shown. For simplicity, a structure obtained after several steps may be depicted in a single drawing. Many specific details of this disclosure, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the disclosure. However, as those skilled in the art will understand, this disclosure may be implemented without adhering to these specific details.

[0164] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A method of forming a semiconductor structure, characterized by, The method for forming the semiconductor structure comprises the following steps: The method comprises the following steps: A plurality of first core particles are provided, and a through silicon via structure is arranged in the first core particle, including: providing an initial core particle; forming a first through silicon via structure arranged in a central region of the initial core particle, the first through silicon via structure being formed by a first barrier layer and a first conductive layer; and forming a second through silicon via structure arranged in an edge region of the initial core particle around the central region of the initial core particle, the second through silicon via structure surrounding the first through silicon via structure for one or more turns, the second through silicon via structure comprising, from outside to inside, a second barrier layer, a first shielding layer and a second conductive layer, wherein the barrier material of the first barrier layer and the second barrier layer is tantalum or tantalum compound, the shielding material of the first shielding layer is one or a mixture of two or more of aluminum, tungsten, aluminum compound or tungsten compound, and the conductive metal of the first conductive layer and the second conductive layer is copper or copper compound; A plurality of the first core particles are vertically stacked to form a core particle stack structure, and a first shielding structure is formed by at least the second through silicon via structure, the first shielding structure being arranged in an edge region of the core particle stack structure; 2. The method of forming a semiconductor structure of claim 1, wherein, A second shielding structure is formed, which surrounds the core particle stack structure along the circumference of the core particle stack structure, and covers the sidewall of each first core particle in the core particle stack structure. The method for forming the core particle stack structure comprises: A first pad is formed, which is arranged on a first surface of the first core particle and covers the first through silicon via structure exposed on the first surface of the first core particle; A second pad is formed, which is arranged on a second surface of the first core particle opposite to the first surface and covers the first through silicon via structure exposed on the second surface of the first core particle; 3. The method of forming a semiconductor structure of claim 2, wherein, The plurality of first core particles are vertically stacked in the order of the first surface and the second surface being arranged opposite to each other, to form the core particle stack structure, the first pad and the second pad of adjacent first core particles are bonded and connected, a first cavity is formed between adjacent first core particles, and the second through silicon via structure forms the first shielding structure. The method for forming the core particle stack structure further comprises: A third pad is formed, which covers the second through silicon via structure exposed on the first surface of the first core particle, and an outer side of the third pad is covered with a second shielding layer; A fourth pad is formed, which covers the second through silicon via structure exposed on the second surface of the first core particle, and an outer side of the fourth pad is covered with a third shielding layer; 4. The method of forming a semiconductor structure of claim 2, wherein, In the core particle stack structure, the third pad and the fourth pad of adjacent first core particles are bonded and connected, and the second through silicon via structure, the third pad and the fourth pad that are vertically connected together form the first shielding structure. The method for forming the core particle stack structure further comprises:

5. The method of forming a semiconductor structure of claim 4, wherein, A first dielectric layer is formed, which fills the first cavity. Along the circumference of the core particle stack structure, the second shielding structure also covers the sidewall of each first dielectric layer in the core particle stack structure.

6. The method of forming a semiconductor structure of claim 1, wherein, The forming the second shielding structure comprises: depositing a shielding material, the shielding material covering sidewalls of the core particle stack structure and a top surface of the core particle stack structure; removing the shielding material covering the top surface of the core particle stack structure, the remaining shielding material forming the second shielding structure.

7. The method of forming a semiconductor structure of claim 6, wherein, The method for forming the semiconductor structure further comprises: forming an isolation layer, the isolation layer covering the top surface of the core particle stack structure; the shielding material covering the isolation layer.

8. The method of forming a semiconductor structure of claim 7, wherein, The removing the shielding material covering the top surface of the core particle stack structure comprises: removing the isolation layer and the shielding material covering the isolation layer.

9. A semiconductor structure, characterized by Comprise: a core particle stack structure, the core particle stack structure comprising at least a plurality of first core particles stacked in a stack, the first core particles being provided with a through-silicon via structure, the first core particles being vertically stacked through the through-silicon via structure, the through-silicon via structure comprising a plurality of first through-silicon via structures and a plurality of second through-silicon via structures; the plurality of first through-silicon via structures being arranged in a central region of the first core particle, the plurality of second through-silicon via structures being arranged in an edge region of the first core particle around the first through-silicon via structures, the plurality of second through-silicon via structures being arranged in one or more circles around the first through-silicon via structures, the first through-silicon via structure being composed of a first barrier layer and a first conductive layer, the second through-silicon via structure comprising, from outside to inside, a second barrier layer, a first shielding layer, and a second conductive layer, wherein the barrier material of the first barrier layer and the second barrier layer is tantalum or tantalum compound, the shielding material of the first shielding layer is one or more than two kinds of mixture of aluminum, tungsten, aluminum compound, or tungsten compound, and the conductive metal of the first conductive layer and the second conductive layer is copper or copper compound; a first shielding structure, the first shielding structure being arranged in the core particle stack structure, the first shielding structure comprising at least the second through-silicon via structure, the first shielding structure being arranged in the edge region of the core particle stack structure; a second shielding structure, the second shielding structure being arranged around the core particle stack structure at a peripheral edge of the core particle stack structure, the second shielding structure covering sidewalls of each of the first core particles in the core particle stack structure.

10. The semiconductor structure of claim 9, wherein, The core particle stack structure further comprises: a first pad, the first pad being arranged at a first surface of the first core particle, the first pad covering the first through-silicon via structure exposed by the first surface of the first core particle; a second pad, the second pad being arranged at a second surface opposite to the first surface of the first core particle, the second pad covering the first through-silicon via structure exposed by the second surface of the first core particle; the plurality of first core particles in the core particle stack structure are vertically stacked in an order of the first surface and the second surface being arranged oppositely, the first pad and the second pad of adjacent first core particles being bonded and connected, a first cavity being arranged between adjacent first core particles, and the second through-silicon via structure being arranged as the first shielding structure.

11. The semiconductor structure of claim 10, wherein, The core particle stack structure further comprises: a third pad covering the second through silicon via structure exposed by the first face of the first core pellet, an outer side of the third pad being covered by a second shielding layer; a fourth pad covering the second through silicon via structure exposed by the second face of the first core pellet, an outer side of the fourth pad being covered by a third shielding layer; in the core pellet stack structure, the third pad and the fourth pad of adjacent first core pellets are bonded and connected, the vertically connected second through silicon via structure, the third pad and the fourth pad being collectively configured as the first shielding structure.

12. The semiconductor structure of claim 11, wherein, The core pellet stack structure further comprises: a first dielectric layer filling the first cavity.

13. The semiconductor structure of claim 12, wherein, Along a circumferential direction of the core pellet stack structure, the second shielding structure further covers a sidewall of each of the first dielectric layers in the core pellet stack structure.

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