amplifier circuit
By combining differential input signals and multi-stage amplification, along with switching control and bias circuit optimization, the problem of insufficient gain in existing amplifier circuits is solved, achieving high-gain and high-efficiency signal amplification.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- REALTEK SEMICON CORP
- Filing Date
- 2021-09-15
- Publication Date
- 2026-06-19
AI Technical Summary
There is room for improvement in the gain of existing amplifier circuits, and it is difficult to achieve high-gain amplification with current technology.
The amplifier circuit design employs a differential input signal. Through the combination of multiple amplification stages and switches, the clock signal controls the switching on and off, achieving multiple common-source amplification of the signal. The bias circuit optimizes the conduction characteristics of the transistor.
It achieves high-gain amplification, improving the operating speed of the amplifier circuit and the efficiency of signal amplification.
Smart Images
Figure CN115811284B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to amplifier circuits, and more particularly to amplifier circuits with high gain. Background Technology
[0002] Figure 1 This is a circuit diagram of an existing amplifier circuit. Amplifier circuit 100 includes transistors 101, 102, 103, 104, and 105. Amplifier circuit 100 receives a pair of differential input signals (including input signal Vip and input signal Vin) through the gates of transistors 101 and 102, and outputs the amplified signal through output terminals Di- and Di+. The gates of transistors 103, 104, and 105 receive a clock CK and are turned on or off according to the clock CK. In the diagram, "VDD" represents the power supply voltage, and "GND" represents the ground level. The operating principle of amplifier circuit 100 is well known to those skilled in the art and will not be described further. However... Figure 1 There is still room for improvement in the gain of the existing amplifier circuit 100. Summary of the Invention
[0003] In view of the shortcomings of the prior art, one object of the present invention is to provide an amplifier circuit to improve upon the shortcomings of the prior art.
[0004] An embodiment of the present invention provides an amplifier circuit having a first output terminal and a second output terminal, comprising: a first transistor having a first terminal, a second terminal, and a first control terminal, wherein the second terminal is coupled to the first output terminal; a second transistor having a third terminal, a fourth terminal, and a second control terminal, wherein the fourth terminal is coupled to the second output terminal; a third transistor having a fifth terminal, a sixth terminal, and a third control terminal, wherein the sixth terminal is coupled to the first terminal, and the third control terminal receives a first input signal; a fourth transistor having a seventh terminal, an eighth terminal, and a fourth control terminal, wherein the seventh terminal is coupled to the fifth terminal, the eighth terminal is coupled to the third terminal, and the fourth control terminal receives a second input signal; and a first switch having a ninth terminal and a... A tenth terminal, wherein the ninth terminal is coupled to a first reference voltage, and the tenth terminal is coupled to the first output terminal; a second switch, having an eleventh terminal and a twelfth terminal, wherein the eleventh terminal is coupled to the first reference voltage, and the twelfth terminal is coupled to the second output terminal; a third switch, having a thirteenth terminal and a fourteenth terminal, wherein the thirteenth terminal is coupled to the first reference voltage, and the fourteenth terminal is coupled to the first terminal and the sixth terminal; a fourth switch, having a fifteenth terminal and a sixteenth terminal, wherein the fifteenth terminal is coupled to the first reference voltage, and the sixteenth terminal is coupled to the third terminal and the eighth terminal; and a fifth switch, having a seventeenth terminal and an eighteenth terminal, wherein the seventeenth terminal is coupled to a second reference voltage, and the eighteenth terminal is coupled to the fifth terminal and the seventh terminal. The first input signal and the second input signal are a pair of differential input signals, and the first output terminal and the second output terminal output a pair of differential output signals.
[0005] Another embodiment of the present invention provides an amplifier circuit that outputs a pair of differential output signals through a first output terminal and a second output terminal, comprising: a first amplification stage electrically connected to a first node and a second node for amplifying a pair of differential input signals; a second amplification stage electrically connected to the first node and the second node and coupled to the first output terminal and the second output terminal; a first switch coupled between the first output terminal and a first reference voltage; a second switch coupled between the second output terminal and the first reference voltage; a third switch coupled between the first node and the first reference voltage; a fourth switch coupled between the second node and the first reference voltage; and a fifth switch coupled between a second reference voltage and the first amplification stage.
[0006] The amplifier circuit of this invention has high gain.
[0007] The features, implementation, and effects of this invention are described in detail below with reference to the accompanying drawings. Attached Figure Description
[0008] Figure 1This is a circuit diagram of an existing amplifier circuit;
[0009] Figure 2 This is a circuit diagram of one embodiment of the amplifier circuit of the present invention;
[0010] Figure 3 This is a circuit diagram of another embodiment of the amplifier circuit of the present invention;
[0011] Figure 4 This is a timing diagram of the conduction of each amplification stage in the amplifier circuit of this invention;
[0012] Figure 5 This is a circuit diagram of another embodiment of the amplifier circuit of the present invention;
[0013] Figure 6 A circuit diagram of one embodiment of the bias circuit 510;
[0014] Figure 7 A circuit diagram of one embodiment of the bias circuit 510;
[0015] Figure 8 This is a circuit diagram of another embodiment of the amplifier circuit of the present invention;
[0016] Figure 9 A circuit diagram of one embodiment of the bias circuit 810;
[0017] Figure 10 A circuit diagram of one embodiment of the bias circuit 810; and
[0018] Figure 11 This is a comparison chart of the operating speeds of the amplifier circuits in this case. Detailed Implementation
[0019] The technical terms used in the following description refer to the common terms in this technical field. If this specification provides explanations or definitions for certain terms, the explanations or definitions in this specification shall prevail.
[0020] The disclosure of this invention includes amplifier circuits. Since some components of the amplifier circuit of this invention may be known components individually, details of known components will be omitted in the following description without affecting the full disclosure and implementability of the device invention.
[0021] In the following description, each transistor has a first terminal, a second terminal, and a control terminal. When a transistor is used as a switch, the first and second terminals are the two ends of the switch, while the control terminal controls whether the switch is turned on (transistor on) or off (transistor off). For a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), the first terminal can be either the source or the drain, the second terminal is either the source or the drain, and the control terminal is the gate. For a bipolar junction transistor (BJT), the first terminal can be either the collector or the emitter, the second terminal is either the collector or the emitter, and the control terminal is the base.
[0022] Figure 2 This is a circuit diagram of one embodiment of the amplifier circuit of the present invention. The amplifier circuit 200 includes transistors M1, M2, M3, and M4, and switches SW1, SW2, SW3, SW4, and SW5. Switches SW1, SW2, SW3, SW4, and SW5 are implemented by transistors M5, M6, M7, M8, and M9, respectively. Figure 2 In the embodiment, transistors M1, M2, M3, M4 and M9 are P-type metal-oxide-semiconductor field-effect transistors (PMOS transistors), while transistors M5, M6, M7 and M8 are N-type metal-oxide-semiconductor field-effect transistors (NMOS transistors).
[0023] The first terminal of transistor M1 is coupled or electrically connected to the first terminal of transistor M3; the second terminal of transistor M1 is the output terminal Di- of amplifier circuit 200, and is coupled to the first reference voltage GND (e.g., ground level) through switch SW1; the control terminal of transistor M1 receives the input signal Vip. The first terminal of transistor M2 is coupled or electrically connected to the first terminal of transistor M4; the second terminal of transistor M2 is the output terminal Di+ of amplifier circuit 200, and is coupled to the first reference voltage GND through switch SW2; the control terminal of transistor M2 receives the input signal Vin. Input signals Vip and Vin form a pair of differential input signals. "Di-" and "Di+" can also represent a pair of differential output signals output through output terminals Di- and Di+.
[0024] The second terminal of transistor M3 is coupled to or electrically connected to the second terminal of transistor M4; the second terminals of transistor M3 and transistor M4 are coupled to a second reference voltage VDD (e.g., power supply voltage, where the second reference voltage VDD is not equal to the first reference voltage GND) via switch SW5. The control terminal of transistor M3 receives the input signal Vip, and the control terminal of transistor M4 receives the input signal Vin.
[0025] One end of switch SW3 is coupled or electrically connected to the first reference voltage GND, and the other end of switch SW3 is coupled or electrically connected (e.g., through node N1) to the first terminal of transistor M1 and the first terminal of transistor M3. One end of switch SW4 is coupled or electrically connected to the first reference voltage GND, and the other end of switch SW4 is coupled or electrically connected (e.g., through node N2) to the first terminal of transistor M2 and the first terminal of transistor M4.
[0026] Switches SW1, SW2, SW3, SW4, and SW5 all operate according to clock CK. When clock CK is at the first level (e.g., high level or logic 1), switches SW1, SW2, SW3, and SW4 are turned on, and switch SW5 is turned off; at this time, amplifier circuit 200 operates in the reset phase. When clock CK is at the second level (e.g., low level or logic 0), switches SW1, SW2, SW3, and SW4 are turned off, and switch SW5 is turned on; at this time, amplifier circuit 200 operates in the amplification phase.
[0027] Transistors M3 and M4 constitute the first amplification stage SA1 of amplifier circuit 200, and transistors M1 and M2 constitute the second amplification stage SA2 of amplifier circuit 200. The first amplification stage SA1 and the second amplification stage SA2 are coupled to or electrically connected to nodes N1 and N2. More specifically, the first terminal of transistor M1 and the first terminal of transistor M3 are coupled to or electrically connected to node N1; the first terminal of transistor M2 and the first terminal of transistor M4 are coupled to or electrically connected to node N2.
[0028] The first amplification stage SA1 amplifies the input signals Vip and Vin, and generates a first amplified signal at the first terminals of transistors M3 and M4. The second amplification stage SA2 amplifies the input signals Vip and Vin, and generates a second amplified signal (i.e., the output signal of amplifier circuit 200) at the output terminals Di- and Di+. The second amplification stage SA2 plays the role of common-source amplification in amplifier circuit 200, further amplifying the amplification results of transistors M3 and M4 (i.e., the first amplified signal). Specifically, since the control signals of the second amplification stage SA2 are the input signals Vip and Vin, and the signal at the first terminal of the second amplification stage SA2 is the first amplified signal (i.e., the amplified input signals Vip and Vin), the second amplification stage SA2 further utilizes the correlation signals of the input signals Vip and Vin for amplification. Therefore, amplifier circuit 200 has a greater gain than the existing amplifier circuit 100.
[0029] Figure 3 This is a circuit diagram of another embodiment of the amplifier circuit of the present invention. Amplifier circuit 300 is similar to amplifier circuit 200, except that amplifier circuit 300 also includes transistor M10, transistor M11, switch SW14, and switch SW15. Amplifier circuit 300 includes three amplification stages; transistors M10 and M11 form the third amplification stage SA3. The second amplification stage SA2 is located between the first amplification stage SA1 and the third amplification stage SA3. Switch SW14 is implemented by transistor M12, and switch SW15 is implemented by transistor M13. Figure 3 In the embodiment, transistors M10 and M11 are PMOS transistors, while transistors M12 and M13 are NMOS transistors.
[0030] The first terminal of transistor M10 is coupled or electrically connected (e.g., through node N3) to the second terminal of transistor M1; the second terminal of transistor M10 is the output terminal Di- of amplifier circuit 300 and is coupled to the first reference voltage GND through switch SW1; the control terminal of transistor M10 receives the input signal Vip. The first terminal of transistor M11 is coupled or electrically connected (e.g., through node N4) to the second terminal of transistor M2; the second terminal of transistor M11 is the output terminal Di+ of amplifier circuit 300 and is coupled to the first reference voltage GND through switch SW2; the control terminal of transistor M11 receives the input signal Vin.
[0031] The second amplification stage SA2 and the third amplification stage SA3 are coupled or electrically connected to nodes N3 and N4. More specifically, the second terminal of transistor M1 and the first terminal of transistor M10 are coupled or electrically connected to node N3; the second terminal of transistor M2 and the first terminal of transistor M11 are coupled or electrically connected to node N4.
[0032] One end of switch SW14 is coupled or electrically connected to the first reference voltage GND, and the other end of switch SW14 is coupled or electrically connected to the first terminal of transistor M10 and the second terminal of transistor M1. One end of switch SW15 is coupled or electrically connected to the first reference voltage GND, and the other end of switch SW15 is coupled or electrically connected to the first terminal of transistor M11 and the second terminal of transistor M2.
[0033] Switches SW14 and SW15 operate according to clock CK. When clock CK is at the first level (e.g., high level or logic 1), switches SW14 and SW15 are turned on; when clock CK is at the second level (e.g., low level or logic 0), switches SW14 and SW15 are not turned on.
[0034] The third amplification stage SA3 plays the role of common-source amplification in amplifier circuit 300, further amplifying the amplified result (second amplified signal) from the second amplification stage SA2. Specifically, because the control signals of the third amplification stage SA3 are the input signals Vip and Vin, and the signal at the first terminal of the third amplification stage SA3 is the second amplified signal (i.e., the input signals Vip and Vin after two amplifications), the third amplification stage SA3 further utilizes the correlation between the input signals Vip and Vin for amplification. Therefore, amplifier circuit 300 has a greater gain than amplifier circuit 200.
[0035] The amplifier circuit of this invention is not limited to three amplification stages; those skilled in the art can use more amplification stages based on the above description.
[0036] Figure 4 The amplifier circuit of this invention includes each amplification stage (with...). Figure 3 The following is a timing diagram of the conduction of an embodiment (as an example). Curves Cv1, Cv2, and Cv3 correspond to the source voltages of transistors M3 / M4, M1 / M2, and M10 / M11, respectively. As shown in the figure, the first amplification stage SA1, the second amplification stage SA2, and the third amplification stage SA3 are sequentially activated (i.e., the corresponding transistors are turned on) to sequentially amplify the signal.
[0037] Figure 5This is a circuit diagram of another embodiment of the amplifier circuit of the present invention. Amplifier circuit 500 is similar to amplifier circuit 200, except that amplifier circuit 500 also includes a bias circuit 510. The bias circuit 510 generates bias voltages Vbias1 and Vbias2 at nodes g1 and g2 respectively, based on the input signal Vip, the input signal Vin, the reference voltage Vb11, and the reference voltage Vb12. Node g1 is the control terminal of transistor M1, and node g2 is the control terminal of transistor M2.
[0038] Figure 6 This is a circuit diagram of one embodiment of the bias circuit 510. The bias circuit 510a includes capacitor C1, capacitor C2, switch SW6, switch SW7, switch SW8, switch SW9, switch SW10, switch SW11, switch SW12 and switch SW13.
[0039] The first terminal of capacitor C1 receives a reference voltage Vb11 via switch SW6 and an input signal Vip via switch SW7; the second terminal of capacitor C1 receives a reference voltage Vb12 via switch SW8 and is coupled to node g1 via switch SW9. The first terminal of capacitor C2 receives a reference voltage Vb11 via switch SW10 and an input signal Vin via switch SW11; the second terminal of capacitor C2 receives a reference voltage Vb12 via switch SW12 and is coupled to node g2 via switch SW13.
[0040] Switches SW6, SW7, SW8, SW9, SW10, SW11, SW12, and SW13 operate according to clock CK. More specifically, when clock CK is at the first level (e.g., high level or logic 1), switches SW6, SW8, SW10, and SW12 are turned on, while switches SW7, SW9, SW11, and SW13 are turned off; when clock CK is at the second level (e.g., low level or logic 0), switches SW6, SW8, SW10, and SW12 are turned off, while switches SW7, SW9, SW11, and SW13 are turned on. In other words, capacitors C1 / C2 charge during the reset phase of amplifier circuit 500 and couple the input signals Vip / Vin to nodes g1 / g2 respectively during the amplification phase of amplifier circuit 500. Therefore, the bias voltages Vbias1 (=Vb12-Vb11+Vip) and Vbias2 (=Vb12-Vb11+Vin) can be expressed as the results of operations on the input signals Vip and Vin and the DC voltage (Vb12-Vb11), respectively. In other words, during the amplification stage, the control terminal of transistor M1 (or transistor M2) receives not only the input signal Vip (or input signal Vin) but also the DC voltage.
[0041] This DC voltage can enable transistors M1 and M2 to turn on earlier. For example, when transistors M1 and M2 are PMOS transistors, this DC voltage can be negative (i.e., Vb12 < Vb11). Furthermore, this DC voltage helps overcome variations in temperature, voltage, and process technology. For example, (1) when the second reference voltage VDD is lower than the designed value, reducing the voltage at the control terminals of transistors M1 and M2 can make them turn on more easily; and (2) when the threshold voltages of transistors M1 and M2 change due to temperature variations or process variations, this DC voltage can be adjusted to change the source-gate voltages of transistors M1 and M2, making them turn on more easily.
[0042] Figure 7 This is a circuit diagram of one embodiment of bias circuit 510. Bias circuit 510b is similar to bias circuit 510a, except that: the first terminal of capacitor C1 receives a reference voltage Vb12 through switch SW7, the second terminal of capacitor C1 receives an input signal Vip through switch SW8, the first terminal of capacitor C2 receives a reference voltage Vb12 through switch SW11, and the second terminal of capacitor C2 receives an input signal Vin through switch SW12. Figure 7 In the embodiment, the bias voltage Vbias1 is also equal to Vb12-Vb11+Vip, and the bias voltage Vbias2 is also equal to Vb12-Vb11+Vin.
[0043] Figure 8 This is a circuit diagram of another embodiment of the amplifier circuit of the present invention. Amplifier circuit 800 is similar to amplifier circuit 300, except that amplifier circuit 800 also includes a bias circuit 810. The bias circuit 810 generates bias voltages Vbias1, Vbias2, Vbias3, and Vbias4 at nodes g1, g2, g3, and g4 respectively, based on the input signal Vip, the input signal Vin, and the reference voltages Vb11, Vb12, Vb21, and Vb22. Node g3 is the control terminal of transistor M10, and node g4 is the control terminal of transistor M11.
[0044] Figure 9This is a circuit diagram of one embodiment of the bias circuit 810. The bias circuit 810a includes capacitors C1, C2, C3, and C4, and switches SW6, SW7, SW8, SW9, SW10, SW11, SW12, SW13, SW16, SW17, SW18, SW19, SW20, SW21, SW22, and SW23.
[0045] Please refer to the information regarding capacitors C1 and C2. Figure 6 The following is an explanation: The first terminal of capacitor C3 receives the reference voltage Vb21 via switch SW16 and the input signal Vip via switch SW17; the second terminal of capacitor C3 receives the reference voltage Vb22 via switch SW18 and is coupled to node g3 via switch SW19. The first terminal of capacitor C4 receives the reference voltage Vb21 via switch SW20 and the input signal Vin via switch SW21; the second terminal of capacitor C4 receives the reference voltage Vb22 via switch SW22 and is coupled to node g4 via switch SW23.
[0046] Figure 10 This is a circuit diagram of one embodiment of the bias circuit 810. The bias circuit 810b is similar to the bias circuit 810a. Those skilled in the art can understand the differences between the bias circuits 810a and 810b from the differences between the bias circuits 810a and 810b, so it will not be described again.
[0047] exist Figure 9 and Figure 10In this circuit, switches SW16, SW17, SW18, SW19, SW20, SW21, SW22, and SW23 operate according to clock CK. More specifically, when clock CK is at the first level (e.g., high level or logic 1), switches SW16, SW18, SW20, and SW22 are turned on, while switches SW17, SW19, SW21, and SW23 are turned off; when clock CK is at the second level (e.g., low level or logic 0), switches SW16, SW18, SW20, and SW22 are turned off, while switches SW17, SW19, SW21, and SW23 are turned on. In other words, capacitors C3 / C4 charge during the reset phase of amplifier circuit 800 and couple the input signals Vip / Vin to nodes g3 / g4 respectively during the amplification phase of amplifier circuit 800. Therefore, the bias voltages Vbias3 (=Vb22-Vb21+Vip) and Vbias4 (=Vb22-Vb21+Vin) can be expressed as the results of operations on the input signal Vip and the input signal Vin, respectively, and the DC voltage (Vb22-Vb21). In other words, during the amplification stage, the control terminal of transistor M10 (or transistor M11) receives not only the input signal Vip (or the input signal Vin) but also the DC voltage.
[0048] Figure 11 This is a comparison graph showing the operating speed of the amplifier circuits in this case. Curve Cv4 is equivalent to the clock CK; curve Cv5 corresponds to amplifier circuit 500; and curve Cv6 corresponds to amplifier circuit 200. When the clock CK transitions from the first level to the second level (i.e., time point t1), amplifier circuits 200 and 500 enter the amplification stage from the reset stage. Amplifier circuit 500 outputs an amplified signal at time point t2, while amplifier circuit 200 outputs an amplified signal at time point t3. Therefore, it can be seen that the bias circuit 510 can significantly improve the operating speed of the amplifier circuit. Similarly, the bias circuit 810 can also significantly improve the operating speed of the amplifier circuit.
[0049] The aforementioned amplifier circuits 200, 300, 500 and 800 can be used as preamplifiers for comparators, but are not limited thereto.
[0050] In other embodiments, the PMOS transistor and NMOS transistor in the foregoing embodiments can be replaced by NMOS transistors and PMOS transistors respectively. Those skilled in the art know how to adjust the clock CK and the reference voltage accordingly to achieve the above-described implementation.
[0051] Please note that the shapes, sizes, and proportions of the components in the aforementioned illustrations are merely illustrative and intended to help those skilled in the art understand the invention, and are not intended to limit the invention.
[0052] Although the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention. Those skilled in the art can make changes to the technical features of the present invention based on the explicit or implicit content of the present invention. All such changes may fall within the scope of patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be determined by the scope of the patent application in this specification.
[0053] [Symbol Explanation]
[0054] 100, 200, 300, 500, 800: Amplifier circuits
[0055] 101, 102, 103, 104, 105, M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13: Transistors
[0056] Vip, Vin: Input signals
[0057] Di-, Di+: Output terminals
[0058] CK: Clock
[0059] SW1, SW2, SW3, SW4, SW5, SW6, SW7, SW8, SW9, SW10, SW11, SW12, SW13, SW14, SW15, SW16, SW17, SW18, SW19, SW20, SW21, SW22, SW23: Switches
[0060] GND, VDD, Vb11, Vb12, Vb21, Vb22: Reference voltages
[0061] SA1: First Amplification Stage
[0062] SA2: Second Amplification Stage
[0063] N1, N2, N3, N4, g1, g2, g3, g4: Nodes
[0064] SA3: Third Amplification Stage
[0065] Cv1, Cv2, Cv3, Cv4, Cv5, Cv6: Curves
[0066] 510, 510a, 510b, 810, 810a, 810b: Bias circuit
[0067] Vbias1, Vbias2, Vbias3, Vbias4: Bias voltage
[0068] C1, C2, C3, C4: Capacitors
[0069] t1, t2, t3: time points.
Claims
1. An amplifier circuit having a first output terminal and a second output terminal, comprising: A first transistor has a first terminal, a second terminal, and a first control terminal, wherein The second terminal is coupled to the first output terminal; A second transistor has a third terminal, a fourth terminal and a second control terminal, wherein the fourth terminal is coupled to the second output terminal; A third transistor has a fifth terminal, a sixth terminal and a third control terminal, wherein the sixth terminal is coupled to the first terminal and the third control terminal receives a first input signal; A fourth transistor has a seventh terminal, an eighth terminal and a fourth control terminal, wherein the seventh terminal is coupled to the fifth terminal, the eighth terminal is coupled to the third terminal, and the fourth control terminal receives a second input signal. A fifth transistor has a nineteenth terminal, a twentieth terminal and a fifth control terminal, wherein the nineteenth terminal is coupled to the second terminal and the twentieth terminal is coupled to the first output terminal. A sixth transistor has a twenty-first terminal, a twenty-second terminal and a sixth control terminal, wherein the twenty-first terminal is coupled to the fourth terminal and the twenty-second terminal is coupled to the second output terminal; A first switch has a ninth terminal and a tenth terminal, wherein the ninth terminal is coupled to a first reference voltage and the tenth terminal is coupled to the first output terminal. A second switch has an eleventh terminal and a twelfth terminal, wherein the eleventh terminal is coupled to the first reference voltage and the twelfth terminal is coupled to the second output terminal; A third switch has a thirteenth terminal and a fourteenth terminal, wherein the thirteenth terminal is coupled to the first reference voltage, and the fourteenth terminal is coupled to the first terminal and the sixth terminal; A fourth switch having a fifteenth terminal and a sixteenth terminal, wherein the fifteenth terminal is coupled to the first reference voltage, and the sixteenth terminal is coupled to the third terminal and the eighth terminal; and A fifth switch has a seventeenth terminal and an eighteenth terminal, wherein the seventeenth terminal is coupled to a second reference voltage, and the eighteenth terminal is coupled to the fifth terminal and the seventh terminal; A sixth switch having a twenty-third terminal and a twenty-fourth terminal, wherein the twenty-third terminal is coupled to the first reference voltage, and the twenty-fourth terminal is coupled to the second terminal and the nineteenth terminal; and A seventh switch has a twenty-fifth terminal and a twenty-sixth terminal, wherein the twenty-fifth terminal is coupled to the first reference voltage, and the twenty-sixth terminal is coupled to the fourth terminal and the twenty-first terminal; The first input signal and the second input signal are a pair of differential input signals, and the first output terminal and the second output terminal output a pair of differential output signals.
2. The amplifier circuit according to claim 1, further comprising: A bias circuit generates a first bias voltage and a second bias voltage based on a third reference voltage, a fourth reference voltage, the first input signal, and the second input signal. wherein The first bias voltage is the result of the calculation of the first input signal, the third reference voltage, and the fourth reference voltage. The second bias voltage is the result of the calculation of the second input signal, the third reference voltage, and the fourth reference voltage. The first control terminal receives the first bias voltage, and the second control terminal receives the second bias voltage.
3. The amplifier circuit of claim 2, wherein, When the first switch, the second switch, the third switch, and the fourth switch are on, the fifth switch is not on; and when the first switch, the second switch, the third switch, and the fourth switch are not on, the fifth switch is on.
4. The amplifier circuit of claim 1, wherein, The first control terminal receives the first input signal, and the second control terminal receives the second input signal.
5. The amplifier circuit according to claim 1, further comprising: A bias circuit generates a first bias voltage, a second bias voltage, a third bias voltage, and a fourth bias voltage based on a third reference voltage, a fourth reference voltage, a fifth reference voltage, a sixth reference voltage, the first input signal, and the second input signal. wherein The first bias voltage is the result of the calculation of the first input signal, the third reference voltage, and the fourth reference voltage. The second bias voltage is the result of the calculation of the second input signal, the third reference voltage, and the fourth reference voltage. The third bias voltage is the result of the calculation of the first input signal, the fifth reference voltage, and the sixth reference voltage. The fourth bias voltage is the result of the calculation of the second input signal, the fifth reference voltage, and the sixth reference voltage. The first control terminal receives the first bias voltage, the second control terminal receives the second bias voltage, the fifth control terminal receives the third bias voltage, and the sixth control terminal receives the fourth bias voltage.
6. The amplifier circuit of claim 5, wherein, When the first switch, the second switch, the third switch, the fourth switch, the sixth switch, and the seventh switch are on, the fifth switch is not on; and when the first switch, the second switch, the third switch, the fourth switch, the sixth switch, and the seventh switch are not on, the fifth switch is on.
7. The amplifier circuit of claim 1, wherein, The first control terminal and the fifth control terminal receive the first input signal, while the second control terminal and the sixth control terminal receive the second input signal.
8. An amplifier circuit that outputs a pair of differential output signals through a first output terminal and a second output terminal, comprising: A first amplification stage is electrically connected to a first node and a second node to amplify a pair of differential input signals; A second amplification stage is electrically connected to the first node and the second node, and coupled to the first output terminal and the second output terminal; A third amplification stage is electrically connected to a third node and a fourth node, and coupled to the first output terminal and the second output terminal; A first switch is coupled between the first output terminal and a first reference voltage; A second switch is coupled between the second output terminal and the first reference voltage; A third switch is coupled between the first node and the first reference voltage; A fourth switch is coupled between the second node and the first reference voltage; A fifth switch is coupled between a second reference voltage and the first amplification stage; A sixth switch is coupled between the third node and the first reference voltage; as well as A seventh switch is coupled between the fourth node and the first reference voltage; The second amplification stage is further electrically connected to the third node and the fourth node.