Multilayer electronic component

Abstract

This invention provides a multilayer electronic component. The electronic component includes a multilayer and a first to a fourth inductor. A second inductor is disposed in front of the first inductor in the -Y direction. A third and a fourth inductor are disposed in front of the first and second inductors, respectively, in the -X direction. Near the ends of the long side of the conductor layer of each of the first and fourth inductors, two or more rows of vias are connected in parallel. Near the ends of the long side of the conductor layer of each of the second and third inductors, one row of vias is connected.

Description

Technical Field

[0001] This invention relates to a stacked electronic component comprising multiple inductors. Background Technology

[0002] In small mobile communication devices, the following structure is widely used: an antenna is set up in the system and used by multiple applications with different frequency bands, and the multiple signals transmitted and received by the antenna are separated by a wavelength divider.

[0003] Typically, a wavelength division multiplexing (WDM) that separates a first signal at a frequency within a first frequency band and a second signal at a frequency within a second frequency band higher than the first frequency band includes: a common port; a first signal port; a second signal port; a first filter disposed on the first signal path from the common port to the first signal port; and a second filter disposed on the second signal path from the common port to the second signal port. For example, an LC resonator composed of an inductor and a capacitor can be used as the first and second filters.

[0004] As a wavelength divider, there are known wavelength dividers that use a stack of multiple dielectric layers, as disclosed in Chinese Patent Application Publication No. 107408932A. Additionally, as an inductor used in an LC resonator, there are known inductors that have via-hole conductors connected to both ends of a conductor layer, as disclosed in Chinese Patent Application Publication No. 107408932A, and inductors that have one or two via-hole conductors connected to both ends of a conductor layer, as disclosed in Chinese Patent Application Publication No. 109643977A.

[0005] In recent years, the market has demanded miniaturization and space-saving design for small mobile communication devices, which also necessitates the miniaturization of the demultiplexers used in these devices. When demultiplexers are miniaturized and inductors are reduced in size, the Q-value of the inductors decreases. To address this, Chinese Patent Application Publication No. 109643977A describes a method to increase the Q-value of the inductor by connecting multiple via conductors to one end of the conductor layer. However, connecting multiple via conductors to one end of the conductor layer for all inductors included in the demultiplexer, as described in Chinese Patent Application Publication No. 109643977A, results in a larger demultiplexer.

[0006] The aforementioned problems are not limited to splitters; all stacked electronic components that include multiple inductors suffer from these issues. Summary of the Invention

[0007] The object of this invention is to provide a stacked electronic component that can be miniaturized while increasing the Q value of the inductor.

[0008] The stacked electronic component of the present invention includes: a stack comprising a plurality of stacked dielectric layers; a first inductor integrated with the stack and wound about a first axis orthogonal to the stacking direction of the plurality of dielectric layers; a second inductor integrated with the stack and wound about a second axis orthogonal to the stacking direction; a third inductor integrated with the stack and wound about a third axis orthogonal to the stacking direction; and a fourth inductor integrated with the stack and wound about a fourth axis orthogonal to the stacking direction. The second inductor is disposed in front of the first inductor in the first direction orthogonal to the stacking direction. The third and fourth inductors are disposed in front of the first and second inductors, respectively, in a second direction orthogonal to both the stacking direction and the first direction.

[0009] The first and fourth inductors each include a plurality of first via rows and at least one first conductor layer. The second and third inductors each include a plurality of second via rows and at least one second conductor layer. The plurality of first via rows and the plurality of second via rows are each formed by connecting two or more vias in series. The at least one first conductor layer and the at least one second conductor layer each include at least one conductor layer. Near the two ends of the at least one first conductor layer in the long direction, two or more first via rows are connected in parallel. Near the two ends of the at least one second conductor layer in the long direction, one second via row is connected.

[0010] In the stacked electronic component of the present invention, the first axis and the fourth axis may be parallel to each other.

[0011] Furthermore, in the stacked electronic component of the present invention, the direction parallel to the second axis and the direction parallel to the fourth axis may be orthogonal to each other.

[0012] Alternatively, in the stacked electronic component of the present invention, the first inductor may include a conductor portion wound less than one turn around a first axis. Alternatively, the fourth inductor may include: a plurality of first conductor portions, each wound less than one turn around a fourth axis; and at least one first connection portion connecting the plurality of first conductor portions in series.

[0013] Alternatively, in the stacked electronic component of the present invention, the second inductor may include: a plurality of second conductor portions, each wound less than one turn around a second axis; and at least one second connection portion connecting the plurality of second conductor portions in series.

[0014] Furthermore, in the stacked electronic component of the present invention, the third axis and the fourth axis may be parallel to each other. In this case, the area of ​​the region obtained by vertically projecting the first space containing the third axis and enclosed by the third inductor onto a virtual plane perpendicular to the third axis may be greater than the area of ​​the region obtained by vertically projecting the second space containing the fourth axis and enclosed by the fourth inductor onto a virtual plane perpendicular to the fourth axis.

[0015] Alternatively, the stacked electronic component of the present invention may further include: a common port; a first signal port; a second signal port; a first filter disposed between the common port and the first signal port, comprising a first inductor and a second inductor, for selectively allowing a first signal of a frequency within a first passband to pass through; and a second filter disposed between the common port and the second signal port, comprising a third inductor and a fourth inductor, for selectively allowing a second signal of a frequency within a second passband to pass through. In this case, the first inductor may be positioned closer to the first signal port from a circuit structure perspective than the second inductor. Additionally, in the pass-through attenuation characteristics of the first filter, the attenuation pole formed by the first inductor may be closer to the first passband than the attenuation pole formed by the second inductor. Furthermore, in this case, the fourth inductor may be positioned closer to the common port from a circuit structure perspective than the third inductor. Additionally, in the pass-through attenuation characteristics of the second filter, the attenuation pole formed by the fourth inductor may be closer to the second passband than the attenuation pole formed by the third inductor.

[0016] In the multilayer electronic component of the present invention, a second inductor is disposed in front of the first inductor in a first direction. A third inductor and a fourth inductor are disposed in front of the first inductor and the second inductor, respectively, in a second direction. Furthermore, in the present invention, two or more first via arrays are connected in parallel near both ends of the long side of the first conductor layer of each of the first and fourth inductors. A second via array is connected near both ends of the long side of the second conductor layer of each of the second and third inductors. Therefore, according to the present invention, the multilayer electronic component can be miniaturized while increasing the Q value of the inductor.

[0017] Other objects, features and advantages of the present invention will become fully apparent from the following description. Attached Figure Description

[0018] Figure 1 This is a circuit diagram illustrating the circuit structure of a stacked electronic component according to one embodiment of the present invention.

[0019] Figure 2 This is a circuit diagram illustrating the circuit structure of a stacked electronic component according to one embodiment of the present invention.

[0020] Figure 3 This is a perspective view showing the appearance of a stacked electronic component according to one embodiment of the present invention.

[0021] Figures 4A to 4C This is an explanatory diagram showing the pattern formation surface of the dielectric layers of the first to third layers in a stacked body of a stacked electronic component according to one embodiment of the present invention.

[0022] Figures 5A to 5C This is an explanatory diagram showing the pattern formation surface of the dielectric layers of layers 4 to 6 in a laminated electronic component according to one embodiment of the present invention.

[0023] Figures 6A to 6C This is an explanatory diagram showing the pattern formation surface of the dielectric layers of layers 7 to 9 in a laminated electronic component according to one embodiment of the present invention.

[0024] Figures 7A to 7C This is an explanatory diagram showing the pattern formation surface of the dielectric layers of layers 10 to 12 in a laminated electronic component according to one embodiment of the present invention.

[0025] Figure 8A This is an explanatory diagram showing the pattern formation surface of the dielectric layer of the 13th layer in a stacked electronic component according to one embodiment of the present invention.

[0026] Figure 8B This is an explanatory diagram showing the pattern formation surface of the dielectric layers of layers 14 to 21 in a stacked body of a stacked electronic component according to one embodiment of the present invention.

[0027] Figure 8C This is an explanatory diagram showing the pattern formation surface of the dielectric layer of the 22nd layer in a stacked electronic component according to one embodiment of the present invention.

[0028] Figure 9A and Figure 9B This is an explanatory diagram showing the pattern formation surfaces of the dielectric layers of the 23rd and 24th layers in a laminated electronic component according to one embodiment of the present invention.

[0029] Figure 10 This is a perspective view showing the interior of a stack of stacked electronic components according to one embodiment of the present invention.

[0030] Figure 11 This is a perspective view showing the interior of a stack of stacked electronic components according to one embodiment of the present invention.

[0031] Figure 12 It means Figure 10 and Figure 11 A side view of a portion of the interior of the stacked body shown.

[0032] Figure 13 It means Figure 10 and Figure 11 A side view of a portion of the interior of the stacked body shown.

[0033] Figure 14 It means Figure 10 and Figure 11 A side view of a portion of the interior of the stacked body shown.

[0034] Figure 15 It means Figure 10 and Figure 11 A side view of a portion of the interior of the stacked body shown.

[0035] Figure 16 It means Figure 10 and Figure 11 A top view of a portion of the interior of the stacked structure shown.

[0036] Figure 17 It means Figure 10 and Figure 11 A top view of a portion of the interior of the stacked structure shown.

[0037] Figure 18 This is a characteristic diagram illustrating the attenuation characteristics between a common port and a first signal port in a stacked electronic component according to one embodiment of the present invention.

[0038] Figure 19 This is a characteristic diagram illustrating the attenuation characteristics between a common port and a second signal port in a stacked electronic component according to one embodiment of the present invention. Detailed Implementation

[0039] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. First, referring to... Figure 1 A summary description of the structure of a stacked electronic component (hereinafter simply referred to as electronic component) 1 according to one embodiment of the present invention will be provided. Figure 1 In the example of electronic component 1, a demultiplexer (duplexer) is shown. The demultiplexer includes: a first filter 10 for selectively passing a first signal with a frequency within a first passband; and a second filter 20 for selectively passing a second signal with a frequency within a second passband higher than the first passband.

[0040] Electronic component 1 further includes: a common port 2; a first signal port 3; a second signal port 4; a first signal path 5 connecting the common port 2 and the first signal port 3; and a second signal path 6 connecting the common port 2 and the second signal port 4. The first filter 10, from a circuit structure perspective, is disposed between the common port 2 and the first signal port 3. The second filter 20, from a circuit structure perspective, is disposed between the common port 2 and the second signal port 4. The first signal path 5 is the path from the common port 2 through the first filter 10 to the first signal port 3. The second signal path 6 is the path from the common port 2 through the second filter 20 to the second signal port 4.

[0041] A first signal with a frequency within the first passband is selectively passed through a first signal path 5 equipped with a first filter 10. A second signal with a frequency within the second passband is selectively passed through a second signal path 6 equipped with a second filter 20. In this way, the electronic component 1 can separate the first signal and the second signal.

[0042] Next, refer to Figure 1 An example of the structure of the first filter 10 will be described. The first filter 10 includes inductors L11, L12, and L13 and capacitors C11, C12, C13, C14, C15, and C16. Inductors L11 and L12 are arranged on the first signal path 5 from a circuit structure perspective. Furthermore, inductor L11 is positioned closer to the first signal port 3 than inductor L12 from a circuit structure perspective. One end of inductor L11 is connected to the first signal port 3. The other end of inductor L11 is connected to one end of inductor L12. The other end of inductor L12 is connected to the common port 2.

[0043] Capacitor C11 is connected in parallel with inductor L11. Capacitor C12 is connected in parallel with inductor L12. One end of capacitor C13 is connected to one end of inductor L11. The other end of capacitor C13 is connected to the other end of inductor L12.

[0044] One end of capacitor C14 is connected to one end of inductor L11. One end of capacitor C15 is connected to the junction of inductors L11 and L12. The other ends of capacitors C14 and C15 are connected to one end of inductor L13. The other end of inductor L13 is connected to ground. Capacitor C16 is connected in parallel with inductor L13. From a circuit structure perspective, inductor L13 is positioned between the first signal path 5 and ground.

[0045] Next, refer to Figure 2An example of the structure of the second filter 20 is described below. The second filter 20 includes inductors L21 and L22 and capacitors C21, C22, C23, C24, C25, C26, C27, C28, C29, C30, and C31. One end of capacitor C21 is connected to the second signal port 4. The other end of capacitor C21 is connected to one end of capacitor C22. The other end of capacitor C22 is connected to one end of capacitor C23. The other end of capacitor C23 is connected to the common port 2.

[0046] One end of capacitor C24 is connected to one end of capacitor C21. The other end of capacitor C24 is connected to the other end of capacitor C22. One end of capacitor C25 is connected to the junction of capacitors C22 and C23.

[0047] From a circuit structure perspective, inductor L21 is positioned between the second signal path 6 and the ground line. Inductor L21 includes inductor portions 211 and 212. One end of inductor portion 211 is connected to the connection point of capacitors C21 and C22. The other end of inductor portion 211 is connected to one end of inductor portion 212. The other end of inductor portion 212 is connected to the ground line.

[0048] From a circuit structure perspective, inductor L22 is positioned between the second signal path 6 and the ground line. Furthermore, from a circuit structure perspective, inductor L22 is positioned closer to the common port 2 than inductor L21. Inductor L22 includes inductor portions 221 and 222. One end of inductor portion 221 is connected to the other end of capacitor C25. The other end of inductor portion 221 is connected to one end of inductor portion 222. The other end of inductor portion 222 is connected to the ground line.

[0049] The inductor portion 211 of inductor L21 and the inductor portion 221 of inductor L22 are magnetically coupled to each other. The inductor portion 212 of inductor L21 and the inductor portion 222 of inductor L22 are not magnetically coupled to each other.

[0050] Capacitor C26 is connected in parallel with the inductor portion 211 of inductor L21. Capacitor C27 is connected in parallel with the inductor portion 212 of inductor L21. One end of capacitor C28 is connected to one end of inductor portion 211. The other end of capacitor C28 is connected to the other end of inductor portion 212.

[0051] Capacitor C29 is connected in parallel with the inductor portion 221 of inductor L22. Capacitor C30 is connected in parallel with the inductor portion 222 of inductor L22. One end of capacitor C31 is connected to one end of inductor portion 221. The other end of capacitor C31 is connected to the other end of inductor portion 222.

[0052] Next, refer to Figure 3 The other structures of electronic component 1 will be described. Figure 3 This is a perspective view showing the appearance of electronic component 1.

[0053] Electronic component 1 also includes a laminate 50, which comprises multiple stacked dielectric layers and multiple conductors. The laminate 50 integrates the common port 2, the first signal port 3, the second signal port 4, inductors L11, L12, L13, L21, L22, and capacitors C11-C16, C21-C31. The first filter 10 and the second filter 20 are each constructed using multiple conductors.

[0054] The laminate 50 has: a bottom surface 50A and a top surface 50B located at both ends of the lamination direction T of the plurality of dielectric layers; and four side surfaces 50C to 50F connecting the bottom surface 50A and the top surface 50B. Side surfaces 50C and 50D face opposite sides to each other, and side surfaces 50E and 50F also face opposite sides to each other. Side surfaces 50C to 50F are perpendicular to the top surface 50B and the bottom surface 50A.

[0055] Here, as Figure 3 The X, Y, and Z directions are defined as shown. The X, Y, and Z directions are orthogonal to each other. In this embodiment, the direction parallel to the stacking direction T is designated as the Z direction. Furthermore, the direction opposite to the X direction is designated as the -X direction, the direction opposite to the Y direction is designated as the -Y direction, and the direction opposite to the Z direction is designated as the -Z direction.

[0056] like Figure 3 As shown, bottom surface 50A is located at the end of the laminate 50 in the -Z direction. Top surface 50B is located at the end of the laminate 50 in the Z direction. Both bottom surface 50A and top surface 50B are rectangular shapes, with the longer side surface in the X direction. Side surface 50C is located at the end of the laminate 50 in the -X direction. Side surface 50D is located at the end of the laminate 50 in the X direction. Side surface 50E is located at the end of the laminate 50 in the -Y direction. Side surface 50F is located at the end of the laminate 50 in the Y direction.

[0057] The planar shape of the laminate 50, viewed from the Z direction, i.e., the shape of the bottom surface 50A (the shape of the top surface 50B), is rectangular. The long side of this rectangle is parallel to the X direction, and the short side of this rectangle is parallel to the Y direction.

[0058] Electronic component 1 further includes: signal terminals 112, 113, and 114 disposed on the bottom surface 50A of the laminate 50; and grounding terminals 111, 115, 116, 117, 118, and 119 connected to a ground wire. Grounding terminal 111 is disposed near a corner where the bottom surface 50A, side surface 50D, and side surface 50E intersect. Signal terminal 113 is disposed near a corner where the bottom surface 50A, side surface 50D, and side surface 50F intersect. Signal terminal 114 is disposed near a corner where the bottom surface 50A, side surface 50C, and side surface 50F intersect. Grounding terminal 115 is disposed near a corner where the bottom surface 50A, side surface 50C, and side surface 50E intersect.

[0059] Signal terminal 112 is positioned between grounding terminal 111 and grounding terminal 115. Grounding terminal 116 is positioned between grounding terminal 111 and signal terminal 113. Grounding terminal 117 is positioned between signal terminal 113 and signal terminal 114. Grounding terminal 118 is positioned between signal terminal 114 and grounding terminal 115. Grounding terminal 119 is positioned at the center of the bottom surface 50A.

[0060] Signal terminal 112 corresponds to common port 2, signal terminal 113 corresponds to first signal port 3, and signal terminal 114 corresponds to second signal port 4. Therefore, common port 2, first signal port 3, and second signal port 4 are disposed on the bottom surface 50A of the laminate 50.

[0061] Next, refer to Figures 4A to 9B An example of the plurality of dielectric layers and the plurality of conductor layers constituting the laminate 50 will be described. In this example, the laminate 50 has 24 dielectric layers stacked together. Hereinafter, these 24 dielectric layers will be referred to as dielectric layers 1 to 24 from bottom to top. In addition, the dielectric layers 1 to 24 will be indicated by reference numerals 51 to 74 in the accompanying drawings.

[0062] exist Figures 4A to 8C In the diagram, multiple circles represent multiple through-holes. Multiple through-holes are formed in each of the dielectric layers 51-72. Each through-hole is formed by filling the holes with conductive paste. Each through-hole is connected to a conductor layer or other through-holes.

[0063] Figure 4A This indicates the patterned surface of the first dielectric layer 51. Terminals 111 to 119 are formed on the patterned surface of the dielectric layer 51. Figure 4B This indicates the patterned surface of the second dielectric layer 52. Conductor layers 521, 522, 523, 524, and 525 are formed on the patterned surface of the dielectric layer 52.

[0064] Figure 4CThis indicates the patterned surface of the third dielectric layer 53. Conductor layers 531, 532, 533, 534, 535, 536, 537, 538, 539, 5310, 5311, and 5312 are formed on the patterned surface of the dielectric layer 53. One end of conductor layer 531 is connected to conductor layer 5311. The other end of conductor layer 531 is connected to conductor layer 5312. Figure 4C In the diagram, dashed lines represent the boundaries between conductor layer 531 and conductor layer 5311, as well as the boundaries between conductor layer 531 and conductor layer 5312.

[0065] Figure 5A This indicates the patterned surface of the fourth dielectric layer 54. Conductor layers 541, 542, 543, 544, 545, 546, 547, and 548 are formed on the patterned surface of the dielectric layer 54. Conductor layers 541 and 543 are connected to conductor layer 542. Figure 5B This indicates the patterned surface of the fifth dielectric layer 55. Conductor layers 551, 552, 553, and 554 are formed on the patterned surface of the dielectric layer 55. Conductor layer 554 is connected to conductor layer 553. Figure 5C This indicates the patterned surface of the sixth dielectric layer 56. Conductor layers 561 and 562 are formed on the patterned surface of the dielectric layer 56.

[0066] Figure 6A This indicates the patterned surface of the 7th dielectric layer 57. Conductor layers 571 and 572 are formed on the patterned surface of the dielectric layer 57. Conductor layer 572 is connected to conductor layer 571. Figure 6B This indicates the patterned surface of the 8th dielectric layer 58. No conductor layer is formed on the patterned surface of the dielectric layer 58. Figure 6C This indicates the patterned surface of the 9th dielectric layer 59. A conductor layer 591 is formed on the patterned surface of the dielectric layer 59.

[0067] Figure 7A This indicates the patterned surface of the 10th dielectric layer 60. A conductor layer 601 is formed on the patterned surface of the dielectric layer 60. Figure 7B This indicates the patterned surface of the 11th dielectric layer 61. No conductor layer is formed on the patterned surface of the dielectric layer 61. Figure 7C This indicates the patterning surface of the 12th dielectric layer 62. Conductor layers 621 and 622 are formed on the patterning surface of the dielectric layer 62. The conductor layers 621 and 622 can have the same shape when viewed from a direction parallel to the stacking direction T (Z direction).

[0068] Figure 8AThis indicates the patterning surface of the 13th dielectric layer 63. Conductor layers 631 and 632 are formed on the patterning surface of the dielectric layer 63. The conductor layers 631 and 632 can have the same shape when viewed from a direction parallel to the stacking direction T (Z direction). Figure 8B This indicates the patterning surfaces of dielectric layers 64-71, layers 14 to 21. No conductor layers are formed on the patterning surfaces of dielectric layers 64-71. Figure 8C This indicates the patterning surface of the 22nd dielectric layer 72. Conductor layers 721, 722, 723, 724, 725, 726, and 727 are formed on the patterning surface of the dielectric layer 72. Conductor layers 722, 723, and 724 can have the same shape when viewed from a direction parallel to the stacking direction T (Z direction). Conductor layers 726 and 727 can have the same shape when viewed from a direction parallel to the stacking direction T (Z direction).

[0069] Figure 9A This indicates the patterning surface of the 23rd dielectric layer 73. Conductor layers 731, 732, 733, 734, 735, 736, and 737 are formed on the patterning surface of the dielectric layer 73. Conductor layers 732, 733, and 734 can have the same shape when viewed from a direction parallel to the stacking direction T (Z direction). Conductor layers 736 and 737 can have the same shape when viewed from a direction parallel to the stacking direction T (Z direction). Figure 9B This indicates the patterned surface of the 24th dielectric layer 74. A mark 741 composed of a conductor layer is formed on the patterned surface of the dielectric layer 74.

[0070] Figure 2 The stack 50 shown is constructed by stacking dielectric layers 51 to 74 of layers 1 to 24, such that the pattern-forming surface of dielectric layer 51 of layer 1 becomes the bottom surface 50A of the stack 50, and the surface of dielectric layer 74 of layer 24 opposite to the pattern-forming surface becomes the upper surface 50B of the stack 50.

[0071] Figures 4A to 8C Each of the multiple vias shown is connected to a conductor layer overlapping in the stacking direction T or other vias overlapping in the stacking direction T when the dielectric layers 51 to 72 of layers 1 to 22 are stacked. Additionally, Figures 4A to 8C The through-hole shown, located inside the terminal or the conductor layer, is connected to the terminal or the conductor layer.

[0072] Figure 10 and Figure 11 This refers to the interior of the laminate 50, which is formed by stacking dielectric layers 51 to 74, from layer 1 to layer 24. For example... Figure 10 and Figure 11As shown, inside the laminate 50, Figures 4A to 9A The diagram shows a stack of multiple conductor layers and multiple vias. Furthermore, in... Figure 10 and Figure 11 The mark 741 has been omitted.

[0073] The laminate 50 can be made of ceramic, for example, the dielectric layers 51-74, and manufactured by a low-temperature simultaneous firing method. In this case, firstly, multiple ceramic green sheets that will later become dielectric layers 51-74 are fabricated. Multiple pre-firing conductor layers that will later become multiple conductor layers and multiple pre-firing through-holes that will later become multiple through-holes are formed on each ceramic green sheet. Next, the multiple ceramic green sheets are stacked to form a green sheet laminate. Then, the green sheet laminate is cut to form a pre-firing laminate. Finally, the ceramic and conductors in the pre-firing laminate are fired through a low-temperature simultaneous firing process to complete the laminate 50.

[0074] Next, refer to Figures 4A to 15 The structure of inductors L11, L12, L13, L21, and L22 is described in detail. Figures 12-15 This is a side view showing a portion of the interior of the stacked body 50. Figure 12 This represents a portion of the interior of the stacked body 50 as viewed from the side 50D, primarily showing inductors L11, L12, and L13. Figure 13 This represents a portion of the interior of the stacked body 50 as viewed from the side 50E, primarily showing inductors L12, L13, and L22. Figure 14 This represents a portion of the interior of the stacked body 50 as viewed from the side 50C, primarily showing inductors L21 and L22. Figure 15 This represents a portion of the interior of the stacked body 50 as viewed from the side 50F, primarily showing inductors L11 and L21.

[0075] Inductors L11, L12, L13, L21, and L22 are each integrated with the laminate 50. As described later, each of inductors L11, L12, L21, and L22 includes multiple via rows. Each of the multiple via rows is formed by connecting two or more vias arranged in the lamination direction T in series.

[0076] First, the structure of inductor L11 will be explained. For example... Figure 12 and Figure 15 As shown, inductor L11 is wound around axis A11, which is parallel to a direction orthogonal to the stacking direction T. In this embodiment, in particular, axis A11 extends in a direction parallel to the Y direction.

[0077] Additionally, inductor L11 includes a conductor portion wound less than one turn around axis A11. The conductor portion of inductor L11 includes conductor layer 11C1 (see reference). Figure 10 and Figure 11 The conductor layer 11C1 has a shape that is longer in a direction parallel to the X direction. The conductor layer 11C1 includes conductor layers 721 and 731 (see reference) that are arranged at different positions in the stacking direction T and connected in parallel by four through holes. Figure 8C and Figure 9A Conductor layers 721 and 731 each extend in a direction parallel to the X direction.

[0078] The conductor portion of inductor L11 also includes two via rows 11T1 and two via rows 11T2 (see reference). Figure 10 and Figure 11 Two through-hole rows 11T1 are connected in parallel near one end of the conductor layer 11C1 along its long side. Two through-hole rows 11T2 are connected in parallel near the other end of the conductor layer 11C1 along its long side.

[0079] Next, the structure of inductor L12 will be explained. For example... Figure 12 and Figure 13 As shown, inductor L12 is wound around axis A12, which is parallel to a direction orthogonal to the stacking direction T. In this embodiment, in particular, axis A12 extends in a direction parallel to the X direction. Furthermore, inductor L12 includes: conductor portions L12A, L12B, and L12C, each wound less than one turn around axis A12; a connecting portion L12D connecting conductor portions L12A and L12B in series; and a connecting portion L12E connecting conductor portions L12B and L12C in series.

[0080] Conductor portions L12A, L12B, and L12C respectively include conductor layers 12C1, 12C2, and 12C3 (see reference). Figure 10 and Figure 11 The conductor layers 12C1, 12C2, and 12C3 each have a longer shape in a direction parallel to the Y direction.

[0081] Conductor layer 12C1 includes conductor layers 722 and 732 (see reference) that are disposed at different positions in the stacking direction T and connected in parallel by two through holes. Figure 8C and Figure 9A The conductor layer portion 12C2 includes conductor layers 723 and 733 (see reference) that are disposed at different positions in the stacking direction T and connected in parallel by two through-holes. Figure 8C and Figure 9AThe conductor layer portion 12C3 includes conductor layers 724 and 734 (see reference) that are disposed at different positions in the stacking direction T and connected in parallel by two through-holes. Figure 8C and Figure 9A Conductor layers 722-724 and 732-734 each extend in a direction parallel to the Y direction.

[0082] The conductor portion L12A also includes via arrays 12T1 and 12T2 (see reference). Figure 10 and Figure 11 The through-hole row 12T1 is connected to a portion near one end of the conductor layer 12C1 along its long side. The through-hole row 12T2 is connected to a portion near the other end of the conductor layer 12C1 along its long side.

[0083] The conductor portion L12B also includes through-hole arrays 12T3 and 12T4 (see reference). Figure 10 and Figure 11 Through-hole row 12T3 is connected to a portion near one end of the conductor layer 12C2 along its long side. Through-hole row 12T4 is connected to a portion near the other end of the conductor layer 12C2 along its long side.

[0084] The conductor portion L12C also includes via arrays 12T5 and 12T6 (see reference). Figure 10 and Figure 11 Through-hole row 12T5 is connected to a portion near one end of the conductor layer 12C3 along its long side. Through-hole row 12T6 is connected to a portion near the other end of the conductor layer 12C3 along its long side.

[0085] The connecting portion L12D connects the through-hole row 12T2 of the conductor portion L12A and the through-hole row 12T3 of the conductor portion L12B. Additionally, the connecting portion L12D includes a conductor layer portion 12C4 (see reference). Figure 10 The conductor layer portion 12C4 includes conductor layers 621 and 631 (see reference) that are disposed at different positions in the stacking direction T and connected in parallel by two through-holes. Figure 7C and Figure 8A ).

[0086] The connecting portion L12E connects the through-hole row 12T4 of the conductor portion L12B and the through-hole row 12T5 of the conductor portion L12C. Additionally, the connecting portion L12E includes a conductor layer portion 12C5 (see reference). Figure 10 The conductor layer portion 12C5 includes conductor layers 622 and 632 (see reference) that are disposed at different positions in the stacking direction T and connected in parallel by two through-holes. Figure 7C and Figure 8A ).

[0087] Figure 5A and Figure 5BThe conductor layers 542 and 552 shown are positioned at different locations in the stacking direction T and are connected in parallel by three vias. The conductor layers 542 and 552 connect the via arrays 11T3 and 11T4 of the conductor portion of inductor L11 and the via array 12T1 of the conductor portion L12A of inductor L12.

[0088] Next, the structure of inductor L13 will be described. Inductor L13 is wound around an axis A13 parallel to the stacking direction T. Inductor L13 consists of conductor layer 531 (see reference). Figure 4C )constitute.

[0089] Next, the structure of inductor L21 will be explained. For example... Figure 14 and Figure 15 As shown, inductor L21 is wound around axis A21, which is parallel to a direction orthogonal to the stacking direction T. In this embodiment, in particular, axis A21 extends in a direction parallel to the Y direction.

[0090] Additionally, inductor L21 includes a conductor portion wound less than one turn around axis A21. The conductor portion of inductor L21 includes conductor layer 21C1 (see reference). Figure 10 and Figure 11 The conductor layer portion 21C1 includes conductor layers 725 and 735 (see reference) that are disposed at different positions in the stacking direction T and connected in parallel by two through-holes. Figure 8C and Figure 9A Conductor layers 725 and 735 each include a first portion extending in the X direction and a second portion extending in the Y direction.

[0091] The conductor portion of inductor L21 also includes via arrays 21T1 and 21T2 (see reference). Figure 10 and Figure 11 Through-hole row 21T1 is connected to a portion near one end of the conductor layer 21C1 along its long side. Through-hole row 21T2 is connected to a portion near the other end of the conductor layer 21C1 along its long side.

[0092] Inductor L21 also includes conductor layers 21C2 and 21C3 (see reference) Figure 11 Conductor layer 21C1 connects one end of via array 21T1 and one end of via array 21T2. Conductor layer 21C2 extends to connect to and be close to the other end of via array 21T1. Conductor layer 21C3 extends to connect to and be close to the other end of via array 21T2.

[0093] Conductor layer 21C2 includes conductor layers 561 and 571 (see reference) that are disposed at different positions in the stacking direction T and connected in parallel by two through holes. Figure 5C and Figure 6A The conductor layer portion 21C3 includes conductor layers 544 and 553 (see reference) that are disposed at different positions in the stacking direction T and connected in parallel by two through-holes. Figure 5A and Figure 5B ).

[0094] Conductor layers 21C1 and 21C2 and vias 21T1 and 21T2 constitute the inductor portion 211 of inductor L21. Conductor layer 21C3 constitutes the inductor portion 212 of inductor L21. Conductor layer 21C3 (conductor layers 544 and 553) passes through conductor layers 526 and 5310 (see reference). Figure 4B and Figure 4C ) and multiple through holes are connected to the grounding terminal 117.

[0095] Next, the structure of inductor L22 will be explained. For example... Figure 13 and Figure 14 As shown, inductor L22 is wound around axis A22, which is parallel to a direction orthogonal to the stacking direction T. In this embodiment, in particular, axis A22 extends in a direction parallel to the Y direction. Furthermore, inductor L22 includes: conductor portions L22A and L22B, each wound less than one turn around axis A22; and a connecting portion L22C connecting conductor portions L22A and L22B in series.

[0096] Conductor portions L22A and L22B respectively include conductor layers 22C1 and 22C2 (refer to...) Figure 10 and Figure 11 The conductor layers 22C1 and 22C2 each have a shape that is longer in a direction parallel to the X direction.

[0097] Conductor layer 22C1 includes conductor layers 726 and 736 (see reference) that are disposed at different positions in the stacking direction T and connected in parallel by four through holes. Figure 8C and Figure 9A The conductor layer portion 22C2 includes conductor layers 727 and 737 (see reference) that are disposed at different positions in the stacking direction T and connected in parallel by four through holes. Figure 8C and Figure 9A Conductor layers 726, 727, 736, and 737 each extend in a direction parallel to the X direction.

[0098] The conductor portion L22A also includes two via rows 22T1 and two via rows 22T2 (see reference). Figure 10 and Figure 11Near one end of the conductor layer 22C1 along its long side, two through-hole rows 22T1 are connected in parallel. Near the other end of the conductor layer 22C1 along its long side, two through-hole rows 22T2 are connected in parallel.

[0099] The conductor section L22B also includes two via rows 22T3 and two via rows 22T4 (see reference). Figure 10 and Figure 11 Two through-hole rows 22T3 are connected in parallel near one end of the conductor layer 22C2 along its long side. Two through-hole rows 22T4 are connected in parallel near the other end of the conductor layer 22C2 along its long side.

[0100] The connecting portion L22C connects the two through-hole rows 22T2 of the conductor portion L22A and the two through-hole rows 22T3 of the conductor portion L22B. Additionally, the connecting portion L22C includes a conductor layer portion 22C3 (see reference). Figure 10 and Figure 11 The conductor layer portion 22C3 includes conductor layers 591 and 601 (see reference) that are disposed at different positions in the stacking direction T and connected in parallel by four through holes. Figure 6C and Figure 7A ).

[0101] Conductor portion L22A constitutes inductor portion 221 of inductor L22. Conductor portion L22B constitutes inductor portion 222 of inductor L22. From a circuit structure perspective, conductor portion L22B is positioned between conductor portion L22A and the ground wire. The two vias 22T4 of conductor portion L22B pass through conductor layers 525 and 539 (see reference). Figure 4B and Figure 4C It connects to grounding terminals 115 and 118 via multiple through holes.

[0102] Next, capacitors C11-C16, C21-C31 and... Figures 4A to 9B The correspondence of the internal components of the stacked body 50 shown is explained. The capacitor C11 is composed of... Figures 4B to 5A , Figure 8C and Figure 9A The capacitor C12 is composed of conductor layers 521, 532, 541, 551 and dielectric layers 52, 53, 54 between these conductor layers. Figure 7C , Figure 8A , Figure 8C and Figure 9A The capacitor C13 is composed of conductor layers 621, 622, 631, 632, 722-724, 732-734, and dielectric layers 62 and 72 between these conductor layers.

[0103] Capacitor C14 is made of Figure 4C The capacitor C15 is composed of conductor layers 5311 and 532. Figure 5A The capacitor C16 is composed of conductor layer 542 and dielectric layer 53 between these conductor layers. Figure 4C and Figure 5A The conductor layers 5312 and 543 shown are formed by the dielectric layer 53 between these conductor layers.

[0104] Capacitor C21 is made of Figure 4C and Figure 5A The capacitor C22 is composed of conductor layers 533 and 545 and the dielectric layer 53 between these conductor layers. Figure 4C , Figure 5A and Figure 5C The capacitor C23 is composed of conductor layers 534 and 545 and the dielectric layer 53 between these conductor layers. Figure 4C and Figure 5A The capacitor C24 is composed of conductor layers 533 and 534, and the dielectric layer 53 between these conductor layers. The capacitor C25 is composed of conductor layers 533 and 534. Figure 4C , Figure 5A and Figure 5C The conductor layers 536, 546, and 547 shown, and the dielectric layer 53 between these conductor layers, constitute the structure.

[0105] Capacitor C26 is made of Figure 5C , Figure 6A , Figure 8C and Figure 9A The capacitor C27 is composed of conductor layers 561, 571, 725, and 735, and dielectric layers 56 and 72 between these conductor layers. Figure 5A and Figure 5B The capacitor C28 is composed of conductor layers 544 and 553 and the dielectric layer 54 between these conductor layers. Figure 5B and Figure 6A The conductor layers 554 and 572 shown and the dielectric layers 55 and 56 between these conductor layers constitute the structure.

[0106] Capacitor C29 is made of Figure 6C , Figure 7A , Figure 8C and Figure 9A The capacitor C30 is composed of conductor layers 591, 601, 726, and 736, and dielectric layers 59 and 72 between these conductor layers. Figure 8C and Figure 9A The capacitor C31 is composed of conductor layers 727 and 737 and dielectric layers 59 and 72 between these conductor layers. Figure 4C and Figure 5AThe conductor layers 537 and 548 shown are formed by the dielectric layer 53 between these conductor layers.

[0107] Next, refer to Figures 10-17 The structural features of the electronic component 1 in this embodiment will be described. Figure 16 and Figure 17 It means Figure 10 and Figure 11 A top view of a portion of the interior of the stacked body 50 shown.

[0108] like Figures 10-15 As shown, inductor L12 is positioned in front of inductor L11 in a direction orthogonal to the stacking direction T, namely the -Y direction. Inductors L21 and L22 are positioned in front of inductors L11 and L12, respectively, in a direction orthogonal to the stacking direction T, namely the -X direction.

[0109] exist Figure 12 and Figure 15 In the diagram, the area enclosed by the dashed line marked S11 represents the space containing axis A11 and bounded by inductor L11. Additionally, in Figure 12 and Figure 13 In the diagram, the area enclosed by the dashed line marked S12 represents the space containing axis A12 and bounded by inductor L12. Additionally, in Figure 14 and Figure 15 In the diagram, the area enclosed by the dashed line marked S21 represents the space containing axis A21 and bounded by inductor L21. Additionally, in Figure 13 and Figure 14 In the figure, the area enclosed by the dashed line with reference numeral S22 represents the space containing axis A22 and enclosed by inductor L22.

[0110] exist Figure 15 In the diagram, the area enclosed by the dashed line marked S11 is the region obtained by projecting space S11 perpendicularly onto a virtual plane (XZ plane) perpendicular to axis A11. This region will be referred to as the projection region of space S11. The area of ​​the projection region of space S11 is equivalent to the opening area of ​​inductor L11.

[0111] In addition, Figure 12 In the diagram, the area enclosed by the dashed line marked S12 is the region obtained by projecting space S12 perpendicularly onto a virtual plane (YZ plane) perpendicular to axis A12. This region will be referred to as the projection region of space S12. The area of ​​the projection region of space S12 is equivalent to the opening area of ​​inductor L12.

[0112] In addition, Figure 15In the diagram, the area enclosed by the dashed line marked S21 is the region obtained by projecting space S21 perpendicularly onto a virtual plane (XZ plane) perpendicular to axis A21. This region will be referred to below as the projection region of space S21. The area of ​​the projection region of space S21 is equivalent to the opening area of ​​inductor L21.

[0113] In addition, Figure 13 In the diagram, the area enclosed by the dashed line marked S22 is the region obtained by projecting space S22 perpendicularly onto a virtual plane (XZ plane) perpendicular to axis A22. This region will be referred to below as the projection region of space S22. The area of ​​the projection region of space S22 is equivalent to the opening area of ​​inductor L22.

[0114] like Figure 12 and Figure 15 As shown, the area of ​​the projected region of space S11 is larger than the area of ​​the projected region of space S12. Additionally, as... Figure 12 and Figure 15 As shown, the area of ​​the projected region of space S21 is larger than the area of ​​the projected region of space S12. Additionally, as... Figure 12 and Figure 13 As shown, the area of ​​the projected region of space S22 is larger than the area of ​​the projected region of space S12.

[0115] In addition, such as Figure 13 and Figure 15 As shown, the areas of the projected regions of space S21 and S22 are different from each other. In this embodiment, in particular, the area of ​​the projected region of space S21 is larger than the area of ​​the projected region of space S22. In addition, the dimension of the projected region of space S21 in the stacking direction T is larger than the dimension of the projected region of space S22 in the stacking direction T.

[0116] When viewed from a direction parallel to axis A11 (Y direction), inductor L11 is configured such that a portion of space S11 overlaps with at least a portion of space S12.

[0117] When viewed from a direction parallel to axis A12 (X direction), inductor L12 is configured such that at least a portion of space S12 overlaps with space S22. Furthermore, inductor L12 is configured such that axis A12 is parallel to the long side of the bottom surface 50A (long side of the upper surface 50B) of the laminate 50.

[0118] Inductor L13 is configured such that its axis A13 does not intersect spaces S11, S21, and S22, but does intersect space S12. In other words, inductor L13 is configured to overlap with inductor L12 when viewed from the Z direction. Between inductors L12 and L13, specifically, in conductor layer 531 (refer to...) Figure 4C) and conductor layers 621, 622 Figure 7C Between (reference), there is no capacitor conductor layer for forming a capacitor.

[0119] When viewed from a direction parallel to axis A21 (Y direction), inductor L21 is configured such that a portion of space S21 overlaps with at least a portion of space S22. In other words, when viewed from a direction parallel to axis A22 (Y direction), inductor L22 is configured such that at least a portion of space S22 overlaps with a portion of space S21.

[0120] The conductor layer 21C3 of inductor L21 is disposed between the conductor layer 21C1 and the bottom surface 50A of inductor L21. Viewed from a direction parallel to the stacking direction T (Z direction), the conductor layer 21C3 extends in a manner that cuts across the signal terminal 114. In addition, inductor L21 is electrically connected to the ground terminal 117. Inductor L22 is electrically connected to ground terminals 115 and 118.

[0121] The inductor L22 includes: a conductor portion L22A constituting the inductor portion 221 of the inductor L22; a conductor portion L22B constituting the inductor portion 222 of the inductor L22; and a connection portion L22C connecting the conductor portions L22A and L22B in series. The conductor portion L22A (inductor portion 221) is magnetically coupled to the conductor layers 21C1 and 21C2 and the via rows 21T1 and 21T2 constituting the inductor portion 211 of the inductor L21.

[0122] exist Figure 17 The diagram shows the two conductor layers 721 and 731 that constitute the conductor layer portion 11C1 of inductor L11. For example... Figure 17 As shown, the area of ​​conductor layer 721 is larger than the area of ​​conductor layer 731. When viewed from a direction parallel to the stacking direction T (Z direction), conductor layer 731 is disposed inside the outer edge of conductor layer 721. The shape of conductor layer 731 when viewed from the Z direction is similar to the shape of conductor layer 721 when viewed from the Z direction. Conductor layer 721 is disposed between conductor layer 731 and axis A11.

[0123] The above description of conductor layers 721 and 731 also applies to the group of conductor layers 72x and 73x (x is an integer of 2 to 7). If conductor layers 721 and 731 in the above description of conductor layers 721 and 731 are replaced with conductor layers 72x and 73x respectively, it becomes a description of conductor layers 72x and 73x. Furthermore, when describing the group of conductor layers 72x and 73x constituting inductor L12, axis A11 in the above description is replaced with axis A12. In addition, when describing the group of conductor layers 725 and 735 constituting inductor L21, axis A11 in the above description is replaced with axis A21. In addition, when describing the group of conductor layers 72x and 73x constituting inductor L22, axis A11 in the above description is replaced with axis A22.

[0124] exist Figure 16 The diagram shows the two conductor layers 621 and 631 that constitute the conductor layer portion 12C4 of inductor L12. For example... Figure 16 As shown, the area of ​​conductor layer 631 is larger than the area of ​​conductor layer 621. Viewed from a direction parallel to the stacking direction T (Z direction), conductor layer 621 is disposed inside the outer edge of conductor layer 631. The shape of conductor layer 621 viewed from the Z direction is similar to the shape of conductor layer 631 viewed from the Z direction. Conductor layer 631 is disposed between conductor layer 621 and axis A12.

[0125] The above description of conductor layers 621 and 631 also applies to the group of conductor layers 622 and 632, the group of conductor layers 561 and 571, the group of conductor layers 543 and 553, and the group of conductor layers 591 and 601. If conductor layers 621 and 631 in the above description of conductor layers 621 and 631 are replaced with conductor layers 622 and 632 respectively, it becomes a description of conductor layers 622 and 632.

[0126] Furthermore, if the conductor layers 621 and 631 in the above description of conductor layers 621 and 631 are replaced with conductor layers 561 and 571 or conductor layers 543 and 553 respectively, and the axis A12 in the above description of conductor layers 621 and 631 is replaced with axis A21, then it becomes a description of conductor layers 561 and 571 or conductor layers 543 and 553.

[0127] Furthermore, if the conductor layers 621 and 631 in the above description of conductor layers 621 and 631 are replaced with conductor layers 591 and 601 respectively, and the axis A12 in the above description of conductor layers 621 and 631 is replaced with axis A22, then it becomes a description of conductor layers 591 and 601.

[0128] Next, an example of the characteristics of the electronic component 1 in this embodiment will be shown. Figure 18 This is a characteristic diagram representing the pass-through attenuation characteristics between the common port 2 and the first signal port 3, i.e., the pass-through attenuation characteristics of the first filter 10. Figure 19 This is a characteristic diagram representing the attenuation characteristics between common port 2 and second signal port 4, i.e., the attenuation characteristics of the second filter 20. Figure 18 and Figure 19 In the diagram, the horizontal axis represents frequency, and the vertical axis represents attenuation.

[0129] exist Figure 18 In the attached drawing, reference numeral 91 indicates the attenuation pole formed by inductor L11, and reference numeral 92 indicates the attenuation pole formed by inductor L12. In the pass-through attenuation characteristics of the first filter 10, inductor L12 forms an attenuation pole 92 on the side with a frequency higher than the first passband. In the pass-through attenuation characteristics of the first filter 10, inductor L11 forms an attenuation pole 91 between the first passband and the attenuation pole 92. That is, in the pass-through attenuation characteristics of the first filter 10, the attenuation pole 91 formed by inductor L11 is closer to the first passband than the attenuation pole 92 formed by inductor L12.

[0130] exist Figure 19 In the attached figure, reference numeral 93 indicates the attenuation pole formed by inductor L21, and reference numeral 94 indicates the attenuation pole formed by inductor L22. In the pass-through attenuation characteristics of the second filter 20, inductor L21 forms an attenuation pole 93 on the side with a frequency lower than the second passband. In the pass-through attenuation characteristics of the second filter 20, inductor L22 forms an attenuation pole 94 between attenuation pole 93 and the second passband. That is, in the pass-through attenuation characteristics of the second filter 20, the attenuation pole 94 formed by inductor L22 is closer to the second passband than the attenuation pole 93 formed by inductor L21.

[0131] Below is an example illustrating the inductance and Q value of inductors L11, L12, L13, L21, and L22. In one example, the inductance of inductor L11 is 0.8nH. The Q value of inductor L11 is 125. The inductance of inductor L12 is 3.4nH. The Q value of inductor L12 is 113. The inductance of inductor L13 is 0.81nH. The Q value of inductor L13 is 53. The inductance of inductor L21 is 1.5nH. The Q value of inductor L21 is 73. The inductance of inductor L22 is 2.0nH. The Q value of inductor L22 is 127.

[0132] Next, the function and effects of the electronic component 1 in this embodiment will be explained. In this embodiment, in inductor L11, two via arrays are connected in parallel near both ends of the conductor layer 11C1 along its long side. Similarly, in inductor L22, two via arrays are connected in parallel near both ends of the conductor layer 22C1 along its long side, and two via arrays are connected in parallel near both ends of the conductor layer 22C2 along its long side.

[0133] Furthermore, in inductor L12, a via array is connected to each end of the conductor layer 12C1 along its long side, a via array is connected to each end of the conductor layer 12C2 along its long side, and a via array is connected to each end of the conductor layer 12C3 along its long side. Similarly, in inductor L21, a via array is connected to each end of the conductor layer 21C1 along its long side.

[0134] As described above, in this embodiment, in each of the inductors L11 and L22, a plurality of (two) rows of vias are connected in parallel at one end of the conductor layer. Therefore, according to this embodiment, the Q value of each of the inductors L11 and L22 can be increased.

[0135] On the other hand, in this embodiment, each of the inductors L12 and L21 has a via array connected to one end of the conductor layer. Therefore, according to this embodiment, compared to the case where multiple via arrays are connected in parallel to one end of the conductor layer in all of the inductors L11, L12, L21, and L22, the electronic component 1 can be made smaller.

[0136] Furthermore, in the first filter 10, it is preferable to increase the Q value of the inductor L11, which forms the attenuation pole 91 closest to the first passband. Similarly, in the second filter 20, it is preferable to increase the Q value of the inductor L22, which forms the attenuation pole 94 closest to the second passband. In this embodiment, from the viewpoint of connecting multiple (two) via rows in parallel at one end of the conductor layer in each of the inductors L11 and L22, the Q values ​​of each inductor L11 and L22 are increased.

[0137] Furthermore, in this embodiment, inductor L12 is disposed in front of inductor L11 in the -Y direction, and inductors L21 and L22 are disposed in front of inductors L11 and L12 respectively in the -X direction. That is, in this embodiment, inductors L11 and L12 are arranged in a row, and inductors L21 and L22 are arranged in a row at a different position than inductors L11 and L12. Therefore, according to this embodiment, compared with the case where inductors L11 and L22 are arranged in a row and inductors L12 and L21 are arranged in a row at a different position than inductors L11 and L22, the useless space generated in the laminate 50 can be reduced, and as a result, the electronic component 1 can be miniaturized.

[0138] As described above, according to this embodiment, the Q values ​​of inductors L11 and L22 can be increased, while the electronic component 1 can be miniaturized.

[0139] Furthermore, in this embodiment, the axis A11 of the wound inductor L11 and the axis A22 of the wound inductor L22 are parallel to each other. In particular, axes A11 and A22 both extend in a direction parallel to the Y direction. Additionally, in each of the inductors L11 and L22, the conductor layer has a shape that is longer in the X direction. Therefore, according to this embodiment, compared to the case where axes A11 and A22 are orthogonal to each other, the dimension of the laminate 50 in the Y direction can be reduced.

[0140] Furthermore, in this embodiment, the direction parallel to axis A12 and the direction parallel to axis A22 are orthogonal to each other. In particular, the direction parallel to axis A12 is parallel to the X direction, and the direction parallel to axis A22 is parallel to the Y direction. Additionally, in this embodiment, inductor L12 is wound approximately 3 times around axis A12, which is parallel to the X direction. As described above, in inductor L22, the conductor layer has a longer shape in the X direction. Therefore, according to this embodiment, compared to the case where axis A22 is parallel to the X direction and the conductor layer of inductor L22 has a shorter shape in the X direction, the useless space generated when inductor L12 is wound multiple times around axis A12 can be reduced.

[0141] Next, other effects of this embodiment will be explained. In this embodiment, the area of ​​the projected region of space S11, which is equivalent to the opening area of ​​inductor L11, is larger than the area of ​​the projected region of space S12, which is equivalent to the opening area of ​​inductor L12. That is, in this embodiment, the area of ​​the projected region of space S12, which is equivalent to the opening area of ​​inductor L12, is smaller than the area of ​​the projected region of space S11, which is equivalent to the opening area of ​​inductor L11. As a result, a space for arranging other inductors can be formed near inductor L12. In this embodiment, inductor L13 is arranged in the aforementioned space. As described above, inductor L13 is arranged such that axis A13 does not intersect space S11 but intersects space S12. In this embodiment, inductors L11, L12, and L13 are also wound around axes parallel to each other in directions different from each other. In particular, axes A11, A12, and A13 are orthogonal to each other. Therefore, according to this embodiment, electromagnetic field coupling between inductors L11, L12, and L13 can be suppressed, while electronic component 1 can be miniaturized.

[0142] Furthermore, in this embodiment, the inductor L11 is configured such that, when viewed from a direction parallel to axis A11, a portion of space S11 overlaps with at least a portion of space S12. Therefore, according to this embodiment, compared to the case where spaces S11 and S12 do not overlap, the electronic component 1 can be miniaturized.

[0143] Furthermore, according to this embodiment, the first filter 10 includes inductors L11, L12, and L13. According to this embodiment, by utilizing the aforementioned features of inductors L11, L12, and L13, the area of ​​the first filter 10 within the laminate 50 can be reduced, resulting in the miniaturization of the electronic component 1.

[0144] Furthermore, in this embodiment, the area of ​​the projected region of space S12, which is equivalent to the opening area of ​​inductor L12, is smaller than the area of ​​the projected region of space S22, which is equivalent to the opening area of ​​inductor L22. In this embodiment, inductors L12, L13, and L22 are also wound around axes parallel to each other in directions different from each other. In particular, axes A12, A13, and A22 are orthogonal to each other. Therefore, according to this embodiment, electromagnetic field coupling between inductors L12, L13, and L22 can be suppressed, while miniaturizing the electronic component 1.

[0145] Furthermore, in this embodiment, the inductor L12 is configured such that, when viewed from a direction parallel to axis A12, a portion of space S12 overlaps with at least a portion of space S22. Therefore, according to this embodiment, compared to the case where spaces S12 and S22 do not overlap, the electronic component 1 can be miniaturized.

[0146] Furthermore, in this embodiment, no capacitor conductor layer is provided between inductor L12 and inductor L13. Therefore, according to this embodiment, compared with the case where a capacitor conductor layer is provided between inductor L12 and inductor L13, the electronic component 1 can be miniaturized.

[0147] Furthermore, in this embodiment, the first filter 10 includes inductors L12 and L13, and the second filter 20 includes inductor L22. According to this embodiment, by utilizing the aforementioned features of inductors L12, L13, and L22, the first filter 10 and the second filter 20 can be brought closer together, resulting in the miniaturization of the electronic component 1.

[0148] However, the area of ​​the projected region of space S12, which is comparable to the opening area of ​​inductor L12, is small; therefore, the inductance of inductor L12 is relatively small. In this embodiment, inductor L12 includes conductor portions L12A, L12B, and L12C, each wound around axis A12 less than one turn. That is, in this embodiment, inductor L12 is wound around axis A12 approximately three turns. Therefore, according to this embodiment, the inductance of inductor L12 can be increased. Furthermore, according to this embodiment, the dimension in the direction parallel to axis A12 of inductor L12 (the direction parallel to the X direction) can be increased. Therefore, according to this embodiment, the space for arranging inductor L13 can be increased.

[0149] Furthermore, in this embodiment, the inductor L12 is configured such that the axis A12 is parallel to the long side of the bottom surface 50A (the long side of the upper surface 50B) of the laminate 50. Therefore, according to this embodiment, other inductors can be arranged in a direction parallel to the axis A12; specifically, the inductor L22 can be arranged, and the inductor L12 can be wound multiple times around the axis A12.

[0150] Furthermore, in this embodiment, inductors L11 and L12 are disposed on the first signal path 5 from a circuit structure perspective, and inductor L13 is disposed between the first signal path 5 and the ground line from a circuit structure perspective. The Q value of inductor L13 can be smaller than the Q value of inductors L11 and L12. As described above, in one example, the Q value of inductor L11 is 125, the Q value of inductor L12 is 113, and the Q value of inductor L13 is 53. In this embodiment, inductors L11 and L12, which preferably have larger Q values, are inductors wound around an axis orthogonal to the stacking direction T, while inductor L13, which can have a smaller Q value, is inductor wound around an axis parallel to the stacking direction T. Moreover, inductor L13, which can have a smaller Q value, is disposed in the space formed near inductor L12.

[0151] Furthermore, in this embodiment, inductor L21 is configured such that, when viewed from a direction parallel to axis A21 (Y direction), a portion of space S21 overlaps with at least a portion of space S22. In other words, inductor L22 is configured such that, when viewed from a direction parallel to axis A22 (Y direction), at least a portion of space S22 overlaps with a portion of space S22. In this embodiment, axis A21 is parallel to axis A22. Therefore, in this embodiment, inductors L21 and L22 are configured such that the opening of inductor L21 and the opening of inductor L22 are opposite to each other, and when viewed from the Y direction, inductor L21 and inductor L22 overlap.

[0152] Here, we consider adjusting the magnetic coupling between inductors L21 and L22. For example, the magnetic coupling can be adjusted by shifting one of inductors L21 or L22 in the X or -X direction. However, this would create unusable space within the stack 50, and the planar shape (shape viewed from the Z direction) of the electronic component 1 would become larger.

[0153] In this embodiment, the areas of the projection regions of space S21 and S22 are different from each other. Therefore, according to this embodiment, the magnetic coupling can be adjusted without shifting either inductor L21 or L22 in the X direction or the -X direction.

[0154] However, to adjust the area of ​​the projected region of space S21, the dimension of the stacking direction T of inductor L21 can be increased. In this case, the distance from the bottom surface 50A of the stack 50 to inductor L21 becomes smaller. If a grounding terminal is provided near inductor L21, stray capacitance will be generated between inductor L21 and the grounding terminal, which may result in undesirable characteristics.

[0155] In this embodiment, the inductor L21 includes: a conductor layer 21C2 extending to connect to and approach the other end of the via array 21T1 and via array 21T2; and a conductor layer 21C3 extending to connect to and approach the other end of the via array 21T2 and via array 21T1. According to this embodiment, using at least one of the conductor layers 21C2 and 21C3, the inductor L21 can be configured without overlapping with the ground terminal when viewed from a direction parallel to the stacking direction T (Z direction). In this embodiment, particularly when viewed from a direction parallel to the stacking direction T (Z direction), the conductor layer 21C3 extends in a manner that cuts across the signal terminal 114. Therefore, according to this embodiment, the dimension of the stacking direction T of the inductor L21 can be increased, thereby adjusting the area of ​​the projected region of the space S21.

[0156] As described above, according to this embodiment, the electromagnetic field coupling between inductors L21 and L22 can be adjusted, while the electronic component 1 can be miniaturized.

[0157] In this embodiment, electronic component 1 includes a second filter 20 including inductors L21 and L22, and a first filter 10 excluding inductors L21 and L22. To increase the insulation between the first filter 10 and the second filter 20, a grounding terminal can be provided at the location sandwiched between the first filter 10 and the second filter 20. In this embodiment, the conductor layer 21C3 is connected to the grounding terminal 117 located at the location sandwiched between the first filter 10 and the second filter 20. That is, according to this embodiment, the insulation between the first filter 10 and the inductor L21 can be increased, while the inductor L21 is connected to the grounding terminal 117 via the conductor layer 21C3.

[0158] Furthermore, in this embodiment, inductor L22 includes conductor portions L22A and L22B. Conductor portion L22A is magnetically coupled to inductor L21. That is, in this embodiment, a portion of inductor L22 is magnetically coupled to inductor L21. According to this embodiment, by configuring the inductor as described above, the magnetic coupling between inductor L21 and inductor L22 can be adjusted.

[0159] Furthermore, in this embodiment, the conductor layer portion 11C1 of the inductor L11 includes two conductor layers 721 and 731. As described above, during the manufacturing process of the laminate 50, a ceramic green sheet laminate is formed, comprising multiple pre-firing conductor layers that will later become multiple conductor layers and multiple pre-firing through-holes that will later become multiple through-holes. If the conductor layers 721 and 731 are misaligned due to the misalignment of the ceramic green sheet or the multiple pre-firing conductor layers, the characteristics of the inductor L11 will change.

[0160] In this embodiment, the area of ​​conductor layer 721 is larger than the area of ​​conductor layer 731. Therefore, even assuming that conductor layer 731 is offset relative to conductor layer 721, if the offset is less than a certain amount, conductor layer 731 will not be exposed from conductor layer 721 when viewed from a direction parallel to the stacking direction T (Z direction). Thus, according to this embodiment, the variation in the characteristics of inductor L11 caused by the offset between conductor layers 721 and conductor layer 731 can be suppressed.

[0161] The above description of conductor layers 721 and 731 also applies to the group of conductor layers 72x and 73x (x is an integer between 2 and 7), the group of conductor layers 621 and 631, the group of conductor layers 622 and 632, the group of conductor layers 561 and 571, the group of conductor layers 543 and 553, and the group of conductor layers 591 and 601. Therefore, according to this embodiment, it is possible to suppress the variation in the characteristics of the first filter 10 and the second filter 20 caused by the offset of the ceramic green sheet or multiple pre-firing conductor layers, and as a result, it is possible to suppress the variation in the characteristics of the electronic component 1.

[0162] Furthermore, the present invention is not limited to the above-described embodiments and various modifications can be made. For example, the number of inductors included in the first filter 10 and the second filter 20 can each be three or more.

[0163] Additionally, axes A11 and A12 can intersect at angles other than 90°. Similarly, axes A21 and A22 can intersect at angles other than 90°.

[0164] In addition, in each of inductors L11 and L22, three or more through-hole arrays can be connected in parallel at one end of the conductor layer.

[0165] Alternatively, in each of the inductors L11, L12, L21, and L22, the conductor layer portion may include three or more conductor layers arranged at different positions and connected in parallel in the stacking direction T. When the conductor layer portion includes three conductor layers, the conductor layer with the smallest area may be positioned between the other two conductor layers. Alternatively, the conductor layer portion may consist of a single conductor layer.

[0166] Based on the foregoing description, various modes and variations in which the present invention can be implemented have been clarified. Therefore, within the equivalent scope of the claims, the present invention can be implemented even using modes other than the preferred mode described above.

Claims

1. A laminated electronic component, characterized by, include: A laminate comprising multiple stacked dielectric layers; A first inductor integrated with the laminate is wound around a first axis orthogonal to the stacking direction of the plurality of dielectric layers; A second inductor integrated with the laminate is wound around a second axis orthogonal to the lamination direction; A third inductor integrated with the laminate is wound around a third axis orthogonal to the lamination direction; and The fourth inductor, integrated with the laminate, is wound around a fourth axis orthogonal to the lamination direction. The second inductor is positioned in front of the first inductor in a first direction orthogonal to the stacking direction. The third inductor and the fourth inductor are respectively positioned in front of the first inductor and the second inductor in a second direction orthogonal to the stacking direction and the first direction. The first inductor and the fourth inductor each include a plurality of first via rows and at least one first conductor layer. The second inductor and the third inductor each include a plurality of second via rows and at least one second conductor layer. The plurality of first through-hole rows and the plurality of second through-hole rows are each formed by connecting two or more through holes in series. The at least one first conductor layer and the at least one second conductor layer each include a conductor layer. Near one end of the conductor layer in the long side direction of at least one first conductor layer portion, two or more of the plurality of first through-hole rows are connected in parallel. Near the other end of the conductor layer in the long side direction of the at least one first conductor layer portion, two or more additional first through-hole rows from the plurality of first through-hole rows are connected in parallel. In the portion near one end of the conductor layer in the long side direction of at least one second conductor layer, only one of the plurality of second via rows is connected. In the portion near the other end of the conductor layer in the long side direction of the at least one second conductor layer, only one of the plurality of second through-hole rows is connected.

2. The stacked electronic component according to claim 1, characterized in that: The first axis and the fourth axis are parallel to each other.

3. The stacked electronic component according to claim 1, characterized in that: The direction parallel to the second axis and the direction parallel to the fourth axis are orthogonal to each other.

4. The stacked electronic component according to claim 1, characterized in that: The first inductor includes a conductor portion wound less than one turn around the first axis. The fourth inductor includes: a plurality of first conductor portions, each wound less than one turn around the fourth axis; and at least one first connection portion connecting the plurality of first conductor portions in series.

5. The stacked electronic component according to claim 1, characterized in that: The second inductor includes: a plurality of second conductor portions, each wound less than one turn around the second axis; and at least one second connection portion connecting the plurality of second conductor portions in series.

6. The stacked electronic component according to claim 1, characterized in that: The third axis is parallel to the fourth axis.

7. The stacked electronic component according to claim 6, characterized in that: The area of ​​the region obtained by vertically projecting the first space, which includes the third axis and is enclosed by the third inductor, onto a virtual plane perpendicular to the third axis is greater than the area of ​​the region obtained by vertically projecting the second space, which includes the fourth axis and is enclosed by the fourth inductor, onto a virtual plane perpendicular to the fourth axis.

8. The multilayer electronic component according to claim 1, characterized by Also includes: Public port; First signal port; Second signal port; A first filter, comprising a first inductor and a second inductor, is disposed between the common port and the first signal port for selectively allowing a first signal of a frequency within a first passband to pass through. and A second filter, comprising the third and fourth inductors, is disposed between the common port and the second signal port for selectively allowing a second signal at a frequency within the second passband to pass through.

9. The stacked electronic component according to claim 8, characterized in that: From a circuit structure perspective, the first inductor is positioned closer to the first signal port than the second inductor.

10. The stacked electronic component according to claim 8, characterized in that: In the pass-through attenuation characteristics of the first filter, the attenuation pole formed by the first inductor is closer to the first passband than the attenuation pole formed by the second inductor.

11. The stacked electronic component according to claim 8, characterized in that: From a circuit structure perspective, the fourth inductor is positioned closer to the common port than the third inductor.

12. The stacked electronic component according to claim 8, characterized in that: In the pass-through attenuation characteristics of the second filter, the attenuation pole formed by the fourth inductor is closer to the second passband than the attenuation pole formed by the third inductor.

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