Pixel circuit and driving method thereof, and display device

Abstract

A pixel circuit and a driving method thereof, and a display device, wherein the pixel circuit comprises a driving subcircuit, a writing subcircuit, a compensation subcircuit, a reset subcircuit and a light-emitting element, wherein: the driving subcircuit is configured to provide a driving current to a third node (N3) in response to a control signal of a first node (N1); the writing subcircuit is configured to write a signal of a data signal line (Data) into a second node (N2) in response to a control signal of a first scanning signal line (S1), wherein the signal of the data signal line (Data) is a data voltage signal or a reset voltage signal; the compensation subcircuit is configured to write a reset voltage signal into the third node (N3) in response to a control signal of the first scanning signal line (S1); and is also configured to compensate the first node (N1) in response to a control signal of the first scanning signal line (S1); and the reset subcircuit is configured to write a reset voltage signal into the first node (N1) in response to control signals of the first scanning signal line (S1) and a second scanning signal line (S2).

Description

Technical Field

[0001] The embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and in particular to a pixel circuit and a driving method thereof, and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diode (QLED) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, bendability and low cost. With the continuous development of display technology, flexible display devices (Flexible Display) using OLED or QLED as light-emitting devices and thin film transistors (TFT) for signal control have become the mainstream products in the current display field. Summary of the invention

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] The embodiment of the present disclosure provides a pixel circuit, including a driving subcircuit, a writing subcircuit, a compensation subcircuit and a reset subcircuit, wherein: the driving subcircuit is respectively connected to a first node, a second node and a third node, and is configured to provide a driving current to the third node in response to a control signal of the first node; the writing subcircuit is respectively connected to a first scanning signal line, a data signal line and a second node, and is configured to write a signal of the data signal line into the second node in response to a signal of the first scanning signal line, and the signal of the data signal line is a data voltage signal or a reset voltage signal; the compensation subcircuit is respectively connected to a first power line, a first scanning signal line, a first node and a third node, and is configured to write the reset voltage signal into the third node in response to a signal of the first scanning signal line; and is also configured to compensate the first node in response to a signal of the first scanning signal line; the reset subcircuit is respectively connected to a first scanning signal line, a second scanning signal line, a first node and a second node, and is configured to write the reset voltage signal into the first node in response to a signal of the first scanning signal line and a second scanning signal line.

[0005] In an exemplary embodiment, the reset subcircuit includes a second transistor and a fourth transistor; the control electrode of the second transistor is connected to the first scan signal line, the first electrode of the second transistor is connected to the second electrode of the fourth transistor, and the second electrode of the second transistor is connected to the first node; the control electrode of the fourth transistor is connected to the second scan signal line, and the first electrode of the fourth transistor is connected to the second node; or,

[0006] The control electrode of the second transistor is connected to the first scanning signal line, the first electrode of the second transistor is connected to the second node, and the second electrode of the second transistor is connected to the first electrode of the fourth transistor; the control electrode of the fourth transistor is connected to the second scanning signal line, and the second electrode of the fourth transistor is connected to the first node.

[0007] In an exemplary embodiment, the compensation subcircuit includes a sixth transistor and a storage capacitor, the driving subcircuit includes a third transistor, and the write subcircuit includes a fifth transistor; the control electrode of the sixth transistor is connected to the first scan signal line, the first electrode of the sixth transistor is connected to the third node, and the second electrode of the sixth transistor is connected to the first node; one end of the storage capacitor is connected to the first node, and the other end of the storage capacitor is connected to the first power line; the control electrode of the third transistor is connected to the first node, the first electrode of the third transistor is connected to the second node, and the second electrode of the third transistor is connected to the third node; the control electrode of the fifth transistor is connected to the first scan signal line, the first electrode of the fifth transistor is connected to the data signal line, and the second electrode of the fifth transistor is connected to the second node.

[0008] In an exemplary embodiment, the pixel circuit also includes a first light-emitting control subcircuit and a second light-emitting control subcircuit, wherein: the first light-emitting control subcircuit is respectively connected to a first power line, a first scan signal line and a second node, and is configured to provide the signal of the first power line to the second node in response to the signal of the first scan signal line; the second light-emitting control subcircuit is respectively connected to a second scan signal line, a third node and a fourth node, and is configured to write the reset voltage signal to the fourth node in response to the signal of the second scan signal line; and is also configured to allow a driving current to pass between the third node and the fourth node.

[0009] In an exemplary embodiment, the first light-emitting control subcircuit includes a first transistor, and the second light-emitting control subcircuit includes a seventh transistor; the control electrode of the first transistor is connected to the first scanning signal line, the first electrode of the first transistor is connected to the first power line, and the second electrode of the first transistor is connected to the second node; the control electrode of the seventh transistor is connected to the second scanning signal line, the first electrode of the seventh transistor is connected to the third node, and the second electrode of the seventh transistor is connected to the fourth node.

[0010] In an exemplary embodiment, the signal of the first scan signal line and the signal of the second scan signal line are provided through two adjacent stages of the same group of shift registers.

[0011] In an exemplary embodiment, the first transistor, the third transistor, the fourth transistor and the seventh transistor are all first type transistors, the second transistor, the fifth transistor and the sixth transistor are all second type transistors, and the first type transistors and the second type transistors are different in transistor type.

[0012] In an exemplary embodiment, the first type transistor is a P-type thin film transistor; and the second type transistor is an N-type thin film transistor.

[0013] In an exemplary embodiment, the pixel circuit includes a substrate and a first semiconductor layer, a first conductive layer, a second semiconductor layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer stacked on the substrate; the first semiconductor layer includes an active layer of at least one polysilicon transistor, the first conductive layer includes a second scanning signal line and a first electrode plate of a storage capacitor, and an orthographic projection of the second scanning signal line on the substrate overlaps with an orthographic projection of the active layer of the polysilicon transistor on the substrate; the second semiconductor layer includes an active layer of at least one oxide transistor, the second conductive layer includes a second electrode plate of a storage capacitor and a first scanning signal line, the third conductive layer includes a second auxiliary signal line, and an orthographic projection of the first scanning signal line on the substrate, an orthographic projection of the second auxiliary signal line on the substrate overlaps with an orthographic projection of the active layer of the oxide transistor on the substrate; the fourth conductive layer includes first and second electrodes of a plurality of polysilicon transistors and first and second electrodes of a plurality of oxide transistors, and the fifth conductive layer includes a data signal line and a first power line.

[0014] In an exemplary embodiment, the polysilicon transistor includes a first transistor, a third transistor, a fourth transistor, and a seventh transistor; and the oxide transistor includes a second transistor, a fifth transistor, and a sixth transistor.

[0015] In an exemplary embodiment, the pixel circuit includes a first area and a second area; the first transistor is disposed in the first area, the first scan signal line is disposed in the second area, and the control electrode of the first transistor is connected to the first scan signal line through a connecting electrode and a via.

[0016] In an exemplary embodiment, the pixel circuit includes a first area and a second area; the seventh transistor, the fourth transistor and the second scan signal line are all arranged in the second area, and the area where the second scan signal line overlaps with the active layer of the fourth transistor serves as the control electrode of the fourth transistor, and the area where the second scan signal line overlaps with the active layer of the seventh transistor serves as the control electrode of the seventh transistor.

[0017] In an exemplary embodiment, the pixel circuit includes a first region and a second region; the third transistor is disposed in the first region, the first scan signal line and the seventh transistor are disposed in the second region, and the first scan signal line is disposed between the third transistor and the seventh transistor.

[0018] An embodiment of the present disclosure further provides a display device, comprising a pixel circuit as described in any of the preceding items.

[0019] The embodiment of the present disclosure also provides a driving method for a pixel circuit, which is used to drive a pixel circuit as described in any of the above, and the driving method includes: in a reset stage, the writing subcircuit writes the reset voltage signal of the data signal line into the second node in response to the control signal of the first scanning signal line; the reset subcircuit writes the reset voltage signal of the second node into the first node in response to the control signal of the first scanning signal line and the second scanning signal line; the compensation subcircuit writes the reset voltage signal of the first node into the third node in response to the control signal of the first scanning signal line; in a data writing stage, the writing subcircuit writes the data voltage signal of the data signal line into the second node in response to the control signal of the first scanning signal line, and the compensation subcircuit compensates for the first node in response to the control signal of the first scanning signal line; in a light emitting stage, the driving subcircuit provides a driving current to the third node in response to the control signal of the first node.

[0020] In an exemplary embodiment, the control signal of the first scan signal line and the control signal of the second scan signal line are output by a set of array substrate row driving circuits.

[0021] In an exemplary embodiment, the control signal of the first scan signal line and the control signal of the second scan signal line are output by two groups of array substrate row driving circuits.

[0022] In an exemplary embodiment, the data signal line includes multiple signal cycles, each signal cycle provides a reset voltage signal and a data voltage signal for a row of sub-pixels, the duration of the data voltage signal is the duration of the data writing phase, and the duration of the reset voltage signal is the duration of the reset phase.

[0023] Other aspects will become apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure. The shapes and sizes of the components in the accompanying drawings do not reflect the actual proportions and are only intended to illustrate the contents of the present disclosure.

[0025] Figure 1 A schematic diagram of the structure of a pixel circuit provided in an embodiment of the present disclosure;

[0026] Figure 2 An equivalent circuit diagram of a reset subcircuit provided in an embodiment of the present disclosure;

[0027] Figure 3 An equivalent circuit diagram of a compensation sub-circuit, a driving sub-circuit and a writing sub-circuit provided in an embodiment of the present disclosure;

[0028] Figure 4 An equivalent circuit diagram of a first light-emitting control subcircuit and a second light-emitting control subcircuit provided in an embodiment of the present disclosure;

[0029] Figure 5a and Figure 5b Two equivalent circuit diagrams of pixel circuits provided in embodiments of the present disclosure;

[0030] Figure 6 A working timing diagram of a pixel circuit provided by an embodiment of the present disclosure;

[0031] Figure 7a The pixel circuit provided in the embodiment of the present disclosure is Figure 6 Signal simulation diagram under the working timing shown;

[0032] Figure 7b A schematic diagram of the change of the current through the light-emitting element in the light-emitting stage when the threshold voltage Vth of the pixel circuit provided by the embodiment of the present disclosure is -2V, -2.5V, -3V and the data voltage is 3V to 7V;

[0033] Figure 7c A schematic diagram of the change of the current passing through the light-emitting element with the threshold voltage Vth in the light-emitting stage under different data voltages of the pixel circuit provided by the embodiment of the present disclosure;

[0034] Figure 8 A schematic diagram of the change of the current passing through the light-emitting element with the data voltage in one frame when the refresh frequency of the pixel circuit provided by the embodiment of the present disclosure is 60 Hz and 1 Hz;

[0035] Fig. 9 Another working timing diagram of the pixel circuit provided in the embodiment of the present disclosure;

[0036] Fig.10 A schematic diagram of a planar structure of a pixel circuit provided in an embodiment of the present disclosure;

[0037] Fig.11 for Fig.10 Sectional view along AA direction;

[0038] Fig.12a This is a schematic diagram of a pixel circuit disclosed herein after forming a first semiconductor layer pattern;

[0039] Figure 12b for Fig.12a Sectional view along AA direction;

[0040] Fig.13a It is a schematic diagram of a pixel circuit disclosed in the present invention after a first conductive layer pattern is formed;

[0041] Fig.13b for Fig.13a Sectional view along AA direction;

[0042] Fig.14a This is a schematic diagram of a pixel circuit disclosed herein after forming a second semiconductor layer pattern;

[0043] Fig.14b for Fig.14a Sectional view along AA direction;

[0044] Fig.15a It is a schematic diagram of a pixel circuit disclosed in the present invention after a second conductive layer pattern is formed;

[0045] Fig.15b for Fig.15a Sectional view along AA direction;

[0046] Fig.16a It is a schematic diagram of a pixel circuit disclosed in the present invention after a third conductive layer pattern is formed;

[0047] Fig.16b for Fig.16a Sectional view along AA direction;

[0048] Fig.17a It is a schematic diagram of a pixel circuit disclosed in the present invention after a sixth insulating layer pattern is formed;

[0049] Fig.17b for Fig.17b Sectional view along AA direction;

[0050] Fig.18a It is a schematic diagram of a pixel circuit disclosed in the present invention after a fourth conductive layer pattern is formed;

[0051] Fig.18b for Fig.18a Sectional view along AA direction;

[0052] Fig.19a This is a schematic diagram of a pixel circuit disclosed in the present invention after a first planar layer pattern is formed;

[0053] Fig.19b for Fig.19a Sectional view along AA direction;

[0054] Fig.20a It is a schematic diagram of a pixel circuit disclosed in the present invention after a fifth conductive layer pattern is formed;

[0055] Fig.20b for Fig.20a Sectional view along AA direction;

[0056] Fig.21a and Figure 21b Schematic diagram of two pixel circuit structures in two adjacent sub-pixels in a first direction according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0057] The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. Note that the embodiments can be implemented in a plurality of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0058] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprising" and similar words always cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0059] In the embodiments of the present disclosure, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current mainly flows.

[0060] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged.

[0061] In this specification, "connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0062] The present disclosure provides a pixel circuit. Figure 1 A schematic diagram of the structure of a pixel circuit provided in an embodiment of the present disclosure is shown in FIG. Figure 1 As shown, the pixel circuit includes: a driving subcircuit, a writing subcircuit, a compensation subcircuit, a reset subcircuit and a light-emitting element.

[0063] The driving sub-circuit is connected to the first node N1, the second node N2 and the third node N3 respectively, and is configured to provide a driving current to the third node N3 in response to a control signal of the first node N1;

[0064] The writing sub-circuit is connected to the first scanning signal line S1, the data signal line Data and the second node N2 respectively, and is configured to respond to the control signal of the first scanning signal line S1, write the signal of the data signal line Data into the second node N2, and the signal of the data signal line Data is a data voltage signal or a reset voltage signal;

[0065] The compensation sub-circuit is respectively connected to the first power line VDD, the first scan signal line S1, the first node N1 and the third node N3, and is configured to write the reset voltage signal of the first node N1 to the third node N3 in response to the control signal of the first scan signal line S1, and is also configured to compensate the first node N1 in response to the control signal of the first scan signal line S1;

[0066] The reset subcircuit is connected to the first scan signal line S1, the second scan signal line S2, the first node N1 and the second node N2 respectively, and is configured to write the reset voltage signal of the second node N2 into the first node N1 in response to the control signals of the first scan signal line S1 and the second scan signal line S2.

[0067] The pixel circuit provided by the embodiment of the present disclosure writes the reset voltage signal of the data signal line Data to the second node N2 in response to the control signal of the first scan signal line S1 through the writing subcircuit; the reset subcircuit writes the reset voltage signal of the second node N2 to the first node N1 in response to the control signal of the first scan signal line S1 and the second scan signal line S2; the compensation subcircuit writes the reset voltage signal of the first node N1 to the third node N3 in response to the control signal of the first scan signal line S1, thereby resetting the first node N1 and the third node N3, eliminating the charge on the anode surface of the light-emitting element, avoiding the influence of the threshold voltage drift of the driving subcircuit on the driving current of the light-emitting element, and improving the uniformity of the displayed image and the display quality of the display panel. In addition, the pixel circuit of the embodiment of the present disclosure has fewer leakage channels, which improves the screen flickering problem under low frequency and low brightness.

[0068] In an exemplary embodiment, Figure 1 As shown, the pixel circuit further includes: a first light-emitting control subcircuit and a second light-emitting control subcircuit, wherein:

[0069] The first light emitting control subcircuit is respectively connected to the first power line VDD, the first scan signal line S1 and the second node N2, and is configured to provide a signal of the first power line VDD to the second node N2 in response to a control signal of the first scan signal line S1;

[0070] The second light emitting control subcircuit is respectively connected to the second scanning signal line S2, the third node N3 and the fourth node N4, and is configured to write the reset voltage signal of the third node N3 into the fourth node N4 in response to the control signal of the second scanning signal line S2; and is also configured to allow a driving current to pass between the third node N3 and the fourth node N4.

[0071] In an exemplary embodiment, one end of the light emitting element is connected to the third node N3 or the fourth node N4, and the other end of the light emitting element is connected to the second power line VSS.

[0072] In an exemplary embodiment, Figure 2 The equivalent circuit diagram of the reset subcircuit provided in the embodiment of the present disclosure is as follows: Figure 2 As shown, the reset subcircuit provided in the embodiment of the present disclosure includes: a second transistor T2 and a fourth transistor T4.

[0073] The control electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the second electrode of the fourth transistor T4, and the second electrode of the second transistor T2 is connected to the first node N1;

[0074] A control electrode of the fourth transistor T4 is connected to the second scan signal line S2 , and a first electrode of the fourth transistor T4 is connected to the second node N2 .

[0075] Figure 2 An exemplary structure of the reset subcircuit is shown. It is easy for those skilled in the art to understand that the implementation of the reset subcircuit is not limited to this, as long as its function can be achieved. In another exemplary embodiment, the control electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the first electrode of the fourth transistor T4; the control electrode of the fourth transistor T4 is connected to the second scan signal line S2, and the second electrode of the fourth transistor T4 is connected to the first node N1.

[0076] In an exemplary embodiment, Figure 3 The equivalent circuit diagram of the compensation sub-circuit, the driving sub-circuit and the writing sub-circuit provided in the embodiment of the present disclosure is as follows: Figure 3 As shown, the compensation sub-circuit provided in the embodiment of the present disclosure includes a sixth transistor T6 and a storage capacitor C1, the driving sub-circuit includes a third transistor T3, and the writing sub-circuit includes a fifth transistor T5.

[0077] The control electrode of the sixth transistor T6 is connected to the first scan signal line S1, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first node N1;

[0078] One end of the storage capacitor C1 is connected to the first node N1, and the other end of the storage capacitor C1 is connected to the first power line VDD;

[0079] The control electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3;

[0080] A control electrode of the fifth transistor T5 is connected to the first scan signal line S1 , a first electrode of the fifth transistor T5 is connected to the data signal line Data, and a second electrode of the fifth transistor T5 is connected to the second node N2 .

[0081] Figure 3An exemplary structure of the compensation sub-circuit, the driving sub-circuit and the writing sub-circuit is shown in FIG. It is easy for those skilled in the art to understand that the implementation of the compensation sub-circuit, the driving sub-circuit and the writing sub-circuit is not limited thereto, as long as their respective functions can be achieved.

[0082] In an exemplary embodiment, Figure 4 The equivalent circuit diagram of the first light-emitting control subcircuit and the second light-emitting control subcircuit provided in the embodiment of the present disclosure is as follows: Figure 4 As shown, the first light-emitting control subcircuit provided in the embodiment of the present disclosure includes a first transistor T1, and the second light-emitting control subcircuit includes a seventh transistor T7.

[0083] The control electrode of the first transistor T1 is connected to the first scan signal line S1, the first electrode of the first transistor T1 is connected to the first power line VDD, and the second electrode of the first transistor T1 is connected to the second node N2;

[0084] A control electrode of the seventh transistor T7 is connected to the second scan signal line S2 , a first electrode of the seventh transistor T7 is connected to the third node N3 , and a second electrode of the seventh transistor T7 is connected to the fourth node N4 .

[0085] Figure 4 An exemplary structure of the first light-emitting control subcircuit and the second light-emitting control subcircuit is shown in FIG. It is easy for a person skilled in the art to understand that the implementation of the first light-emitting control subcircuit and the second light-emitting control subcircuit is not limited thereto, as long as their respective functions can be realized.

[0086] Figure 5a An equivalent circuit diagram of a pixel circuit provided by an embodiment of the present disclosure is shown in FIG. Figure 5a As shown, in the pixel circuit provided by the embodiment of the present disclosure, the reset subcircuit includes: a second transistor T2 and a fourth transistor T4; the compensation subcircuit includes a sixth transistor T6 and a storage capacitor C1, the drive subcircuit includes a third transistor T3, and the write subcircuit includes a fifth transistor T5; the first light-emitting control subcircuit includes a first transistor T1, and the second light-emitting control subcircuit includes a seventh transistor T7.

[0087] The control electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the second electrode of the fourth transistor T4, and the second electrode of the second transistor T2 is connected to the first node N1;

[0088] A control electrode of the fourth transistor T4 is connected to the second scan signal line S2, and a first electrode of the fourth transistor T4 is connected to the second node N2;

[0089] The control electrode of the sixth transistor T6 is connected to the first scan signal line S1, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first node N1;

[0090] One end of the storage capacitor C1 is connected to the first node N1, and the other end of the storage capacitor C1 is connected to the first power line VDD;

[0091] The control electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3;

[0092] A control electrode of the fifth transistor T5 is connected to the first scan signal line S1, a first electrode of the fifth transistor T5 is connected to the data signal line Data, and a second electrode of the fifth transistor T5 is connected to the second node N2;

[0093] The control electrode of the first transistor T1 is connected to the first scan signal line S1, the first electrode of the first transistor T1 is connected to the first power line VDD, and the second electrode of the first transistor T1 is connected to the second node N2;

[0094] A control electrode of the seventh transistor T7 is connected to the second scan signal line S2 , a first electrode of the seventh transistor T7 is connected to the third node N3 , and a second electrode of the seventh transistor T7 is connected to the fourth node N4 .

[0095] Figure 5b Another equivalent circuit diagram of a pixel circuit provided by an embodiment of the present disclosure is shown in FIG. Figure 5b As shown, in the pixel circuit provided by the embodiment of the present disclosure, the reset subcircuit includes: a second transistor T2 and a fourth transistor T4; the compensation subcircuit includes a sixth transistor T6 and a storage capacitor C1, the drive subcircuit includes a third transistor T3, and the write subcircuit includes a fifth transistor T5; the first light-emitting control subcircuit includes a first transistor T1, and the second light-emitting control subcircuit includes a seventh transistor T7.

[0096] The control electrode of the second transistor T2 is connected to the first scanning signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the first electrode of the fourth transistor T4;

[0097] A control electrode of the fourth transistor T4 is connected to the second scan signal line S2, and a second electrode of the fourth transistor T4 is connected to the first node N1;

[0098] The control electrode of the sixth transistor T6 is connected to the first scan signal line S1, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first node N1;

[0099] One end of the storage capacitor C1 is connected to the first node N1, and the other end of the storage capacitor C1 is connected to the first power line VDD;

[0100] The control electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3;

[0101] A control electrode of the fifth transistor T5 is connected to the first scan signal line S1, a first electrode of the fifth transistor T5 is connected to the data signal line Data, and a second electrode of the fifth transistor T5 is connected to the second node N2;

[0102] The control electrode of the first transistor T1 is connected to the first scan signal line S1, the first electrode of the first transistor T1 is connected to the first power line VDD, and the second electrode of the first transistor T1 is connected to the second node N2;

[0103] A control electrode of the seventh transistor T7 is connected to the second scan signal line S2 , a first electrode of the seventh transistor T7 is connected to the third node N3 , and a second electrode of the seventh transistor T7 is connected to the fourth node N4 .

[0104] Figure 5a and Figure 5b The exemplary structures of the reset subcircuit, the compensation subcircuit, the drive subcircuit, the write subcircuit, the first light-emitting control subcircuit and the second light-emitting control subcircuit are shown. It is easy for those skilled in the art to understand that the implementation of the above subcircuits is not limited to this, as long as their respective functions can be achieved.

[0105] In an exemplary embodiment, the light emitting element EL may be an organic light emitting diode (OLED) or any other type of light emitting diode.

[0106] In an exemplary embodiment, Figure 5a and Figure 5b As shown, the first transistor T1 , the third transistor T3 , the fourth transistor T4 and the seventh transistor T7 are all P-type thin film transistors, and the second transistor T2 , the fifth transistor T5 and the sixth transistor T6 are all N-type thin film transistors.

[0107] In an exemplary embodiment, the N-type thin film transistor may be a low temperature polysilicon (LTPS) thin film transistor (TFT), and the P-type thin film transistor may be an indium gallium zinc oxide (IGZO) thin film transistor; or, the N-type thin film transistor may be an IGZO thin film transistor, and the P-type thin film transistor may be an LTPS thin film transistor.

[0108] In an exemplary embodiment, the first transistor T1 , the third transistor T3 , the fourth transistor T4 and the seventh transistor T7 are all LTPS thin film transistors, and the second transistor T2 , the fifth transistor T5 and the sixth transistor T6 are IGZO thin film transistors.

[0109] In the present embodiment, the indium gallium zinc oxide thin film transistor generates less leakage current than the low-temperature polysilicon thin film transistor. Therefore, setting the second transistor T2, the fifth transistor T5 and the sixth transistor T6 as indium gallium zinc oxide thin film transistors can significantly reduce the leakage of the control electrode of the driving transistor during the light-emitting stage, thereby improving the problem of low-frequency and low-brightness flickering of the display panel.

[0110] In the following, the pixel circuit provided by the embodiment of the present disclosure is taken as an example in which the first transistor T1, the third transistor T3, the fourth transistor T4 and the seventh transistor T7 are all P-type thin film transistors, and the second transistor T2, the fifth transistor T5 and the sixth transistor T6 are all N-type thin film transistors. Figure 6 The working timing diagram shown in FIG. 1 is a detailed description of the working process of a pixel circuit unit in a frame period. Figure 5a and Figure 5b As shown, the pixel circuit provided by the embodiment of the present disclosure includes 7 transistor units (T1-T7), 1 capacitor unit (C1) and 3 signal lines (VDD, VSS and Data), wherein the first power line VDD continuously provides a high level signal, the second power line VSS continuously provides a low level signal, and the data signal line Data periodically provides a data voltage signal Vdata_H and a reset voltage signal Vdata_L. In an exemplary embodiment, its working process includes:

[0111] The first stage t1 is called the reset stage. The signal of the first scan signal line S1 is a high-level signal, the signal of the second scan signal line S2 is a low-level signal, and the data signal line Data outputs a reset voltage signal Vdata_L. The high-level signal of the first scan signal line S1 turns off the first transistor T1, and turns on the second transistor T2, the fifth transistor T5, and the sixth transistor T6. The low-level signal of the second scan signal line S2 turns on the fourth transistor T4 and the seventh transistor T7. The conduction of the fifth transistor T5, the fourth transistor T4, and the second transistor T2 causes the reset voltage signal Vdata_L of the data signal line Data to be written to the first node N1. The conduction of the sixth transistor T6 and the seventh transistor T7 causes the reset voltage signal Vdata_L of the first node N1 to be written to the fourth node N4. At this time, the signals of the first node N1 and the fourth node N4 are both the reset voltage signal Vdata_L provided by the data signal line Data. In this stage, the storage capacitor C1, the anode terminal voltage of the light-emitting element EL, and the gate voltage of the third transistor (i.e., the driving transistor) T3 are reset to complete the initialization. Since the first transistor T1 is turned off, the light emitting element EL does not emit light in this stage.

[0112] The second stage t2 is called the data writing stage. The signals of the first scanning signal line S1 and the second scanning signal line S2 are both high-level signals, and the data signal line Data outputs the data voltage signal Vdata_H. In this stage, since the second end of the storage capacitor C1 (i.e., the first node N1) is at a low level, the third transistor T3 is turned on. The high-level signals of the first scanning signal line S1 and the second scanning signal line S2 turn on the second transistor T2, the fifth transistor T5, and the sixth transistor T6, and turn off the first transistor T1, the fourth transistor T4, and the seventh transistor T7. The conduction of the fifth transistor T5, the third transistor T3, and the sixth transistor T6 causes the data voltage signal Vdata_H output by the data signal line Data to pass through the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on sixth transistor T6 to be provided to the first node N1, and the sum of the data voltage signal Vdata_H output by the data signal line Data and the threshold voltage Vth of the third transistor T3 is charged into the storage capacitor C1, and the voltage of the second end (first node N1) of the storage capacitor C1 is Vdata_H+Vth. Since the first transistor T1 and the seventh transistor T7 are turned off, the light emitting element EL does not emit light in this stage.

[0113] The third stage t3 is called the light-emitting stage, and the signals of the first scanning signal line S1 and the second scanning signal line S2 are both low-level signals. The low-level signals of the first scanning signal line S1 and the second scanning signal line S2 turn on the first transistor T1, the fourth transistor T4 and the seventh transistor T7, and turn off the second transistor T2, the fifth transistor T5 and the sixth transistor T6. The power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode (i.e., the fourth node N4) of the light-emitting element EL through the turned-on first transistor T1, the third transistor T3 and the seventh transistor T7, and drives the light-emitting element EL to emit light.

[0114] During the pixel circuit driving process, the driving current flowing through the third transistor T3 (ie, the driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the first node N1 is Vdata_H+Vth, the driving current of the third transistor T3 is:

[0115] I=K*(Vgs-Vth) 2 =K*[(Vdata_H+Vth-Vdd)-Vth] 2 =K*[(Vdata_H-Vdd)] 2

[0116] Among them, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting element EL, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vdata_H is the data voltage output by the data signal line Data, and Vdd is the power supply voltage output by the first power supply line VDD.

[0117] It can be seen from the above formula that the current I flowing through the light emitting element EL has nothing to do with the threshold voltage Vth of the third transistor T3, thereby eliminating the influence of the threshold voltage Vth of the third transistor T3 on the current I and ensuring the uniformity of brightness.

[0118] Due to the influence of process instability, particles, temperature, etc. in the semiconductor manufacturing process, the threshold voltage Vth of the driving thin film transistor (DTFT) is often easily offset, which in turn causes uneven current through the light-emitting diode, resulting in uneven display (mura) on the screen. Figure 7a 3 is a signal simulation diagram of the pixel circuit of the embodiment of the present disclosure under the corresponding timing. Through the simulation, it can be known that the pixel circuit can emit light normally. Figure 7bWhen the threshold voltage Vth is -2V, -2.5V and -3V, and the Vdata voltage is 3V to 7V, the current Ioled passing through the light-emitting element in the light-emitting stage, under different Vth, the Ioled-Vdata curves of the pixel circuit are almost the same, indicating that the pixel circuit of the embodiment of the present disclosure achieves compensation for the threshold voltage Vth. Figure 7c The figure is a schematic diagram showing the change of the current Ioled flowing through the light-emitting element during the light-emitting stage with the threshold voltage Vth of the driving thin film transistor under different data voltages Vdata of the pixel circuit. When the data voltage Vdata is 4V, the current Ioled flowing through the light-emitting element during the light-emitting stage is about 110nA, and the change rate of Ioled with Vth is about 3.5%; when the data voltage Vdata is 5V, the current Ioled flowing through the light-emitting element during the light-emitting stage is about 20nA, and the change rate of Ioled with Vth is about 6%; when the data voltage Vdata is 6.5V, the current Ioled flowing through the light-emitting element during the light-emitting stage is about 0.8nA, and the change rate of Ioled with Vth is about 12%, which has a good Vth compensation effect.

[0119] Based on the above working timing, the pixel circuit eliminates the residual positive charge of the light-emitting element EL after the last light emission, realizes compensation for the gate voltage of the driving transistor, avoids the influence of the threshold voltage drift of the driving transistor on the driving current of the light-emitting element EL, and improves the uniformity of the displayed image and the display quality of the display panel.

[0120] Currently, display screens are developing towards narrow borders. To improve product competitiveness, display panels need to reduce the screen borders. The pixel circuit provided by the disclosed embodiment only needs one set of gate driver on array (GOA) circuits to drive the screen, thereby saving border space and achieving the purpose of reducing the screen border and improving the screen resolution.

[0121] Usually in the low temperature polysilicon (LTPS) thin film transistor pixel circuit, the leakage current of the switching thin film transistor is about 10-13A. This will cause the brightness of the OLED device to change within a frame due to the leakage of the control electrode of the driving thin film transistor DTFT during the light-emitting stage, which is visible to the human eye and causes flicker. Especially when the OLED screen works at low frequency and low brightness, the flickering phenomenon will be more obvious. This is a problem that needs to be solved urgently.

[0122] In the pixel circuit of the embodiment of the present disclosure, the switch transistors (T2, T5 and T6) connected to the driving thin film transistor are all indium gallium zinc oxide thin film transistors, and their leakage current can usually reach 10 -16A, which is used as the switching TFT of the pixel circuit and connected to the gate of the DTFT, can effectively reduce the leakage of the DTFT control electrode during the light-emitting stage, thereby improving the flicker problem of the OLED screen at low frequency and low brightness. Figure 8 It can be seen that when V data Less than 5.5V(I oled Greater than 8.6nA), at 60Hz and 1Hz, within one frame I oled The change rate is less than 0.35%. data When it is greater than 5.5V, I oled The rate of change of V increases. At 60Hz, V data 7V(I oled =0.47nA), within one frame I oled The maximum rate of change is -11.3%. At 1Hz, V data 6.5V(I oled =0.9nA), within one frame I oled The maximum change rate is 5.3%. Overall, at low brightness of 1Hz, I oled The change rate is better than 60Hz, indicating that the pixel circuit can improve the screen flicker problem under low frequency and low brightness.

[0123] In some other exemplary embodiments, Fig. 9 As shown, the two groups of scan signals provided by the first scan signal line S1 and the second scan signal line S2 can be output by different GOA circuits. Fig. 9 As shown, its working process includes:

[0124] The first stage t1 is called the reset stage. The signal of the first scan signal line S1 is a high-level signal, the signal of the second scan signal line S2 is a low-level signal, and the data signal line Data outputs a reset voltage signal Vdata_L. The high-level signal of the first scan signal line S1 turns off the first transistor T1, and turns on the second transistor T2, the fifth transistor T5, and the sixth transistor T6. The low-level signal of the second scan signal line S2 turns on the fourth transistor T4 and the seventh transistor T7. The conduction of the fifth transistor T5, the fourth transistor T4, and the second transistor T2 causes the reset voltage signal Vdata_L of the data signal line Data to be written to the first node N1. The conduction of the sixth transistor T6 and the seventh transistor T7 causes the reset voltage signal Vdata_L of the first node N1 to be written to the fourth node N4. At this time, the signals of the first node N1 and the fourth node N4 are both the reset voltage signal Vdata_L provided by the data signal line Data. In this stage, the storage capacitor C1, the anode terminal voltage of the light-emitting element EL, and the gate voltage of the third transistor (i.e., the driving transistor) T3 are reset to complete the initialization. Since the first transistor T1 is turned off, the light emitting element EL does not emit light in this stage.

[0125] The second stage t2 is called the data writing stage. The signals of the first scanning signal line S1 and the second scanning signal line S2 are both high-level signals, and the data signal line Data outputs the data voltage signal Vdata_H. In this stage, since the second end of the storage capacitor C1 (i.e., the first node N1) is at a low level, the third transistor T3 is turned on. The high-level signals of the first scanning signal line S1 and the second scanning signal line S2 turn on the second transistor T2, the fifth transistor T5, and the sixth transistor T6, and turn off the first transistor T1, the fourth transistor T4, and the seventh transistor T7. The conduction of the fifth transistor T5, the third transistor T3, and the sixth transistor T6 causes the data voltage signal Vdata_H output by the data signal line Data to pass through the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on sixth transistor T6 to be provided to the first node N1, and the sum of the data voltage signal Vdata_H output by the data signal line Data and the threshold voltage Vth of the third transistor T3 is charged into the storage capacitor C1, and the voltage of the second end (first node N1) of the storage capacitor C1 is Vdata_H+Vth. Since the first transistor T1 and the seventh transistor T7 are turned off, the light emitting element EL does not emit light in this stage.

[0126] The third stage t3 is called the light-emitting stage, and the signals of the first scanning signal line S1 and the second scanning signal line S2 are both low-level signals. The low-level signals of the first scanning signal line S1 and the second scanning signal line S2 turn on the first transistor T1, the fourth transistor T4 and the seventh transistor T7, and turn off the second transistor T2, the fifth transistor T5 and the sixth transistor T6. The power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode (i.e., the fourth node N4) of the light-emitting element EL through the turned-on first transistor T1, the third transistor T3 and the seventh transistor T7, and drives the light-emitting element EL to emit light.

[0127] In an exemplary embodiment, if Fig.10 and Fig.11 As shown, Fig.11 for Fig.10 A cross-sectional view taken along the AA direction, wherein the pixel circuit includes a substrate 10 and a first semiconductor layer, a first conductive layer, a second semiconductor layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer stacked on the substrate 10;

[0128] The first semiconductor layer includes an active layer of at least one polysilicon transistor, the first conductive layer includes a second scanning signal line 22 and a first electrode plate 23 of a storage capacitor, and an orthographic projection of the second scanning signal line 22 on the substrate overlaps with an orthographic projection of the active layer of the polysilicon transistor on the substrate 10;

[0129] The second semiconductor layer includes an active layer of at least one oxide transistor, the second conductive layer includes a second electrode 32 of the storage capacitor and a first scanning signal line 31, the third conductive layer includes a second auxiliary signal line 42, and an orthographic projection of the first scanning signal line 31 on the substrate 10, an orthographic projection of the second auxiliary signal line 42 on the substrate 10 and an orthographic projection of the active layer of the oxide transistor on the substrate 10 all have overlapping areas;

[0130] The fourth conductive layer includes first and second electrodes of a plurality of polysilicon transistors and first and second electrodes of a plurality of oxide transistors, and the fifth conductive layer includes a data signal line and a first power line.

[0131] In an exemplary embodiment, the polysilicon transistor includes a first transistor T1 , a third transistor T3 , a fourth transistor T4 , and a seventh transistor T7 ; and the oxide transistor includes a second transistor T2 , a fifth transistor T5 , and a sixth transistor T6 .

[0132] In an exemplary embodiment, the pixel circuit includes a first region R1 and a second region R2;

[0133] The first transistor T1 , the third transistor T3 and the storage capacitor C1 are disposed in the first region, and the second transistor T2 , the fourth transistor T4 to the seventh transistor T7 , the first scan signal line 31 and the second scan signal line 22 are disposed in the second region.

[0134] The structure of the display substrate of the embodiment of the present disclosure is exemplified by the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as depositing a film layer, coating a photoresist, mask exposure, development, etching and stripping the photoresist. Deposition can be any one or more selected from sputtering, evaporation and chemical vapor deposition, coating can be any one or more selected from spraying and spin coating, and etching can be any one or more selected from dry etching and wet etching. "Thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". When the "thin film" still requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" mentioned in the present disclosure means that A and B are formed simultaneously by the same patterning process. “The orthographic projection of A includes the orthographic projection of B” means that the orthographic projection of B falls within the range of the orthographic projection of A, or the orthographic projection of A covers the orthographic projection of B.

[0135] In some exemplary embodiments, Figure 4 The preparation process of the display substrate shown may include the following steps:

[0136] In an exemplary embodiment, a process of preparing a display substrate may include the following operations.

[0137] (11) Forming a first semiconductor layer pattern. In an exemplary embodiment, forming the first semiconductor layer pattern may include: depositing a first insulating film and a first active layer film in sequence on the substrate 10; coating a layer of photoresist on the first active layer film, exposing and developing the photoresist using a single-tone mask, forming an unexposed area at the first active layer pattern position, retaining the photoresist, and forming a fully exposed area without photoresist at other positions; etching the first active layer film in the fully exposed area and stripping off the remaining photoresist to form a first insulating layer 91 and a first semiconductor layer pattern. The first insulating layer 91 is used to block the influence of ions in the substrate on the thin film transistor, and may be a composite film of silicon nitride SiNx, silicon oxide SiOx, or SiNx / SiOx. The first active layer film may be made of silicon material, and the silicon material includes amorphous silicon and polycrystalline silicon. The first active layer film may also be made of amorphous silicon a-Si, and formed into polycrystalline silicon through crystallization or laser annealing, such as Fig.12a and Figure 12b As shown, Figure 12b for Fig.12a Sectional view along AA direction.

[0138] like Fig.12a As shown, the first semiconductor layer of each sub-pixel may include a first active layer 11 of a first transistor T1, a third active layer 13 of a third transistor T3, a fourth active layer 14 of a fourth transistor T4, and a seventh active layer 17 of a seventh transistor T7, and the first active layer 11, the third active layer 13, and the fourth active layer 14 are an integrated structure connected to each other.

[0139] In an exemplary embodiment, the first active layer 11 of the first transistor T1 and the third active layer 13 of the third transistor T3 are disposed in the first region R1, and the fourth active layer 14 of the fourth transistor T4 and the seventh active layer 17 of the seventh transistor T7 are disposed in the second region R2. The fourth active layer 14 and the seventh active layer 17 both extend along the second direction Y. In an exemplary embodiment, the fourth active layer 14 and the seventh active layer 17 are equidistant from a boundary line of the first region R1 and the second region R2.

[0140] In an exemplary embodiment, the third active layer 13 may be shaped like a “X”, the first active layer 11 may be shaped like a “1”, and the fourth and seventh active layers 14 and 17 may be shaped like an “I”.

[0141] In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region. In an exemplary embodiment, the second region 11-2 of the first active layer 11 also serves as the first region 13-1 of the third active layer 13, that is, the second region 11-2 of the first active layer 11 and the first region 13-1 of the third active layer 13 are connected to each other. The first region 11-1 of the first active layer 11, the second region 13-2 of the third active layer 13, the first region 14-1 of the fourth active layer 14, the second region 14-2 of the fourth active layer 14, the first region 17-1 of the seventh active layer 17, and the second region 17-2 of the seventh active layer 17 are separately provided.

[0142] In an exemplary embodiment, the first semiconductor layer may be made of polysilicon (p-Si), that is, the first transistor T1 , the third transistor T3 , the fourth transistor T4 , and the seventh transistor T7 are LTPS thin film transistors.

[0143] like Figure 12bAs shown, after this process, the display substrate includes a first insulating layer 91 arranged on the substrate 10 and a first semiconductor layer arranged on the first insulating layer 91, and the first semiconductor layer may include a first active layer 11 of the first transistor T1, a third active layer 13 of the third transistor T3, a fourth active layer 14 of the fourth transistor T4 and a seventh active layer 17 of the seventh transistor T7.

[0144] (12) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a second insulating film and a first metal film in sequence on a substrate formed with the aforementioned pattern, patterning the first metal film through a patterning process to form a second insulating layer covering the first semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, wherein the first conductive layer pattern includes at least: a first gate block 21, a second scanning signal line 22, and a first electrode plate 23 of a storage capacitor, such as Fig.13a and Fig.13b As shown, Fig.13b for Fig.13a In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE 1) layer.

[0145] In an exemplary embodiment, the first gate block 21 and the first plate 23 of the storage capacitor are disposed in the first region R1. The second scan signal line 22 extends along the first direction X, and the second scan signal line 22 is disposed in the second region R2.

[0146] In an exemplary embodiment, an orthographic projection of the first gate block 21 on the substrate 10 overlaps with an orthographic projection of the first active layer 11 of the first transistor T1 on the substrate 10 , and the overlapping area between the first gate block 21 and the first active layer 11 of the first transistor T1 serves as the gate electrode of the first transistor T1 .

[0147] In an exemplary embodiment, the first electrode plate 23 may be rectangular, and the corners of the rectangle may be chamfered, and an orthographic projection of the first electrode plate 23 on the substrate 10 and an orthographic projection of the third active layer of the third transistor T3 on the substrate 10 have an overlapping area. In an exemplary embodiment, the first electrode plate 23 also serves as a gate electrode of the third transistor T3, and an overlapping area between the third active layer of the third transistor T3 and the first electrode plate 24 serves as a channel area of ​​the third transistor T3, and one end of the channel area is connected to the first area of ​​the third active layer, and the other end is connected to the second area of ​​the third active layer.

[0148] The overlapping area of ​​the second scan signal line 22 and the fourth active layer 14 of the fourth transistor T4 serves as the gate electrode of the fourth transistor T4 , and the overlapping area of ​​the second scan signal line 22 and the seventh active layer 17 of the seventh transistor T7 serves as the gate electrode of the seventh transistor T7 .

[0149] In an exemplary embodiment, after forming the first conductive layer pattern, the first conductive layer can be used as a shield to perform conductorization on the semiconductor layer. The semiconductor layer in the area shielded by the first conductive layer forms the channel region of the first transistor T1, the third transistor T3, the fourth transistor T4 and the seventh transistor T7, and the semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first area and the second area of ​​the first active layer, the third active layer, the fourth active layer and the seventh active layer are all conductorized.

[0150] like Fig.13b As shown, after this process, the display substrate includes a first insulating layer 91 arranged on the base 10, a first semiconductor layer arranged on the first insulating layer 91, a second insulating layer 92 covering the first semiconductor layer and a first conductive layer arranged on the second insulating layer 92, and the first conductive layer may include a first gate block 21, a second scanning signal line 22 and a first plate 23 of a storage capacitor.

[0151] (13) Forming a second semiconductor layer pattern. In an exemplary embodiment, forming the second semiconductor layer pattern may include: depositing a third insulating film and a second semiconductor film in sequence on the substrate on which the aforementioned pattern is formed, patterning the second semiconductor film by a patterning process to form a third insulating layer 93 covering the substrate, and a second semiconductor layer disposed on the third insulating layer 93, such as Fig.14a and Fig.14b As shown, Fig.14b for Fig.14a Sectional view along AA direction.

[0152] like Fig.14a As shown, the second semiconductor layer of each sub-pixel may include a fifth active layer 15 of a fifth transistor T5, a second active layer 12 of a second transistor T2, and a sixth active layer 16 of a sixth transistor T6. In an exemplary embodiment, the fifth active layer 15, the second active layer 12, and the sixth active layer 16 all extend along the second direction Y, and are all disposed in the second region R2. In an exemplary embodiment, the fifth active layer 15, the second active layer 12, and the sixth active layer 16 may all be in an "I" shape, and are all located on a side of the second scan line 22 close to the first region R1. In an exemplary embodiment, the edges of the fifth active layer 15, the second active layer 12, and the sixth active layer 16 adjacent to the first region R1 overlap with the orthographic projection of the boundary line between the first region R1 and the second region R2 on the substrate 10.

[0153] In an exemplary embodiment, the second semiconductor layer may be formed of oxide, that is, the fifth transistor, the second transistor, and the sixth transistor may be oxide thin film transistors.

[0154] like Fig.14bAs shown, in a plane perpendicular to the substrate, a first insulating layer 91 is arranged on the substrate 10, a first semiconductor layer is arranged on the first insulating layer 91, a second insulating layer 92 covers the first semiconductor layer, a first conductive layer is arranged on the second insulating layer 92, a third insulating layer 93 covers the first conductive layer, a second semiconductor layer is arranged on the third insulating layer 93, and the second semiconductor layer includes at least a fifth active layer 15, a second active layer 12 and a sixth active layer 16.

[0155] (14) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a fourth insulating film and a second metal film in sequence on the substrate formed with the aforementioned pattern, patterning the second metal film using a patterning process to form a fourth insulating layer 94 covering the first conductive layer, and a second conductive layer pattern disposed on the fourth insulating layer 94, wherein the second conductive layer pattern includes at least: a first scanning signal line 31 and a second electrode plate 32 of a storage capacitor, such as Fig.15a and Fig.15b As stated, Fig.15b for Fig.15a In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE 2) layer.

[0156] like Fig.15a As shown, in an exemplary embodiment, the first scan signal line 31 extends along the first direction X, is disposed in the second region R2, and is located on the side of the second scan signal line 22 close to the first region R1. The orthogonal projection of the first scan signal line 31 on the substrate 10 overlaps with the orthogonal projection of the second active layer 12 of the second transistor T2 on the substrate 10, and the area where the first scan signal line 31 overlaps with the second active layer 12 of the second transistor T2 serves as the gate electrode of the second transistor T2. The orthogonal projection of the first scan signal line 31 on the substrate 10 overlaps with the orthogonal projection of the fifth active layer 15 of the fifth transistor T5 on the substrate 10, and the area where the first scan signal line 31 overlaps with the fifth active layer 15 of the fifth transistor T5 serves as the gate electrode of the fifth transistor T5. The orthogonal projection of the first scan signal line 31 on the substrate 10 overlaps with the orthogonal projection of the sixth active layer 16 of the sixth transistor T6 on the substrate 10, and the area where the first scan signal line 31 overlaps with the sixth active layer 16 of the sixth transistor T6 serves as the gate electrode of the sixth transistor T6.

[0157] In an exemplary embodiment, the contour of the second electrode plate 32 may be rectangular, and the corners of the rectangle may be chamfered, and the orthographic projection of the second electrode plate 32 on the substrate 10 and the orthographic projection of the first electrode plate 23 on the substrate 10 have an overlapping area. An opening 33 is provided on the second electrode plate 32, and the opening 33 may be located in the middle of the second electrode plate 32. The opening 33 may be rectangular, so that the second electrode plate 32 forms a ring structure. The opening 33 exposes the fourth insulating layer 94 covering the first electrode plate 23, and the orthographic projection of the first electrode plate 23 on the substrate 10 includes the orthographic projection of the opening 33 on the substrate 10. In an exemplary embodiment, the opening 33 is configured to accommodate a first via hole formed subsequently, and the first via hole is located in the opening 33 and exposes the first electrode plate 23, so that the second electrode of the second transistor T2, the first electrode of the sixth transistor T6, and the gate electrode of the third transistor T3 are connected to the first electrode plate 23.

[0158] In an exemplary embodiment, an orthographic projection of an edge of the second electrode plate 32 adjacent to the second region R2 on the substrate 10 overlaps with an orthographic projection of a boundary line between the first region R1 and the second region R2 on the substrate 10 .

[0159] like Fig.15b As shown, in a plane perpendicular to the substrate 10, a first insulating layer 91 is arranged on the substrate 10, a first semiconductor layer is arranged on the first insulating layer 91, a second insulating layer 92 covers the first semiconductor layer, a first conductive layer is arranged on the second insulating layer 92, a third insulating layer 93 covers the first conductive layer, a second semiconductor layer is arranged on the third insulating layer 93, a fourth insulating layer 94 covers the second semiconductor layer, a second conductive layer is arranged on the fourth insulating layer 94, and the second conductive layer includes at least a first scanning signal line 31 and a second electrode 32 of a storage capacitor.

[0160] (15) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern may include: depositing a fifth insulating film and a third metal film in sequence on the substrate on which the aforementioned pattern is formed, patterning the fifth insulating film and the third metal film respectively using a patterning process to form a fifth insulating layer 95 disposed on the second conductive layer, and a third conductive layer pattern disposed on the fifth insulating layer 95, wherein the third conductive layer pattern includes at least: a first auxiliary signal line 41 and a second auxiliary signal line 42, such as Fig.13a and Fig.13b As shown, Fig.13b for Fig.13a In an exemplary embodiment, the third conductive layer may be referred to as a third gate metal (GATE3) layer.

[0161] like Fig.16aAs shown, in an exemplary embodiment, the first auxiliary signal line 41 extends along the second direction Y and is disposed in the first region R1. The shape of the first auxiliary signal line 41 may be "1"-shaped. The first auxiliary signal line 41 is connected to the first electrode plate 23 through a via hole formed subsequently.

[0162] like Fig.16a As shown, in an exemplary embodiment, the second auxiliary signal line 42 extends along the first direction X and is arranged in the second region R2. The second auxiliary signal line 42 is connected to the first scanning signal line 31 through a via hole on the fifth insulating layer 95 (the via hole can be arranged in the frame area, not shown in the figure).

[0163] like Fig.16a As shown, the orthographic projection of the second auxiliary signal line 42 on the substrate 10 overlaps with the orthographic projection of the second active layer 12 of the second transistor T2 on the substrate 10, and the area where the first scan signal line 31, the second auxiliary signal line 42 overlap with the second active layer 12 of the second transistor T2 serves as the double-gate structure of the second transistor T2. The orthographic projection of the second auxiliary signal line 42 on the substrate 10 overlaps with the orthographic projection of the fifth active layer 15 of the fifth transistor T5 on the substrate 10, and the area where the first scan signal line 31, the second auxiliary signal line 42 overlaps with the fifth active layer 15 of the fifth transistor T5 serves as the double-gate structure of the fifth transistor T5. The orthographic projection of the second auxiliary signal line 42 on the substrate 10 overlaps with the orthographic projection of the sixth active layer 16 of the sixth transistor T6 on the substrate 10, and the area where the first scan signal line 31, the second auxiliary signal line 42 overlaps with the sixth active layer 16 of the sixth transistor T6 serves as the double-gate structure of the sixth transistor T6.

[0164] like Fig.16b As shown, in a plane perpendicular to the substrate, a first insulating layer 91 is disposed on the substrate 10, a first semiconductor layer is disposed on the first insulating layer 91, a second insulating layer 92 covers the first semiconductor layer, a first conductive layer is disposed on the second insulating layer 92, a third insulating layer 93 covers the first conductive layer, a second semiconductor layer is disposed on the third insulating layer 93, a fourth insulating layer 94 covers the second semiconductor layer, a second conductive layer is disposed on the fourth insulating layer 94, a fifth insulating layer 95 is disposed on the second conductive layer, and a third conductive layer is disposed on the fifth insulating layer 95. The second conductive layer includes at least a first auxiliary signal line 41 and a second auxiliary signal line 42.

[0165] (16) Forming a via pattern. In an exemplary embodiment, forming the via pattern may include: depositing a sixth insulating film on the substrate on which the aforementioned pattern is formed, patterning the sixth insulating film using a patterning process to form a sixth insulating layer covering the third conductive layer, wherein the sixth insulating layer is provided with a plurality of vias, and the plurality of vias include at least a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16, and a seventeenth via V17, as shown in FIG. Fig.17a and Fig.17b As shown, Fig.17b for Fig.17a Sectional view along AA direction.

[0166] like Fig.17a As shown, in an exemplary embodiment, the first via hole V1 is located in the opening 33 of the second electrode plate 32, the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the opening 33 on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer and the third insulating layer in the first via hole V1 are etched away to expose the surface of the first electrode plate 23. In an exemplary embodiment, the second via hole V2 is located in the first region R1, and the sixth insulating layer in the second via hole V2 is etched away to expose the surface of the first auxiliary signal line 41. In an exemplary embodiment, the third via hole V3 and the fourth via hole V4 are both located in the second region R2, and the sixth insulating layer, the fifth insulating layer and the fourth insulating layer in the third via hole V3 are etched away to expose the surface of the second region of the second active layer, and the sixth insulating layer, the fifth insulating layer and the fourth insulating layer in the fourth via hole V4 are etched away to expose the surface of the first region of the sixth active layer. The first via hole V1, the second via hole V2, the third via hole V3 and the fourth via hole V4 are configured to connect the second electrode of the second transistor T2, the first electrode of the sixth transistor T6, the first auxiliary signal line 41 and the gate electrode of the third transistor T3 formed subsequently to the first electrode plate 23 through the via holes.

[0167] In an exemplary embodiment, the fifth via hole V5 is located in the area where the second electrode plate 32 is located, and the orthographic projection of the fifth via hole V5 on the substrate is located within the range of the orthographic projection of the second electrode plate 32 on the substrate. The sixth insulating layer and the fifth insulating layer in the fifth via hole V5 are etched away to expose the surface of the second electrode plate 32. In an exemplary embodiment, the sixth via hole V6 is located in the first area R1, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer in the sixth via hole V6 are etched away to expose the surface of the first area of ​​the first active layer. The fifth via hole V5 and the sixth via hole V6 are configured to connect a subsequently formed power connection line to the second electrode plate 32 and the first electrode of the first transistor T1 through the via hole.

[0168] In an exemplary embodiment, the seventh via hole V7 is located in the second region R2, and the sixth insulating layer, the fifth insulating layer, and the fourth insulating layer in the seventh via hole V7 are etched away to expose the surface of the first region of the fifth active layer. The seventh via hole V7 is configured to connect a subsequently formed data connection line to the first electrode of the fifth transistor T5 through the via hole.

[0169] In an exemplary embodiment, the eighth via hole V8 is located in the first region R1, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, and the third insulating layer in the eighth via hole V8 are etched away, exposing the surface of the first gate block 21. In an exemplary embodiment, the ninth via hole V9 is located in the second region R2, and the sixth insulating layer in the ninth via hole V9 is etched away, exposing the surface of the second auxiliary signal line 42. The eighth via hole V8 and the ninth via hole V9 are configured to connect the first gate block 21 to the second auxiliary signal line 42 through the via hole.

[0170] In an exemplary embodiment, the tenth via hole V10 and the eleventh via hole V11 are both located in the second region R2, the sixth insulating layer, the fifth insulating layer and the fourth insulating layer in the tenth via hole V10 are etched away, exposing the surface of the second region of the fifth active layer, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the eleventh via hole V11 are etched away, exposing the surface of the first region of the fourth active layer. The tenth via hole V10 and the eleventh via hole V11 are configured to connect the second electrode of the fifth transistor T5 formed subsequently to the first electrode of the fourth transistor T4 through the via hole.

[0171] In an exemplary embodiment, the twelfth via hole V12 and the thirteenth via hole V13 are both located in the second region R2, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer in the twelfth via hole V12 are etched away to expose the surface of the second region of the fourth active layer, and the sixth insulating layer, the fifth insulating layer, and the fourth insulating layer in the eleventh via hole V11 are etched away to expose the surface of the first region of the second active layer. The twelfth via hole V12 and the thirteenth via hole V13 are configured to connect the second electrode of the fourth transistor T4 formed subsequently to the first electrode of the second transistor T2 through the via hole.

[0172] In an exemplary embodiment, the seventeenth via hole V17 is located in the second region R2, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer in the seventeenth via hole V17 are etched away to expose the surface of the second region of the seventh active layer. The seventeenth via hole V17 is configured to connect the second electrode of the subsequently formed seventh transistor T7 to the anode connection line through the via hole.

[0173] like Fig.17a and 17b As shown, in a plane perpendicular to the substrate, a first insulating layer 91 is arranged on the substrate 10, a first semiconductor layer is arranged on the first insulating layer 91, a second insulating layer 92 covers the first semiconductor layer, a first conductive layer is arranged on the second insulating layer 92, a third insulating layer 93 covers the first conductive layer, a second semiconductor layer is arranged on the third insulating layer 93, a fourth insulating layer 94 covers the second semiconductor layer, a second conductive layer is arranged on the fourth insulating layer 94, a fifth insulating layer 95 is arranged on the second conductive layer, a third conductive layer is arranged on the fifth insulating layer 95, a sixth insulating layer 96 covers the third conductive layer, and a plurality of vias are arranged on the sixth insulating layer 96.

[0174] (17) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth metal film on the substrate on which the aforementioned pattern is formed, patterning the fourth metal film using a patterning process to form a fourth conductive layer disposed on the sixth insulating layer 96, the fourth conductive layer at least including: a first connection electrode 51, a power connection line 52, a data connection line 53, a second connection electrode 54, a third connection electrode 55, a fourth connection electrode 56, a fifth connection electrode 57, and a sixth connection electrode 58, as shown in FIG. Fig.18a and Fig.18b As shown, Fig.18b for Fig.18a In an exemplary embodiment, the fourth conductive layer may be referred to as a first source-drain metal (SD1) layer.

[0175] like Fig.18aAs shown, in the exemplary embodiment, the first connection electrode 51 is disposed in the first region R1 and the second region R2, and is connected to the first electrode plate 23 through the first via hole V1 on the one hand, and is connected to the first auxiliary signal line 41 through the second via hole V2 on the other hand, and is connected to the second active layer through the third via hole V3, and is connected to the sixth active layer through the fourth via hole V4. The first connection electrode 51 is configured to interconnect the first electrode plate 23, the first auxiliary signal line 41, the second active layer, and the sixth active layer.

[0176] In an exemplary embodiment, a zigzag power connection line 52 is disposed in the first region R1, which is connected to the second electrode plate 32 through the fifth via V5 on the one hand, and to the first electrode of the first transistor through the sixth via V6 on the other hand. The power connection line 51 is configured to be connected to a first power line formed subsequently.

[0177] In an exemplary embodiment, the data connection line 53 extends along the second direction Y, is connected to the first electrode of the fifth transistor through the seventh via hole V7, and is configured to be connected to a subsequently formed data signal line.

[0178] In the exemplary embodiment, the second connection electrode 54 is disposed in the first region R1 and the second region R2, and is connected to the first gate block 21 through the eighth via hole V8 on one hand, and is connected to the second auxiliary signal line 42 through the ninth via hole V9 on the other hand, and the second connection electrode 54 is configured to connect the first gate block 21 with the second auxiliary signal line 42. Since the second auxiliary signal line 42 is connected to the first scanning signal line 31, the first gate block 21 is connected to the first scanning signal line 31.

[0179] In an exemplary embodiment, the third connection electrode 55 is disposed in the second region R2 and is connected to the fifth active layer through the tenth via hole V10 on one hand and to the fourth active layer through the eleventh via hole V11 on the other hand. The third connection electrode 55 is configured to connect the fifth active layer with the fourth active layer.

[0180] In an exemplary embodiment, the fourth connection electrode 56 is disposed in the second region R2, and is connected to the fourth active layer through the twelfth via hole V12 on the one hand, and is connected to the second active layer through the thirteenth via hole V13 on the other hand. The fourth connection electrode 56 is configured to connect the fourth active layer to the second active layer.

[0181] In an exemplary embodiment, the fifth connecting electrode 57 is disposed in the first region R1 and the second region R2, and is connected to the sixth active layer through the fourteenth via hole V14 on the one hand, and is connected to the seventh active layer through the fifteenth via hole V15 on the other hand, and is connected to the third active layer through the sixteenth via hole V16. The fifth connecting electrode 57 is configured to connect the sixth active layer, the seventh active layer and the third active layer.

[0182] In an exemplary embodiment, the sixth connection electrode 58 is disposed in the second region R2 and is connected to the seventh active layer through the seventeenth via hole V17 , and the sixth connection electrode 58 is configured to connect the seventh active layer to a subsequently formed anode connection electrode.

[0183] like Fig.18b As shown, in a plane perpendicular to the substrate, a first insulating layer 91 is arranged on the substrate 10, a first semiconductor layer is arranged on the first insulating layer 91, a second insulating layer 92 covers the first semiconductor layer, a first conductive layer is arranged on the second insulating layer 92, a third insulating layer 93 covers the first conductive layer, a second semiconductor layer is arranged on the third insulating layer 93, a fourth insulating layer 94 covers the second semiconductor layer, the second conductive layer is arranged on the fourth insulating layer 94, a fifth insulating layer 95 is arranged on the second conductive layer, the third conductive layer is arranged on the fifth insulating layer 95, a sixth insulating layer 96 covers the third conductive layer, a plurality of vias are arranged on the sixth insulating layer 96, the fourth conductive layer covers the plurality of vias, and the fourth conductive layer at least includes: a first connecting electrode 51, a power connecting line 52, a data connecting line 53, a second connecting electrode 54, a third connecting electrode 55, a fourth connecting electrode 56, a fifth connecting electrode 57 and a sixth connecting electrode 58.

[0184] (18) Forming patterns of the seventh insulating layer 97 and the first planar layer 98. In an exemplary embodiment, forming patterns of the seventh insulating layer 97 and the first planar layer 98 may include: first depositing a seventh insulating film on the substrate on which the aforementioned pattern is formed, then coating a first planar film, patterning the seventh insulating film and the first planar film respectively using a patterning process to form a seventh insulating layer 97 covering the fourth conductive layer and a first planar layer 98 covering the seventh insulating layer 97, wherein a plurality of via holes are disposed on the seventh insulating layer 97 and the first planar layer 98, and the plurality of via holes include at least an eighteenth via hole V18, a nineteenth via hole V19, and a twentieth via hole V20, such as Fig.19a and Fig.19b As shown, Fig.19b for Fig.18a In an exemplary embodiment, the seventh insulating layer 97 may be referred to as a passivation (PVX) layer.

[0185] like Fig.19a and Fig.19bAs shown, the eighteenth via hole V18 is located in the area where the power connection line 52 is located, the first flat layer and the seventh insulating layer in the eighteenth via hole V18 are removed, exposing the surface of the power connection line 52, and the eighteenth via hole V18 is configured to connect the first power line formed subsequently to the power connection line 52 through the via hole. The nineteenth via hole V19 is located in the first area R1, the first flat layer and the seventh insulating layer in the nineteenth via hole V19 are removed, exposing the surface of the data connection line 53, and the nineteenth via hole V19 is configured to connect the data signal line formed subsequently to the data connection line 53 through the via hole. The twentieth via hole V20 is located in the second area R2, the first flat layer and the seventh insulating layer in the twentieth via hole V20 are removed, exposing the surface of the sixth connection electrode 58, and the twentieth via hole V20 is configured to connect the anode connection line formed subsequently to the sixth connection electrode 58 through the via hole.

[0186] (23) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer may include: depositing a fifth metal film on the substrate having the aforementioned pattern, patterning the fifth metal film using a patterning process, and forming a fifth conductive layer disposed on the first planar layer 98, wherein the fifth conductive layer at least includes: a data signal line 61, a first power line 62, and an anode connection electrode 63, such as Fig.20a and Fig.20b As shown, Fig.20b for Fig.20a In an exemplary embodiment, the fifth conductive layer may be referred to as a second source-drain metal (SD2) layer.

[0187] like Fig.20a and Fig.20b As shown, the data signal line 61 extends along the second direction Y, and the data signal line 61 is connected to the data connection line 53 through the nineteenth via hole V19. Since the data connection line 53 is connected to the first electrode of the fifth transistor through the seventh via hole V7, the connection between the data signal line and the first electrode of the fifth transistor is realized, so that the data signal transmitted by the data signal line is written into the fifth transistor. The first power line 62 extends along the second direction Y, and the first power line 62 is connected to the power connection line 52 through the eighteenth via hole V18, so that the power connection line 52 has the same potential as the first power line 62. The anode connection electrode 63 can be rectangular, and the anode connection electrode 63 is connected to the sixth connection electrode 58 through the twentieth via hole V20. The anode connection electrode 63 is configured to be connected to the anode formed subsequently.

[0188] (24) Forming a pattern of the second planar layer 99. In an exemplary embodiment, forming the pattern of the second planar layer 99 may include: coating a second planar film on the substrate on which the aforementioned pattern is formed, patterning the second planar film using a patterning process to form a second planar layer 99 covering the fifth conductive layer, wherein at least a twenty-first via hole V21 is disposed on the second planar layer 99. Fig.10 and Fig.11 As shown, Fig.11 for Fig.10 Sectional view along AA direction.

[0189] like Fig.10 and Fig.11 As shown, in an exemplary embodiment, the twenty-first via hole V21 is located in the area where the anode connecting electrode 63 is located, the second flat layer in the twenty-first via hole V21 is removed to expose the surface of the anode connecting electrode 63, and the twenty-first via hole V21 is configured to connect the subsequently formed anode to the anode connecting electrode 63 through the via hole.

[0190] (25) Forming an anode pattern. In an exemplary embodiment, forming the anode pattern may include: depositing a transparent conductive film on the substrate on which the aforementioned pattern is formed, and patterning the transparent conductive film using a patterning process to form an anode disposed on the second planar layer.

[0191] In an exemplary embodiment, the anode is hexagonal, and the anode is connected to the anode connection electrode through the 21st via hole. Since the anode connection electrode is connected to the sixth connection electrode through the 20th via hole, and the sixth connection electrode is connected to the seventh active layer through the 17th via hole, the pixel driving circuit can drive the light emitting element to emit light.

[0192] In an exemplary embodiment, the subsequent preparation process may include: coating a pixel definition film, patterning the pixel definition film through a patterning process to form a pixel definition layer, wherein the pixel definition layer of each sub-pixel is provided with a pixel opening, and the pixel opening exposes the anode. An organic light-emitting layer is formed by an evaporation or inkjet printing process, and a cathode is formed on the organic light-emitting layer. An encapsulation layer is formed, and the encapsulation layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer, which can ensure that external water vapor cannot enter the light-emitting structure layer.

[0193] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may be, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked, and the materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the water and oxygen resistance of the substrate, and the material of the semiconductor layer may be amorphous silicon (a-si).

[0194] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer and the fifth conductive layer may be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single layer structure, or a multi-layer composite structure, such as Mo / Cu / Mo, etc. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, the sixth insulating layer and the seventh insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multi-layer or a composite layer. The first insulating layer is called the first buffer layer, which is used to improve the substrate's resistance to water and oxygen. The second insulating layer is called the first gate insulating layer (GI1), the third insulating layer is called the second buffer layer, the fourth insulating layer is called the second gate insulating layer (GI2), the fifth insulating layer is called the third gate insulating layer (GI3), the sixth insulating layer is called the interlayer insulating layer (ILD), and the seventh insulating layer is called the passivation layer (PVX). The first flat layer and the second flat layer can be made of organic materials, and the transparent conductive film can be made of indium tin oxide ITO or indium zinc oxide IZO. The first semiconductor layer can be made of polysilicon (p-Si), and the second semiconductor layer can be made of oxide.

[0195] The structure of the display substrate and its preparation process shown in the present disclosure are merely exemplary. In an exemplary embodiment, the corresponding structure can be changed and the composition process can be increased or decreased according to actual needs, and the present disclosure does not limit this.

[0196] The preparation of OLED displays is easily affected by process instability, foreign matter, temperature and other factors, which in turn causes the threshold voltage of the driver thin film transistor (DTFT) to shift. Under normal lighting voltage conditions, the opening degree of the driver thin film transistor is uneven, which easily leads to different currents passing through the light-emitting diodes, and the OLED display will have uneven brightness. In addition, mobile phone screens are currently developing towards narrow bezels. In order to improve product competitiveness, the screen bezel needs to be reduced. At the same time, since the leakage current of the commonly used LTPS 7T1C pixel driver circuit switch TFT is about 10 -13 A. This will cause the brightness of the OLED device to change within a frame due to leakage of the DTFT gate during the light-emitting stage, resulting in flicker. Especially when the OLED screen works at low frequency and low brightness, the flicker will be more obvious, which is a problem that needs to be solved urgently.

[0197] From the structure and preparation process of the display substrate described above, it can be seen that the pixel circuit provided by the embodiment of the present disclosure, by setting a reasonable layout structure, can not only save space, which is conducive to high-resolution display, but also has fewer leakage channels, improving the problem of screen flickering under low frequency and low brightness; at the same time, by setting a reasonable driving timing, internal compensation can be achieved, avoiding the influence of the threshold voltage drift of the driving sub-circuit on the driving current of the light-emitting element, and improving the uniformity of the displayed image and the display quality of the display panel. The preparation process disclosed in the present disclosure can be well compatible with the existing preparation process, the process is simple to realize, easy to implement, high production efficiency, low production cost, and high yield rate.

[0198] In an exemplary embodiment, if Fig.21a or Figure 21b As shown, two adjacent sub-pixels in the first direction X may be arranged in a mirror image.

[0199] In an exemplary embodiment, the power connection lines 52 in two adjacent sub-pixels in the first direction X may be an integrated structure connected to each other.

[0200] In an exemplary embodiment, for two sub-pixels adjacent in the first direction X, only one eighteenth via hole V18 for connecting the first power line 62 and the power connection line 52 may be provided. The eighteenth via hole V18 may be located in any one of the two sub-pixels adjacent in the first direction X, or may be located between the two sub-pixels adjacent in the first direction X.

[0201] In an exemplary embodiment, since the first active layer 11 is connected to the first power line 62 through the power connection line 52 , the first active layers 11 in two adjacent sub-pixels in the first direction X may be an integral structure connected to each other.

[0202] In an exemplary embodiment, the first gate blocks 21 in two adjacent sub-pixels in the first direction X may be an integrated structure connected to each other.

[0203] In an exemplary embodiment, the second connection electrodes 54 in two sub-pixels adjacent to each other in the first direction X may be an integral structure connected to each other.

[0204] In an exemplary embodiment, two adjacent sub-pixels in the first direction X may be provided with only one second connection electrode 54 for connecting the first gate block 21 and the second auxiliary signal line 42 and a set of corresponding via holes (i.e., the eighth via hole V8 and the ninth via hole V9, as shown in FIG. Fig.17a For example, a corresponding set of vias (ie, the eighth via V8 and the ninth via V9, as shown in FIG. Fig.17a At least one of the sub-pixels shown in the figure may also be located between two adjacent pixels; for example, the second connecting electrode 54 and the corresponding via hole may be located in any one of the two adjacent sub-pixels in the first direction X mentioned above.

[0205] In an exemplary embodiment, two adjacent sub-pixels in the first direction X may each be provided with a second connection electrode 54 for connecting the first gate block 21 and the second auxiliary signal line 42 and a set of corresponding via holes (i.e., an eighth via hole V8 and a ninth via hole V9, as shown in FIG. Fig.17a As shown), in this way, the second connection electrodes 54 in two adjacent sub-pixels form a parallel structure, thereby reducing the connection resistance.

[0206] like Figure 21b As shown, the first power lines 62 in two adjacent sub-pixels in the first direction X may be an integrated structure connected to each other, which can ensure that the anode is flatter after being arranged on the top.

[0207] Some embodiments of the present disclosure further provide a method for driving a pixel circuit, which is applied to the pixel circuit provided in the above embodiments. The pixel circuit includes: a driving subcircuit, a writing subcircuit, a compensation subcircuit, a reset subcircuit and a light-emitting element, as well as a first scanning signal line, a second scanning signal line, a data signal line, a first power line and a second power line. The pixel circuit has multiple scanning cycles. In one scanning cycle, the driving method includes the following steps:

[0208] Step S1, in the reset stage, the write subcircuit responds to the control signal of the first scan signal line to write the reset voltage signal of the data signal line into the second node; the reset subcircuit responds to the control signals of the first scan signal line and the second scan signal line to write the reset voltage signal of the second node into the first node; the compensation subcircuit responds to the control signal of the first scan signal line to write the reset voltage signal of the first node into the third node.

[0209] In this step, the first node and the third node are initialized by the write subcircuit, the reset subcircuit and the compensation subcircuit, and the storage capacitor, the anode terminal voltage of the light-emitting element and the control electrode voltage of the driving subcircuit are reset, thereby eliminating the residual positive charge at the anode of the light-emitting element after the last light emission and the residual charge in the storage capacitor.

[0210] In an exemplary embodiment, the pixel circuit further includes: a second light emitting control subcircuit, and step S1 further includes: the second light emitting control subcircuit writes the reset voltage signal of the third node into the fourth node in response to the control signal of the second scanning signal line.

[0211] Step S2, in the data writing stage, the writing subcircuit responds to the control signal of the first scanning signal line to write the data voltage signal of the data signal line into the second node, and the compensation subcircuit responds to the control signal of the first scanning signal line to compensate the first node.

[0212] In this step, a data voltage signal is provided to the data signal line. When the first node is charged to Vdata+Vth, the driving transistor is turned off, thereby compensating the threshold voltage of the driving transistor and improving the uniformity of the displayed image.

[0213] Step S3: In the light emitting stage, the driving sub-circuit provides a driving current to the third node in response to the control signal of the first node.

[0214] In this step, the driving current generated is:

[0215] I=K*(Vgs-Vth) 2 =K*[(Vdata_H+Vth-Vdd)-Vth] 2 =K*[(Vdata_H-Vdd)] 2

[0216] Among them, I is the driving current flowing through the driving transistor, that is, the driving current driving the light-emitting element, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the driving transistor, Vth is the threshold voltage of the driving transistor, Vdata is the data voltage output by the data signal line, and Vdd is the power supply voltage output by the first power supply line.

[0217] In an exemplary embodiment, the pixel circuit further includes: a first light-emitting control subcircuit and a second light-emitting control subcircuit, and step S3 further includes: the first light-emitting control subcircuit responds to the control signal of the first scanning signal line to provide the signal of the first power line to the second node, and the second light-emitting control subcircuit responds to the control signal of the second scanning signal line to allow a driving current to pass between the third node and the fourth node.

[0218] The driving method of the pixel circuit provided by the embodiment of the present disclosure eliminates the residual positive charge of the light-emitting element after the last light emission, realizes compensation for the gate voltage of the thin film transistor, and improves the uniformity of the displayed image and the display quality of the display panel. In addition, the driving method of the pixel circuit of the embodiment of the present disclosure has fewer leakage channels, which improves the screen flickering effect under low frequency. In addition, the pixel circuit of the embodiment of the present disclosure does not need to be designed with a double gate, which reduces the space occupied by the pixel circuit and improves the resolution of the screen.

[0219] Based on the same inventive concept, the embodiment of the present disclosure further provides a display device, which includes the pixel circuit provided in the above embodiment. The display device of the present disclosure can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame or a navigator. In an exemplary embodiment, the display device can be a wearable display device that can be worn on the human body in some way, such as a smart watch, a smart bracelet, etc.

[0220] There are a few points to note:

[0221] The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures may refer to the general design.

[0222] In the absence of conflict, the embodiments of the present disclosure, that is, the features in the embodiments, can be combined with each other to obtain new embodiments.

[0223] Although the embodiments disclosed in the present disclosure are as above, the contents described are only embodiments adopted to facilitate understanding of the present disclosure and are not intended to limit the present disclosure. Any technician in the field to which the present disclosure belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present disclosure, but the scope of patent protection of the present disclosure shall still be subject to the scope defined in the attached claims.

Claims

1. A pixel circuit, comprising a driving subcircuit, a writing subcircuit, a compensation subcircuit and a reset subcircuit, in: The driving subcircuit is connected to the first node, the second node and the third node respectively, and is configured to provide a driving current to the third node in response to a control signal of the first node; The writing subcircuit is connected to the first scanning signal line, the data signal line and the second node respectively, and is configured to write the signal of the data signal line into the second node in response to the control signal of the first scanning signal line, wherein the signal of the data signal line is a data voltage signal or a reset voltage signal; The compensation subcircuit is connected to the first power line, the first scan signal line, the first node and the third node respectively, and is configured to write the reset voltage signal to the third node in response to the control signal of the first scan signal line; and is also configured to compensate the first node in response to the control signal of the first scan signal line; The reset subcircuit is connected to the first scan signal line, the second scan signal line, the first node and the second node respectively, and is configured to write the reset voltage signal into the first node in response to control signals of the first scan signal line and the second scan signal line; The pixel circuit includes a substrate and a first semiconductor layer, a first conductive layer, a second semiconductor layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer stacked on the substrate; the first semiconductor layer includes an active layer of at least one polysilicon transistor, the first conductive layer includes a second scanning signal line and a first electrode plate of a storage capacitor, and an orthographic projection of the second scanning signal line on the substrate overlaps with an orthographic projection of the active layer of the polysilicon transistor on the substrate; the second semiconductor layer includes an active layer of at least one oxide transistor, the second conductive layer includes a second electrode plate of a storage capacitor and a first scanning signal line, the third conductive layer includes a second auxiliary signal line, and an orthographic projection of the first scanning signal line on the substrate, an orthographic projection of the second auxiliary signal line on the substrate overlaps with an orthographic projection of the active layer of the oxide transistor on the substrate; the fourth conductive layer includes first and second electrodes of a plurality of polysilicon transistors and first and second electrodes of a plurality of oxide transistors, and the fifth conductive layer includes a data signal line and a first power line.

2. The pixel circuit according to claim 1, in, The reset subcircuit includes a second transistor and a fourth transistor; The control electrode of the second transistor is connected to the first scanning signal line, the first electrode of the second transistor is connected to the second electrode of the fourth transistor, and the second electrode of the second transistor is connected to the first node; the control electrode of the fourth transistor is connected to the second scanning signal line, and the first electrode of the fourth transistor is connected to the second node; or, The control electrode of the second transistor is connected to the first scanning signal line, the first electrode of the second transistor is connected to the second node, and the second electrode of the second transistor is connected to the first electrode of the fourth transistor; the control electrode of the fourth transistor is connected to the second scanning signal line, and the second electrode of the fourth transistor is connected to the first node.

3. The pixel circuit according to claim 1, in, The compensation subcircuit includes a sixth transistor and a storage capacitor, the driving subcircuit includes a third transistor, and the writing subcircuit includes a fifth transistor; The control electrode of the sixth transistor is connected to the first scanning signal line, the first electrode of the sixth transistor is connected to the third node, and the second electrode of the sixth transistor is connected to the first node; One end of the storage capacitor is connected to the first node, and the other end of the storage capacitor is connected to the first power line; The control electrode of the third transistor is connected to the first node, the first electrode of the third transistor is connected to the second node, and the second electrode of the third transistor is connected to the third node; A control electrode of the fifth transistor is connected to the first scanning signal line, a first electrode of the fifth transistor is connected to the data signal line, and a second electrode of the fifth transistor is connected to the second node.

4. The pixel circuit according to claim 1, further comprising a first light emitting control subcircuit and a second light emitting control subcircuit. in: The first light emitting control subcircuit is respectively connected to the first power line, the first scanning signal line and the second node, and is configured to provide the signal of the first power line to the second node in response to the control signal of the first scanning signal line; The second light-emitting control subcircuit is connected to the second scanning signal line, the third node and the fourth node respectively, and is configured to write the reset voltage signal to the fourth node in response to the control signal of the second scanning signal line; and is also configured to allow a driving current to pass between the third node and the fourth node.

5. The pixel circuit according to claim 4, in, The first light emission control subcircuit includes a first transistor, and the second light emission control subcircuit includes a seventh transistor; The control electrode of the first transistor is connected to the first scanning signal line, the first electrode of the first transistor is connected to the first power line, and the second electrode of the first transistor is connected to the second node; A control electrode of the seventh transistor is connected to the second scanning signal line, a first electrode of the seventh transistor is connected to the third node, and a second electrode of the seventh transistor is connected to the fourth node.

6. The pixel circuit according to claim 1, in, The control signal of the first scanning signal line and the control signal of the second scanning signal line are provided through two adjacent stages of the same group of shift registers.

7. The pixel circuit according to claim 1, further comprising a first light-emitting control subcircuit and a second light-emitting control subcircuit, the reset subcircuit comprising a second transistor and a fourth transistor; the compensation subcircuit comprising a sixth transistor and a storage capacitor, the drive subcircuit comprising a third transistor, and the write subcircuit comprising a fifth transistor; the first light-emitting control subcircuit comprising a first transistor, and the second light-emitting control subcircuit comprising a seventh transistor; The control electrode of the second transistor is connected to the first scanning signal line, the first electrode of the second transistor is connected to the second electrode of the fourth transistor, the second electrode of the second transistor is connected to the first node, the control electrode of the fourth transistor is connected to the second scanning signal line, and the first electrode of the fourth transistor is connected to the second node ； Alternatively, the control electrode of the second transistor is connected to the first scanning signal line, the first electrode of the second transistor is connected to the second node, the second electrode of the second transistor is connected to the first electrode of the fourth transistor, the control electrode of the fourth transistor is connected to the second scanning signal line, and the second electrode of the fourth transistor is connected to the first node; The control electrode of the sixth transistor is connected to the first scanning signal line, the first electrode of the sixth transistor is connected to the third node, and the second electrode of the sixth transistor is connected to the first node; One end of the storage capacitor is connected to the first node, and the other end of the storage capacitor is connected to the first power line; The control electrode of the third transistor is connected to the first node, the first electrode of the third transistor is connected to the second node, and the second electrode of the third transistor is connected to the third node; The control electrode of the fifth transistor is connected to the first scanning signal line, the first electrode of the fifth transistor is connected to the data signal line, and the second electrode of the fifth transistor is connected to the second node; The control electrode of the first transistor is connected to the first scanning signal line, the first electrode of the first transistor is connected to the first power line, and the second electrode of the first transistor is connected to the second node; A control electrode of the seventh transistor is connected to the second scanning signal line, a first electrode of the seventh transistor is connected to the third node, and a second electrode of the seventh transistor is connected to a fourth node.

8. The pixel circuit according to claim 7, in, The first transistor, the third transistor, the fourth transistor and the seventh transistor are all first-type transistors, the second transistor, the fifth transistor and the sixth transistor are all second-type transistors, and the first-type transistors and the second-type transistors are of different transistor types.

9. The pixel circuit according to claim 8, in, The first type transistor is a P-type thin film transistor; the second type transistor is an N-type thin film transistor.

10. The pixel circuit according to claim 1, in, The polysilicon transistors include a first transistor, a third transistor, a fourth transistor, and a seventh transistor; and the oxide transistors include a second transistor, a fifth transistor, and a sixth transistor.

11. The pixel circuit according to claim 10, in, The pixel circuit includes a first area and a second area; The first transistor is disposed in the first region, the first scanning signal line is disposed in the second region, and the control electrode of the first transistor is connected to the first scanning signal line through a connecting electrode and a via hole.

12. The pixel circuit according to claim 10, in, The pixel circuit includes a first area and a second area; The seventh transistor, the fourth transistor and the second scanning signal line are all arranged in the second area, and the area where the second scanning signal line overlaps with the active layer of the fourth transistor serves as the control electrode of the fourth transistor, and the area where the second scanning signal line overlaps with the active layer of the seventh transistor serves as the control electrode of the seventh transistor.

13. The pixel circuit according to claim 10, in, The pixel circuit includes a first area and a second area; The third transistor is disposed in the first region, the first scan signal line and the seventh transistor are disposed in the second region, and the first scan signal line is disposed between the third transistor and the seventh transistor.

14. A display device, comprising the pixel circuit according to any one of claims 1 to 13.

15. A method for driving a pixel circuit, for driving the pixel circuit according to any one of claims 1 to 13, wherein the driving method include: In the reset phase, the writing subcircuit writes a reset voltage signal of the data signal line into the second node in response to a control signal of the first scanning signal line; The reset subcircuit writes the reset voltage signal of the second node into the first node in response to the control signals of the first scan signal line and the second scan signal line; The compensation sub-circuit writes the reset voltage signal of the first node into the third node in response to the control signal of the first scanning signal line; In the data writing stage, the writing subcircuit responds to the control signal of the first scanning signal line to write the data voltage signal of the data signal line into the second node, and the compensation subcircuit responds to the control signal of the first scanning signal line to compensate the first node; In the light emitting stage, the driving sub-circuit provides a driving current to the third node in response to a control signal of the first node.

16. The driving method according to claim 15, in, The control signal of the first scanning signal line and the control signal of the second scanning signal line are output by a group of array substrate row driving circuits.

17. The driving method according to claim 15, in, The control signal of the first scanning signal line and the control signal of the second scanning signal line are output by two groups of array substrate row driving circuits.

18. The driving method according to claim 16 or 17, in, The data signal line includes multiple signal cycles, each signal cycle provides a reset voltage signal and a data voltage signal for a row of sub-pixels, the duration of the data voltage signal is the duration of the data writing phase, and the duration of the reset voltage signal is the duration of the reset phase.

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