A power supply performance test method and related components

Abstract

The application relates to a power supply performance test method and related components, the method comprising: powering on a power supply performance test system according to a power-on logic sequence; performing pre-sweeping at a fixed duty cycle based on the powered-on power supply performance test system, obtaining voltage peak-to-peak values of all frequency points of each channel, and dividing the frequency points corresponding to the voltage peak-to-peak values into three sequence data sets according to a preset ratio; performing voltage dynamic tests on the three sequence data sets based on a preset rule, and judging whether the test results meet preset standards; and if yes, generating a test report. The application can simultaneously perform automatic tests on frequency points of multiple channels, can accurately and quickly find the worst power supply dynamic response frequency point, saves test and recording time, improves test precision, meanwhile, the collected data can form a three-dimensional voltage dynamic model of frequency, duty cycle and voltage, and more completely and accurately represent test results.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of server testing, and particularly relates to a power supply performance testing method and related components. BACKGROUND

[0002] With the development of server technology, the requirement for server quality is higher and higher. In an M7 platform server, a PCH (Platform Controller Hub) chip is responsible for connecting a PCIe (Peripheral Component Interface Extend) bus, an IDE (Integrated Development Environment) device, an I / O device and the like, and is an integrated south bridge of the entire server platform. The power supply performance of the PCH on a server mainboard directly affects the communication quality and service life of a hard disk and the like I / O device, and the efficiency, dynamic response, thermal compensation and DC regulation are key items that need to be considered in the power supply design of the server PCH. Therefore, how to test the PCH power supply of the server to determine the power supply performance of the PCH chip of the server is an important technical problem.

[0003] The prior art usually corrects an oscilloscope probe in a manual manner, sequentially powers on the equipment manually, and performs frequency sweeping in a manual traversal manner. The prior art cannot cover all frequency points, cannot collect the worst voltage variation dynamic data, and it is difficult to completely and accurately reflect the test result, and the test precision is poor. Meanwhile, seven to eight channels need to be tested, and the LPVRTT (Long Range Radio Transmission Technology) pull load current, duty cycle, frequency and the like parameters of each channel of the PCH power supply need to be manually adjusted, the data and waveforms are manually filled into a test report module, the data is analyzed, and the data testing and recording time is long. SUMMARY

[0004] Therefore, it is necessary to provide a power supply performance testing method and related components aiming at the above technical problems.

[0005] In one aspect, a power supply performance testing method is provided, applied to a power supply performance testing system, and the method comprises the following steps.

[0006] Step A: power on the power supply performance testing system according to a power-on logic sequence;

[0007] Step B: pre-sweep at a fixed duty cycle based on the power-on power supply performance testing system, obtain voltage peak values of all frequency points of each channel, and divide the frequency points corresponding to the voltage peak values into three sequence data sets according to a preset ratio;

[0008] Step C: performing voltage dynamic test on the three sequence data sets respectively based on preset rules, and judging whether the test results meet preset standards;

[0009] Step D: if yes, generating a test report.

[0010] In one of the embodiments, the power-on of the power supply performance test system according to the power-on logic sequence comprises: using the host computer to control the power distribution unit to sequentially power on the Intel pull tool, the oscilloscope, the digital multimeter and the data processing module; at the same time, using the host computer to control the digital multimeter to measure the pins of the platform manager hub to be tested, and judging whether a short circuit phenomenon occurs based on the measurement result; if no short circuit phenomenon occurs, powering on the platform manager hub to be tested.

[0011] In one of the embodiments, before the pre-sweeping, the method further comprises: using the host computer to collect voltage readings of the digital multimeter, the oscilloscope and the power supply performance test system in an idle state; based on the voltage readings, calculating a maximum error, comparing the maximum error with a first preset value; if the maximum error is greater than the first preset value, using the oscilloscope to correct the collected voltage; if the maximum error is less than or equal to the first preset value, entering the pre-sweeping step.

[0012] In one of the embodiments, the pre-sweeping at a fixed duty cycle to obtain voltage peak-to-peak values of all frequency points of each channel, and dividing the voltage peak-to-peak values into three sequence data sets according to a preset ratio comprises: adjusting the load of the power supply performance test system, determining the duty cycle of the sweep based on the adjusted load; pre-sweeping all channels based on the duty cycle, recording voltage peak-to-peak values of all frequency points of each channel, and arranging the voltage peak-to-peak values in ascending order; dividing the frequency points corresponding to the arranged voltage peak-to-peak values into three sequence data sets according to a preset ratio.

[0013] In one of the embodiments, the voltage dynamic test on the three sequence data sets respectively based on preset rules, and judging whether the test results meet preset standards comprises: sweeping the duty cycle of the frequency points in the three sequence data sets from a second preset value to a third preset value with a fixed step; when the sweep result contains a target frequency point that does not meet the preset standard, reducing the fixed step and re-sweeping; when the sweep results of the three sequence data sets do not contain the target frequency point, outputting the test result to form a test report.

[0014] On the other hand, a power supply performance test system is provided, which comprises:

[0015] A power distribution unit connected with the data acquisition module and the data processing module through power lines; a host computer connected with the power distribution unit based on a network between interconnection protocols, connected with the data processing module through a universal serial bus cable, and used for powering on the data processing module according to a power-on logic sequence; the host computer is connected with the data acquisition module through a universal interface bus cable, used for controlling a data acquisition process of the data acquisition module and powering on the data acquisition module according to the power-on logic sequence; and the data processing module is connected with the data acquisition module through a universal serial bus cable, used for performing a voltage dynamic test on a system to be tested.

[0016] In one of the embodiments, the data acquisition module further comprises a platform manager hub board to be tested, an oscilloscope, a digital multimeter and an Intel puller; the platform manager hub board is connected with the Intel puller through a pin joint; the Intel puller is connected with the oscilloscope through a differential probe; and the Intel puller is connected with the digital multimeter through a DuPont wire.

[0017] In another aspect, a power supply performance testing device is further provided, and the device comprises:

[0018] A power-on module, used for powering on a power supply performance testing system according to a power-on logic sequence;

[0019] A pre-sweeping module, used for pre-sweeping the power supply performance testing system at a fixed duty cycle after being powered on, acquiring voltage peak values of all frequency points of each channel, and dividing the frequency points corresponding to the voltage peak values into three sequence data sets according to a preset ratio;

[0020] A judgment module, used for performing voltage dynamic tests on the three sequence data sets respectively based on a preset rule, and judging whether a test result meets a preset standard;

[0021] A test report generation module, used for generating a test report when the test result meets the preset standard.

[0022] In still another aspect, a computer device is provided, comprising a memory, a processor and a computer program stored in the memory and executable on the processor, and the processor implements the following steps when executing the computer program:

[0023] Step A: powering on the power supply performance testing system according to a power-on logic sequence;

[0024] Step B: Based on the power supply performance test system after power-on, a pre-scan frequency is performed under a fixed duty cycle to obtain the peak-to-peak voltage of all frequency points of each channel, and the frequency points corresponding to the peak-to-peak voltage are divided into three sequence datasets according to a preset ratio;

[0025] Step C: Perform voltage dynamic tests on the three sequence datasets based on preset rules, and determine whether the test results meet the preset standards;

[0026] Step D: If satisfied, generate a test report.

[0027] In another aspect, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, performs the following steps:

[0028] Step A: Power on the power supply performance test system according to the power-on logic sequence;

[0029] Step B: Based on the power supply performance test system after power-on, a pre-scan frequency is performed under a fixed duty cycle to obtain the peak-to-peak voltage of all frequency points of each channel, and the frequency points corresponding to the peak-to-peak voltage are divided into three sequence datasets according to a preset ratio;

[0030] Step C: Perform voltage dynamic tests on the three sequence datasets based on preset rules, and determine whether the test results meet the preset standards;

[0031] Step D: If satisfied, generate a test report.

[0032] The aforementioned power supply performance testing method and related components include: powering on the power supply performance testing system according to the power-on logic sequence; performing a pre-scan frequency based on the power supply performance testing system after power-on under a fixed duty cycle to obtain the peak-to-peak voltage values ​​of all frequency points for each channel, and dividing the frequency points corresponding to the peak-to-peak voltage values ​​into three sequence datasets according to a preset ratio; performing voltage dynamic testing on the three sequence datasets respectively based on preset rules, and determining whether the test results meet preset standards; if they do, generating a test report. This application can be used for automated testing of multi-channel PCHs in servers, solving the problems of low testing efficiency, poor test result accuracy, and excessively long testing time caused by the mechanical repetition of manual testing. This application can simultaneously perform automated testing on the frequency points of multiple channels, accurately and quickly finding the frequency point with the worst dynamic response of the power supply, saving testing and recording time, improving testing accuracy, and at the same time, the collected data can form a three-dimensional voltage dynamic model of frequency, duty cycle, and voltage, more completely and accurately representing the test results. Attached Figure Description

[0033] Figure 1 This is a diagram illustrating the application environment of a power supply performance testing method in one embodiment.

[0034] Figure 2 a flowchart of a power supply performance test method in an embodiment;

[0035] Figure 3 another flowchart of a power supply performance test method in an embodiment;

[0036] Figure 4 a PCH power supply dynamic model diagram of a power supply performance test method in an embodiment;

[0037] Figure 5 a structural block diagram of a power supply performance test system in an embodiment;

[0038] Figure 6 a structural block diagram of a power supply performance test device in an embodiment;

[0039] Figure 7 an internal structural diagram of a computer device in an embodiment. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical scheme and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not to limit the present application.

[0041] The power supply performance test method provided by the present application can be applied in an application environment as shown in Figure 1 . The terminal 102 communicates with the data processing platform set on the server 104 through the network, wherein the terminal 102 can be, but is not limited to, various personal computers, notebook computers, smart phones, tablet computers and portable wearable devices, and the server 104 can be realized by an independent server or a server cluster composed of multiple servers.

[0042] Embodiment 1

[0043] In an embodiment, as shown in Figures 2-4 , a power supply performance test method is provided. Taking the terminal in Figure 1 as an example, the method includes the following steps:

[0044] S1: powering on the power supply performance test system according to the power-on logic sequence.

[0045] It should be noted that powering on the power supply performance test system according to the power-on logic sequence includes:

[0046] Open the PDX test software, and use the host computer to control the power distribution unit to sequentially power on the Intel load fixture, the oscilloscope, the digital multimeter, and the data processing module;

[0047] Meanwhile, the host computer controls the digital multimeter to measure the Pin pins of the platform manager hub to be tested, and determines whether a short circuit phenomenon occurs based on the measurement result.

[0048] When the multimeter measurement is 0Ω, it is a short circuit, and the rest indicates no short circuit. If no short circuit phenomenon occurs, the platform manager hub to be tested is powered on.

[0049] Further, after the system is powered on, the host computer collects voltage readings of the digital multimeter, the oscilloscope, and the PDX software in an empty load state before the pre-sweeping, wherein the voltage in the PDX software is the voltage of the entire power supply performance test system. Based on the voltage readings, the maximum error is calculated, which is the difference between any two of the PDX software, the digital multimeter, and the oscilloscope. The maximum error is compared with a first preset value: if the maximum error is greater than the first preset value, the collected voltage is corrected using the oscilloscope, and after the correction is completed, the initial test is started according to the command of the host computer; if the maximum error is less than or equal to the first preset value, the pre-sweeping step is entered. For example, the first preset value set in this embodiment is 2mv.

[0050] S2: Based on the pre-sweeping of the power supply performance test system at a fixed duty cycle after power-on, the voltage peak-to-peak value of each channel at all frequency points is obtained, and the voltage peak-to-peak value is divided into three sequence data sets according to a preset ratio.

[0051] It should be noted that when the BUCK circuit is stable, the amount of charging of the upper MOS capacitor when the upper MOS is turned on is equal to the amount of discharging of the capacitor when the lower MOS is turned on. Generally, in dynamic testing, the minimum and maximum voltages are operated around the effective value with half-peak operation, that is:

[0052] Vout max ≈Vout mean +0.5*Vpk_pk max

[0053] Vout min ≈Vout mean -0.5*Vpk_pk max

[0054] wherein Vout max represents the maximum value of the output voltage, Vout mean represents the effective value of the output voltage, Vpk_pk max represents the maximum value of the peak-to-peak value of the output voltage, and Vout minrepresenting a minimum value of the output voltage;

[0055] In the PCH-related POL circuit, the effective value is determined by the reference voltage and the voltage dividing resistor, which is generally a certain value, so the voltage peak-to-peak value can be used as an important indicator of dynamic testing. During dynamic testing, first, the load of the power supply performance test system is adjusted. When heavy load and light load each accounts for 50%, the load change causes the same capacitor charging and discharging time, which best reflects the dynamic characteristics of the power supply at this frequency, so the embodiment uses 50% as the duty cycle index of the first pre-sweeping.

[0056] Based on 50% duty cycle, pre-sweep all channels, record the voltage peak-to-peak value of each channel at all frequency points, and arrange them in ascending order;

[0057] According to the preset proportion, the frequency points corresponding to the arranged voltage peak-to-peak values are divided into three sequence data sets, wherein the preset proportion of the embodiment is 10%, 30% and 60%.

[0058] S3: Perform voltage dynamic testing on the three sequence data sets based on a preset rule, and determine whether the test result meets a preset standard.

[0059] It should be noted that the step is specifically:

[0060] The duty cycle of the frequency points in the three sequence data sets is scanned from the second preset value to the third preset value in a fixed step, specifically:

[0061] The duty cycle of the frequency points in the first sequence data set is scanned from 50% to 95% in a fixed step of 5%, wherein 50% and 95% correspond to the second preset value and the third preset value, respectively.

[0062] Record the maximum and minimum values obtained by scanning the frequency points. When the maximum and minimum values do not meet the preset standard (SPEC), the corresponding frequency point in the first sequence data set fails the dynamic test, the worst frequency point is determined, the oscilloscope captures the worst waveform image, the peripheral power supply is adjusted and optimized, and the load is pulled by changing the duty cycle mode. Reduce the duty cycle step to obtain a more accurate frequency point range, and test again to find the worst frequency point. The oscilloscope captures the worst waveform image, and the test is repeated until the scanning of the first sequence data set is completed and no target frequency point is found, wherein the recorded frequency point is defined as the current target frequency point. If the first sequence data set passes the test, i.e. after the scanning of the first sequence data set is completed and no target frequency point is found, the second and third sequence data sets are tested by repeating the above steps.

[0063] When none of the three sequence data sets finds a target frequency point that does not meet the SPEC after scanning, the test result is output.

[0064] S4: if yes, generate a test report.

[0065] Specifically, it is determined whether the voltage dynamic test meets the voltage SPEC. If yes, i.e., the scan results of the three sequence data sets do not contain the target frequency point, the PCH voltage, frequency, and duty cycle are output, a PCH power dynamic model is formed in a three-dimensional simulation system, a test report is generated, and power-down is performed according to the power-down sequence. The test report is as shown in Figure 4 The dynamic model as shown in Figure 4 The dynamic model as shown in

[0066] The application provides a high-efficiency server mainboard PCH test method. The test steps include: under a fixed duty cycle, automatically adjusting the load frequency of each channel to perform pre-scan frequency, obtaining a voltage peak Vpk-pk, sorting the frequency points according to Vpk-pk from large to small to obtain a first sequence, a second sequence, and a third sequence; for the frequency points in the first sequence, the load is performed by changing the duty cycle mode, and the maximum and minimum values of the voltage are recorded. If the value does not meet the SPEC standard frequency point, the scanning is ended. If no frequency point that does not meet the SPEC standard is found, the second and third sequences are sequentially scanned under different duty cycles. The application adopts a suitable test strategy, simultaneously performs automatic test on multiple channel frequency points, can accurately and quickly find the worst power dynamic response frequency point, saves test and recording time, improves test precision, and simultaneously forms a frequency, duty cycle, and voltage three-dimensional voltage dynamic model by using the collected data, which more clearly and specifically represents the test result.

[0067] It should be understood that, although Figures 2-3 the steps in the flowchart of Figures 2-3 at least one of the steps can include multiple sub-steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution order of the sub-steps or stages is not necessarily sequential, but can be performed in rotation or alternation with at least a part of other steps or sub-steps or stages of other steps.

[0068] Embodiment 2

[0069] In one embodiment, asFigure 5 As shown in the figure, a power supply performance test system is provided, comprising: a power distribution unit, a data acquisition module, a data processing module and a host computer, wherein:

[0070] The power distribution unit is connected with the data acquisition module and the data processing module through a power line;

[0071] The data acquisition module is connected with the data processing module through a universal serial bus cable;

[0072] The host computer is connected with the data processing module through the universal serial bus cable, and is connected with the power distribution unit based on the Internet Protocol.

[0073] In one embodiment, the data acquisition module comprises a platform manager hub test board, an oscilloscope, a digital multimeter and an Intel puller fixture;

[0074] The platform manager hub test board is connected with the Intel puller fixture through a pin joint;

[0075] The Intel puller fixture is connected with the oscilloscope through a differential probe;

[0076] The Intel puller fixture is connected with the digital multimeter through a DuPont line.

[0077] In one embodiment, the host computer is connected with the digital multimeter and the oscilloscope through a general-purpose interface bus cable, respectively, for controlling the acquisition process of the data acquisition module.

[0078] As Figure 5 As shown in the figure, the test system is an automatic programmable system, which can automatically test the power supply design of the mainstream PCH chip on the market. Specifically, the PCH test board (platform manager hub test board), the oscilloscope, the digital multimeter and the LPVRTT (Intel puller fixture) constitute a data acquisition area; the host computer communicates with the LPVRTT and the data processing module through a USB cable (Universal Serial Bus, USB cable); the host computer is connected with the digital multimeter and the oscilloscope through a GPIB (General-Purpose Interface Bus) cable; the test board and the LPVRTT are connected through a pin to pin Headto Head joint; the LPVRTT is connected with the oscilloscope through a differential probe; the LPVRTT is connected with the digital multimeter through a DuPont line; the data acquisition area performs initial test and retest during debugging process under the control of the host computer.

[0079] After the test environment is built, the host computer controls the PDU (power distribution unit) to power on the LPVRTT according to the standard power-on sequence, opens the PDX test software, powers on the oscilloscope, digital multimeter, and data processing module in turn, and controls the digital multimeter to measure the Pin pins. After determining that there is no short circuit, the board card to be tested is powered on. After the system is powered on, the host computer collects the voltage readings of the digital multimeter, oscilloscope, and PDX software in the no-load state, determines whether the maximum error exceeds the preset value, and if it is greater than the preset value, corrects the oscilloscope, and if it is not greater than the preset value, enters the test. After the correction is completed, the initial test is started according to the command of the host computer.

[0080] As a specific implementation of the above embodiment, the specific steps of powering on the power supply performance test system according to the power-on logic sequence are as follows:

[0081] The host computer controls the power distribution unit to power on the Intel pull fixture, oscilloscope, digital multimeter, and data processing module in turn.

[0082] At the same time, the host computer controls the digital multimeter to measure the pins of the platform manager hub board card to be tested, and determines whether a short circuit phenomenon occurs based on the measurement result.

[0083] If no short circuit phenomenon occurs, the platform manager hub board card to be tested is powered on.

[0084] As a specific implementation of the above embodiment, before the test, it further includes:

[0085] The host computer collects the voltage readings of the digital multimeter, oscilloscope, and power supply performance test system in the no-load state.

[0086] Based on the voltage readings, the maximum error is calculated, and the maximum error is compared with the first preset value:

[0087] If the maximum error is greater than the first preset value, the collected voltage is corrected by the oscilloscope.

[0088] If the maximum error is less than or equal to the first preset value, the pre-sweeping step is entered.

[0089] As a specific implementation of the above embodiment, the specific steps of the test include:

[0090] Adjusting the load of the power supply performance test system, determining the duty cycle of the sweep based on the adjusted load;

[0091] Based on the duty cycle, pre-sweeping all channels, recording the voltage peak value of each channel at all frequency points, and arranging them in ascending order;

[0092] The arranged frequency points corresponding to the voltage peak-peak value are divided into three sequence data sets according to a preset ratio.

[0093] As a specific implementation of the above embodiment, the specific steps of the test further include: sequentially scanning the duty cycle corresponding to the frequency points in the three sequence data sets from a second preset value to a third preset value at a fixed step size;

[0094] When the target frequency point that does not meet the preset standard is contained in the scanning result, the fixed step size is reduced and the scanning is performed again;

[0095] When the scanning results of the three sequence data sets do not contain the target frequency point, a test result is output, and a test report is formed.

[0096] The specific limitations of the power supply performance test system can be referred to the limitations of the power supply performance test method in the above, which will not be repeated here. Each module in the above power supply performance test system can be realized by software, hardware and combinations thereof, in whole or in part. The above modules can be embedded in or independent of the processor in the computer device in hardware form, or can be stored in the memory in the computer device in software form, so that the processor calls and executes the operations corresponding to each of the above modules.

[0097] Embodiment 3

[0098] In one embodiment, as shown in Figure 6 A power supply performance test device is provided, comprising: a power-on module, a pre-scan frequency module, a judgment module and a test report generation module, wherein:

[0099] The power-on module is configured to power on the power supply performance test system according to a power-on logic sequence;

[0100] The pre-scan frequency module is configured to pre-scan at a fixed duty cycle based on the power-on power supply performance test system, obtain voltage peak-peak values of all frequency points of each channel, and divide the frequency points corresponding to the voltage peak-peak values into three sequence data sets according to a preset ratio;

[0101] The judgment module is configured to perform voltage dynamic tests on the three sequence data sets based on a preset rule, and judge whether the test results meet a preset standard;

[0102] The test report generation module is configured to generate a test report when the test results meet the preset standard.

[0103] As a more preferred embodiment, in the embodiment of the application, the power-on module is specifically configured to:

[0104] The host computer controls the power distribution unit to sequentially power on the Intel load fixture, the oscilloscope, the digital multimeter and the data processing module.

[0105] Meanwhile, the host computer controls the digital multimeter to measure the pins of the platform manager hub to be tested, and judges whether a short circuit phenomenon occurs based on the measurement result.

[0106] If the short circuit phenomenon does not occur, the platform manager hub to be tested is powered on.

[0107] In one embodiment, the device further comprises a pre-processing module, which is specifically used for:

[0108] The host computer collects the voltage readings of the digital multimeter, oscilloscope and power supply performance test system in the no-load state.

[0109] Based on the voltage readings, the maximum error is calculated, and the maximum error is compared with a first preset value:

[0110] If the maximum error is greater than the first preset value, the collected voltage is corrected by the oscilloscope.

[0111] If the maximum error is less than or equal to the first preset value, the pre-sweeping step is entered.

[0112] As a more preferred embodiment, in the embodiment of the present application, the pre-sweeping module is specifically used for:

[0113] Adjusting the load of the power supply performance test system, determining the duty cycle of the sweep based on the adjusted load;

[0114] Pre-sweeping all channels based on the duty cycle, recording the voltage peak-to-peak value of all frequency points of each channel, and arranging them in ascending order;

[0115] According to a preset ratio, the frequency points corresponding to the arranged voltage peak-to-peak values are divided into three sequence data sets.

[0116] As a more preferred embodiment, in the embodiment of the present application, the test report generation module is specifically used for:

[0117] Scanning the duty cycle of the frequency points in the three sequence data sets from a second preset value to a third preset value with a fixed step;

[0118] When the scanning result contains a target frequency point that does not meet the preset standard, the fixed step is reduced and the scanning is performed again;

[0119] When the scanning results of the three sequence data sets do not contain the target frequency point, the test result is outputted, and the test report is formed.

[0120] The specific definition of the power supply performance testing device can refer to the definition of the power supply performance testing method in the foregoing, and will not be described here. Each module in the power supply performance testing device described above can be implemented by software, hardware, or a combination thereof, in whole or in part. The above-mentioned modules can be embedded in or independent of the processor in the computer device in hardware form, or can be stored in the memory in the computer device in software form, so that the processor invokes and executes the operations corresponding to each of the above-mentioned modules.

[0121] Embodiment 4

[0122] In an embodiment, a computer device, which can be a terminal, has an internal structure diagram as shown in Figure 7 The computer device includes a processor, a memory, a network interface, a display screen, and an input system connected by a system bus. The processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for running the operating system and the computer program in the non-volatile storage medium. The network interface of the computer device is configured to communicate with external terminals through a network connection. The computer program is executed by the processor to implement a power supply performance testing method. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen. The input system of the computer device can be a touch layer overlaid on the display screen, or a key, trackball, or touchpad provided on the housing of the computer device, or an external keyboard, touchpad, or mouse, etc.

[0123] Those skilled in the art can understand that Figure 7 The structure shown in the above embodiment is only a block diagram of part of the structure related to the scheme of the present application, and does not constitute a limitation on the computer device to which the scheme of the present application is applied. The specific computer device can include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0124] In an embodiment, a computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor. The processor implements the following steps when executing the computer program:

[0125] S1: powering on the power supply performance testing system according to a power-on logic sequence;

[0126] S2: performing pre-sweeping at a fixed duty cycle based on the powered-on power supply performance testing system, obtaining voltage peak values of all frequency points of each channel, and dividing the frequency points corresponding to the voltage peak values into three sequence data sets according to a preset ratio;

[0127] S3: performing voltage dynamic test on the three sequence data sets respectively based on preset rules, and judging whether the test result meets preset standards;

[0128] S4: if yes, generating a test report.

[0129] In one embodiment, the processor, when executing the computer program, also implements the following steps:

[0130] The host computer is used to control the power distribution unit to sequentially power on the Intel pull tool, the oscilloscope, the digital multimeter and the data processing module;

[0131] Meanwhile, the host computer is used to control the digital multimeter to measure the pins of the platform manager hub to be tested, and judge whether a short circuit phenomenon occurs based on the measurement result;

[0132] If no short circuit phenomenon occurs, the platform manager hub to be tested is powered on.

[0133] In one embodiment, the processor, when executing the computer program, also implements the following steps:

[0134] The host computer is used to collect voltage readings of the digital multimeter, the oscilloscope and the power supply performance test system in an idle state;

[0135] Based on the voltage readings, a maximum error is calculated, and the maximum error is compared with a first preset value:

[0136] If the maximum error is greater than the first preset value, the collected voltage is corrected by the oscilloscope;

[0137] If the maximum error is less than or equal to the first preset value, a pre-sweeping step is entered.

[0138] In one embodiment, the processor, when executing the computer program, also implements the following steps:

[0139] The load of the power supply performance test system is adjusted, and the duty cycle of the sweep is determined based on the adjusted load;

[0140] All channels are pre-swept based on the duty cycle, voltage peak-to-peak values of all frequency points of each channel are recorded, and the voltage peak-to-peak values are arranged in ascending order;

[0141] The frequency points corresponding to the arranged voltage peak-to-peak values are divided into three sequence data sets according to a preset ratio.

[0142] In one embodiment, the processor, when executing the computer program, also implements the following steps:

[0143] The duty cycles of the frequency points in the three sequence data sets are sequentially swept from a second preset value to a third preset value with a fixed step.

[0144] when the scanning result contains a target frequency point that does not meet the preset standard, reducing the fixed step and re-scanning;

[0145] when the scanning result of the three sequence data sets does not contain the target frequency point, outputting a test result and forming a test report.

[0146] Embodiment 5

[0147] In one embodiment, a computer readable storage medium is provided, and a computer program is stored on the computer readable storage medium. The computer program is executed by a processor to implement the following steps:

[0148] S1: powering on the power supply performance test system according to a power-on logic sequence;

[0149] S2: performing pre-sweeping at a fixed duty cycle based on the powered-on power supply performance test system, obtaining voltage peak-to-peak values of all frequency points of each channel, and dividing the frequency points corresponding to the voltage peak-to-peak values into three sequence data sets according to a preset ratio;

[0150] S3: performing voltage dynamic testing on the three sequence data sets respectively based on a preset rule, and judging whether the test result meets a preset standard;

[0151] S4: if yes, generating a test report.

[0152] In one embodiment, the computer program is executed by the processor to further implement the following steps:

[0153] The host computer is used to control the power distribution unit to sequentially power on the Intel pull-up fixture, the oscilloscope, the digital multimeter, and the data processing module;

[0154] Meanwhile, the host computer is used to control the digital multimeter to measure the pins of the platform manager hub to-be-tested board card, and judge whether a short circuit phenomenon occurs based on the measurement result;

[0155] If the short circuit phenomenon does not occur, the platform manager hub to-be-tested board card is powered on.

[0156] In one embodiment, the computer program is executed by the processor to further implement the following steps:

[0157] The host computer is used to collect voltage readings of the digital multimeter, the oscilloscope, and the power supply performance test system in an idle state;

[0158] Based on the voltage readings, a maximum error is calculated, and the maximum error is compared with a first preset value:

[0159] If the maximum error is greater than the first preset value, the collected voltage is corrected by the oscilloscope.

[0160] If the maximum error is less than or equal to the first preset value, a pre-sweeping step is entered.

[0161] In one embodiment, the computer program, when executed by the processor, further implements the following steps:

[0162] Adjusting the load of the power supply performance test system, determining the duty cycle of the sweep based on the adjusted load;

[0163] Pre-sweeping all channels based on the duty cycle, recording the voltage peak-to-peak value of each channel at all frequency points, and arranging them in ascending order;

[0164] According to a predetermined ratio, the frequency points corresponding to the arranged voltage peak-to-peak values are divided into three sequence data sets.

[0165] In one embodiment, the computer program, when executed by the processor, further implements the following steps:

[0166] In a fixed step, the duty cycle of the frequency points corresponding to the three sequence data sets is scanned from the second preset value to the third preset value;

[0167] When the scanning result contains a target frequency point that does not meet the preset standard, the fixed step is reduced and the scanning is performed again;

[0168] When the scanning results of the three sequence data sets do not contain the target frequency point, the test result is output and the test report is formed.

[0169] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer readable storage medium, and when the computer program is executed, the processes of the above-mentioned embodiments of the methods can be included. Any reference to memory, storage, databases, or other media in the embodiments provided by the present application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration but not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0170] The technical features of the above embodiments can be combined in any way. In order to make the description simple, not all possible combinations of the technical features in the above embodiments are described, but as long as the combinations of the technical features do not exist, they should be considered as the scope of the present application.

[0171] The above embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, some modifications and improvements can be made, which are all within the scope of the present application. Therefore, the scope of the patent of the present application should be subject to the appended claims.

Claims

1. A power supply performance test method, characterized by, The method is applied to a power supply performance test system, and the method comprises the following steps: powering on the power supply performance test system according to a power-on logic sequence; performing pre-sweeping on the powered-on power supply performance test system at a fixed duty cycle, obtaining voltage peak-to-peak values of all frequency points of each channel, and dividing the frequency points corresponding to the voltage peak-to-peak values into three sequence data sets according to a preset ratio; performing voltage dynamic tests on the three sequence data sets respectively based on a preset rule, and judging whether a test result meets a preset standard; if yes, generating a test report; before the pre-sweeping, the method further comprises the following steps: collecting voltage readings of a digital multimeter, an oscilloscope and the power supply performance test system in an unloaded state by using a host computer; based on the voltage readings, calculating a maximum error, and comparing the maximum error with a first preset value: if the maximum error is greater than the first preset value, correcting the collected voltage by using the oscilloscope; if the maximum error is less than or equal to the first preset value, entering the pre-sweeping step; the step of performing pre-sweeping at a fixed duty cycle, obtaining voltage peak-to-peak values of all frequency points of each channel, and dividing the voltage peak-to-peak values into three sequence data sets comprises the following steps: adjusting a load of the power supply performance test system, determining a sweep duty cycle based on the adjusted load; performing pre-sweeping on all channels based on the duty cycle, recording voltage peak-to-peak values of all frequency points of each channel, and arranging the voltage peak-to-peak values in ascending order; dividing the frequency points corresponding to the arranged voltage peak-to-peak values into three sequence data sets according to a preset ratio; the step of performing voltage dynamic tests on the three sequence data sets respectively based on a preset rule, and judging whether a test result meets a preset standard comprises the following steps: scanning the duty cycles of the frequency points in the three sequence data sets from a second preset value to a third preset value with a fixed step length; when the scanning result contains a target frequency point that does not meet the preset standard, reducing the fixed step length and performing scanning again; when the scanning results of the three sequence data sets do not contain the target frequency point, outputting a test result and forming a test report.

2. The power supply performance test method of claim 1, wherein the step of powering on the power supply performance test system according to a power-on logic sequence comprises the following steps: controlling a power distribution unit by using a host computer to power on an Intel load fixture, an oscilloscope, a digital multimeter and a data processing module in sequence; at the same time, controlling the digital multimeter by using the host computer to measure pins of a platform manager hub to-be-tested board, and judging whether a short circuit phenomenon occurs based on a measurement result; if the short circuit phenomenon does not occur, powering on the platform manager hub to-be-tested board.

3. A power supply performance test system for implementing the power supply performance test method according to claim 1, characterized by the system comprises: a power distribution unit, which is connected with a data acquisition module and a data processing module through a power line; a host computer, which is connected with the power distribution unit based on an Internet Protocol, and is connected with the data processing module through a Universal Serial Bus cable, and is used for powering on the data processing module according to a power-on logic sequence; the host computer is connected with the data acquisition module through a General Purpose Interface Bus cable, and is used for controlling a data acquisition process of the data acquisition module, and powering on the data acquisition module according to the power-on logic sequence. The data processing module is connected with the data acquisition module through a universal serial bus cable, and is used for voltage dynamic testing on the system to be tested.

4. The power supply performance test system of claim 3, wherein, The data acquisition module comprises a platform manager hub test board, an oscilloscope, a digital multimeter and an Intel puller fixture. The platform manager hub test board is connected with the Intel puller fixture through a pin joint. The Intel puller fixture is connected with the oscilloscope through a differential probe. The Intel puller fixture is connected with the digital multimeter through a DuPont wire.

5. A power supply performance test apparatus for implementing the power supply performance test method according to claim 1, characterized by, The device comprises: A power-on module, configured to power on a power supply performance test system according to a power-on logic sequence; A pre-sweeping module, configured to pre-sweep, based on the power supply performance test system after being powered on, at a fixed duty cycle, to obtain voltage peak-to-peak values of all frequency points of each channel, and divide frequency points corresponding to the voltage peak-to-peak values into three sequence data sets according to a preset ratio; A judgment module, configured to perform voltage dynamic testing on the three sequence data sets respectively based on a preset rule, and judge whether a test result meets a preset standard; A test report generation module, configured to generate a test report when the test result meets the preset standard.

6. A computer device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor executes the computer program to implement the steps of the method in claim 1 or 2.

7. A computer readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the method in claim 1 or 2.

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