Display panel and display device including the same

Abstract

The present application provides a display panel and a display device including the same. In the display panel, a panel defect caused by static electricity induced by an MPS line remaining on the panel after a cutting process in a cell array process of a display device is eliminated, the remaining MPS line is electrically connected to an ESD circuit through a discharge line, and thus static electricity induced by the MPS line remaining on the panel flows to the ESD circuit through the discharge line, thereby suppressing a panel defect caused by the MPS line.

Description

TECHNICAL FIELD

[0001] The disclosure relates to a display panel and a display device including the same, in which a panel defect caused by static electricity induced by a multi-pattern search (MPS) line remaining on the display panel after a cutting process of a mother glass in a manufacturing process of the display device can be eliminated. BACKGROUND

[0002] A typical liquid crystal display device displays an image by controlling the light transmittance of liquid crystal having dielectric anisotropy using an electric field. To this end, the liquid crystal display device includes a liquid crystal display panel in which pixel areas are arranged in a matrix form and a driving circuit for driving the liquid crystal display panel.

[0003] In the liquid crystal display panel, a first substrate and a second substrate are bonded to each other while maintaining a certain space therebetween, and a liquid crystal layer is formed between the space maintained by the two substrates. In order to drive the liquid crystal layer in units of pixels, a plurality of gate lines and a plurality of data lines are provided on the first substrate and cross each other to define pixel areas at intersections therebetween. A pixel electrode is formed in each pixel area, and a thin film transistor is formed at a region where each gate line and each data line cross each other. The thin film transistor is turned on based on a scan signal of each gate line, thereby applying a data signal of the data line to each pixel electrode. Thereby, a thin film transistor array substrate is obtained.

[0004] In addition, on the second substrate, a black matrix layer for blocking light in a region other than the pixel areas, a color filter layer formed in each pixel area to exhibit a color, and a common electrode corresponding to the pixel electrode and generating an electric field for driving the liquid crystal layer are provided. Thereby, a color filter array substrate is obtained.

[0005] The driving circuit includes a gate driver for driving the gate lines, a data driver for driving the data lines, and a timing controller for supplying control signals and data signals used to control the gate driver and the data driver.

[0006] The gate driver has a shift register that sequentially outputs scan pulses to the gate lines. The shift register is constituted by a plurality of stages that are connected to each other in a dependent manner. The plurality of stages sequentially output the scan pulses to sequentially scan the gate lines of the liquid crystal panel. Specifically, a first stage of the plurality of stages receives a start signal from the timing controller as a trigger signal, and the remaining stages other than the first stage receive an output signal from a previous stage as a trigger signal. Further, each of the plurality of stages receives at least one clock pulse from a plurality of clock pulses having sequential phase differences. Accordingly, the first stage to the last stage sequentially output the scan pulses.

[0007] Regarding the use of the gate driver, a separate gate driver integrated circuit (IC) in which a shift register of the gate driver is embedded is manufactured, and then the gate driver IC is connected to a gate line pad of a liquid crystal display panel using a mounting process.

[0008] The above-mentioned liquid crystal display device can generally be manufactured using a cell array process, a bonding process, a module process, and the like.

[0009] The cell array process defines multiple panel areas on the first mother substrate and forms a thin film transistor array with gate lines, data lines, thin film transistors, and pixel electrodes in each panel area. The cell array process defines multiple panel areas on the second mother substrate and forms a color filter array with a black matrix layer, color filter layer, and common electrode in each panel area.

[0010] The bonding process forms a sealant on the edge portion of each panel area of ​​the first mother substrate or the second mother substrate and drips liquid crystal, aligns the two mother substrates with each other and bonds the substrates to each other, cuts the attached substrates based on the panel area, and performs automatic probe inspection.

[0011] The module process refers to the process of attaching the driver IC to the unit panel and coupling the backlight thereto.

[0012] After the cell array process is completed as described above, and before the bonding process, each signal line is checked for disconnection and short-circuit defects by an MPS (Multi-Pattern Search) line. When a defect is detected, a repair process may be additionally performed.

[0013] As described above, for the MPS inspection for inspecting disconnection and short defects of each signal line of a thin film transistor array, MPS lines for inspecting defects are formed during a cell array process and are removed during a cutting process.

[0014] In this regard, in the cell array manufacturing process for the 23.8-inch panel model, the spacing between panel areas on the mother substrate defining multiple panel areas is very small compared to other panel models. The MPS line for inspecting disconnection and short-circuit defects of each signal line can be formed in the spacing.

[0015] During the bonding process, in order to maximize the efficiency of the panel glass, a panel-to-panel just-cut is performed that cuts the line between two panel areas adjacent to each other in the vertical direction. After the just-cut, the MPS line remains on the top surface of each panel.

[0016] In this regard, when static electricity is generated on the panel after tangent, the remaining MPS lines induce static electricity, and the induced static electricity floats in the MPS lines and is applied to the common voltage (Vcom) line.

[0017] At this time, the Vcom line is connected to the pixel, so the applied static electricity is applied to the pixel, causing voltage distortion scanning, which causes temporary coloring on the screen.

[0018] The above information disclosed in this Background section is only for enhancement of understanding of the background of the described technology and therefore it may contain information that does not form the prior art that is already known to a person of ordinary skill in the art. Summary of the Invention

[0019] Accordingly, the present disclosure is directed to a display panel and a display device including the same that substantially obviate one or more problems due to the above limitations and disadvantages.

[0020] More particularly, the present disclosure is directed to providing a display panel and a display device including the same, in which pixel defects caused by static electricity induced by MPS lines remaining on the display panel after a cutting process of a mother glass during the manufacturing process of the display device are removed.

[0021] The present disclosure is not limited to the above, and other advantages of the present disclosure that are not mentioned can be understood based on the following description and can be more clearly understood based on the aspects of the present disclosure. In addition, it is easy to understand that the purposes and advantages of the present disclosure can be achieved using the means shown in the claims and their combinations.

[0022] In one aspect of the present disclosure, a display panel may be a panel obtained by tangenting a mother panel (mother glass) having a plurality of panel regions arranged adjacent to each other during a scribing process, the display panel including: a base substrate including a display region and a non-display region; and an electrostatic discharge portion including an MPS (multi-mode search) region disposed in an upper region of the non-display region, wherein at least one MPS line is disposed in the MPS region; an ESD region provided with at least one ESD (electrostatic discharge) circuit, wherein the ESD circuit discharges static electricity generated in the display region and the non-display region; and at least one discharge line for connecting the at least one MPS line to the at least one ESD circuit, respectively. Thus, the display panel may allow static electricity generated in the non-display region to flow from the MPS line to the ESD circuit via the discharge line.

[0023] In addition, a display device according to one aspect of the present disclosure can be provided. The display panel can be a panel obtained by tangenting a mother panel (mother glass) having multiple panel areas arranged adjacent to each other during a scribing process, the display panel comprising: a base substrate including a display area and a non-display area arranged outside the display area, wherein in the display area, a pixel is defined at each of the intersections of multiple gate lines and multiple data lines; a GIP (gate in panel) for supplying scan signals to the multiple gate lines; a data driver for supplying data signals to the multiple data lines; and an electrostatic discharge unit. The electrostatic discharge unit comprises: an MPS (multi-mode search) area overlapping an upper area of ​​the non-display area, wherein at least one MPS line is provided in the MPS area; an ESD area provided with at least one ESD (electrostatic discharge) circuit, wherein the ESD circuit discharges static electricity generated in the display area and the non-display area; a grounding area between the MPS area and the ESD area, wherein a grounding electrode is provided in the grounding area; and at least one discharge line for connecting at least one MPS line to the at least one ESD circuit, respectively. Therefore, static electricity generated in the non-display area can flow from the MPS line to the ESD circuit through the discharge line, thereby preventing temporary coloring from occurring on the screen.

[0024] According to one aspect of the present disclosure, since the MPS lines remaining on the display panel are respectively connected to the ESD circuit through the discharge lines, static electricity generated in the non-display area and flowing into the MPS lines can flow into the ESD circuit via the discharge lines, thereby preventing voltage distortion caused by the MPS lines.

[0025] Furthermore, according to the present disclosure, since there is no need to attach a conductive tape to the panel to remove ESD defects caused by the MPS line, the quality of the display panel can be improved.

[0026] Furthermore, according to the present disclosure, even when static electricity flows into the display panel due to the MPS line remaining on the display panel, it is possible to prevent stains from occurring on the screen, thereby improving the quality of the display panel.

[0027] The effects of the present disclosure are not limited to the above-mentioned effects, and another effect that is not mentioned will be clearly understood by those skilled in the art through the following description.

[0028] In addition to the above-described effects, specific effects of the present disclosure will be described together with description of specific embodiments for carrying out the following disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this disclosure, illustrating aspects of the disclosure and together with the description serve to explain the principles of the disclosure.

[0030] In the attached figure:

[0031] Figure 1 A mother glass for manufacturing a display panel according to one aspect of the present disclosure is shown;

[0032] Figure 2 It shows Figure 1 A diagram of the detailed structure of each panel area;

[0033] Figure 3 is shown for the Figure 1 A diagram of a scribing line for cutting between two adjacent panel areas;

[0034] Figure 4 is shown by following Figure 3 An example diagram of a display panel obtained by taking a tangent line between two adjacent panel regions;

[0035] Figure 5 shows a configuration of an electrostatic discharge portion in a display panel according to one aspect of the present disclosure;

[0036] Figure 6A is a diagram illustrating a connection area MPS between one discharge line and one MPS line in the MPS area of ​​an electrostatic discharge portion according to one aspect of the present disclosure;

[0037] Figure 6B is a diagram showing a plan view of a connection region MPS in the MPS region of an electrostatic discharge portion according to one aspect of the present disclosure;

[0038] Figure 6C is a diagram showing a cross-sectional view cut along line AA′ of a connection region MPS in the MPS region of an electrostatic discharge portion according to one aspect of the present disclosure;

[0039] Figure 7A is a diagram illustrating a discharge line in a grounding region of an electrostatic discharge portion according to one aspect of the present disclosure;

[0040] Figure 7B is a diagram showing a cross-sectional view taken along line BB′ of a grounding region of an electrostatic discharge portion according to one aspect of the present disclosure;

[0041] Figure 8A is a diagram illustrating a discharge ESD circuit ESD in an ESD region of an electrostatic discharge unit according to one aspect of the present disclosure;

[0042] Figure 8B is a diagram showing a circuit configuration example of a discharge ESD circuit ESD in an ESD region of an electrostatic discharge portion according to one aspect of the present disclosure;

[0043] Figure 9 is a diagram showing a line structure of one pixel in a display area according to one aspect of the present disclosure; and

[0044] Figure 10 It is along Figure 9 A cross-sectional view taken along line DD' in the line structure of FIG. DETAILED DESCRIPTION

[0045] The advantages and features of the present disclosure, as well as methods for achieving these advantages and features, will become apparent with reference to the aspects described in detail later in conjunction with the accompanying drawings. However, the present disclosure is not limited to the aspects disclosed below, but may be implemented in a variety of different forms. Therefore, these aspects are set forth only to complete the present disclosure and to fully inform those skilled in the art of the present disclosure of its scope, and the present disclosure is limited only by the scope of the claims.

[0046] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for describing aspects of the present disclosure are illustrative, and the present disclosure is not limited thereto. The same reference numerals refer to the same elements herein. In addition, for simplicity of description, descriptions and details of known steps and elements are omitted. In addition, in the following detailed description of the present disclosure, many specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it should be understood that the present disclosure can be practiced without these specific details. In other cases, known methods, procedures, components and circuits are not described in detail to avoid unnecessary confusion of aspects of the present disclosure.

[0047] The terms used herein are only intended to describe the purpose of specific aspects and are not intended to limit the present disclosure. As used herein, the singular constructions "one" and "an" are intended to also include plural constructions, unless the context clearly indicates otherwise. It will also be understood that, when used in this specification, the terms "comprise," "comprising," "include," and "including" specify the presence of the features, integers, operations, elements, and / or parts, but do not exclude the presence or addition of one or more other features, integers, operations, elements, parts, and / or parts thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the items listed herein. Expressions such as "at least one" can modify the entire list of elements when preceding the list of elements, and may not modify the individual elements of the list. In the interpretation of numerical values, even without clear description, errors or tolerances therein may also occur.

[0048] Furthermore, it should be understood that when a first element or layer is referred to as being "on" a second element or layer, the first element may be disposed directly on the second element or may be disposed indirectly on the second element, with a third element or layer disposed between the first element or layer and the second element or layer. It should be understood that when an element or layer is referred to as being "connected to" or "coupled to" another element or layer, it may be directly on the other element or layer, connected to or coupled to the other element or layer, or one or more intervening elements or layers may be present. It should be understood that when an element or layer is referred to as being "between" two elements or layers, it may be the only element or layer between the two elements or layers, or one or more intervening elements or layers may be present.

[0049] Furthermore, as used herein, when a layer, film, region, plate, etc. is disposed “on” or “on top of” another layer, film, region, plate, etc., the former may be in direct contact with the latter, or another layer, film, region, plate, etc. may be disposed between the former and the latter. As used herein, when a layer, film, region, plate, etc. is disposed directly “on” or “on top of” another layer, film, region, plate, etc., the former is in direct contact with the latter, and no other layer, film, region, plate, etc. is disposed between the former and the latter. Furthermore, as used herein, when a layer, film, region, plate, etc. is disposed “below” or “beneath” another layer, film, region, plate, etc., the former may be in direct contact with the latter, or another layer, film, region, plate, etc. may be disposed between the former and the latter. As used herein, when a layer, film, region, plate, etc. is disposed directly “below” or “beneath” another layer, film, region, plate, etc., the former is in direct contact with the latter, and no other layer, film, region, plate, etc. is disposed between the former and the latter.

[0050] It should be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Thus, a first element, component, region, layer, or portion described below may be referred to as a second element, component, region, layer, or portion without departing from the spirit and scope of the present disclosure.

[0051] When interpreting numerical values, unless otherwise expressly stated, the values ​​are interpreted as including the error range.

[0052] It should be understood that when an element or layer is referred to as being “connected to” or “coupled to” another element or layer, it can be directly on, connected to, or coupled to the other element or layer, or one or more intervening elements or layers may be present. Additionally, it should be understood that when an element or layer is referred to as being “between” two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may be present.

[0053] The features of each aspect of the present disclosure may be combined with each other in part or in whole, and may be technically related to each other or operate with each other. These aspects may be implemented independently of each other or may be implemented together in a related relationship.

[0054] In the description of a temporal relationship, such as "after", "subsequently", "before", etc., a temporal precedence relationship between two events, unless "directly after", "directly subsequent", or "directly before" is not indicated, another event may occur between them.

[0055] Unless otherwise defined, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention pertains. It will also be understood that terms (e.g., terms defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0056] Hereinafter, a display panel and a display device including the same according to some aspects of the present disclosure will be described.

[0057] Figure 1 A mother glass for manufacturing a display panel according to one aspect of the present disclosure is shown. Figure 2 It shows Figure 1 A diagram showing the detailed structure of each panel area. Figure 3 is shown for the Figure 1 Figure 1 shows a scribe line used to cut between two adjacent panel areas. Figure 4 is shown by following Figure 3 Figure 1 shows an example of a display panel obtained by tangentiating a ruled line between two adjacent panel areas.

[0058] Reference Figures 1 to 4 , a mother glass for manufacturing a display panel according to one aspect of the present disclosure may be implemented as, for example, a mother panel 10 in which a plurality of panel regions 11 , 12 , and 13 are arranged and spaced apart from each other.

[0059] The mother panel 10 according to one aspect of the present disclosure may be configured such that one panel area has a size of 23.8 inches. Therefore, 32 panel areas may be arranged in the mother panel 10. 32 panel areas may be defined in the mother panel 10. However, the present disclosure is not limited thereto. The number of panel areas defined in the mother panel 10 may vary depending on the size of each panel area. Figure 1 As shown, in the mother panel 10 , for example, four panel regions may be defined in the transverse direction (ie, the X-axis direction), and eight panel regions may be defined in the longitudinal direction (ie, the Y-axis direction).

[0060] In the mother panel 10, a space may be defined between adjacent panels in the lateral direction (X-axis direction). Each of the plurality of MPS pads 22 for MPS inspection may be provided in the space between two panel regions that are spaced apart from each other and adjacent to each other in the lateral direction (X-axis direction).

[0061] The mother panel 10 may include a first panel region 11 , a second panel region 12 , and a third panel region 13 adjacent to each other in a longitudinal direction (Y-axis direction).

[0062] In the mother panel 10, the panel areas may be arranged in a lateral direction (X-axis direction) and adjacent to each other, or may be arranged in a longitudinal direction (Y-axis direction) and adjacent to each other. An MPS line 20 may be provided in each panel area, and the MPS line 20 may be connected to each MPS pad 22 provided in the space between the panel areas.

[0063] Scribe lines may be formed on mother panel 10. The scribe lines may be used to cut and separate first panel region 11 and second panel region 12 from each other.

[0064] In one aspect of the present disclosure, in order to obtain a panel, for example, a scribing process of irradiating a laser to a scribing line and irradiating along the scribing line and tangentially along the scribing line may be performed.

[0065] Therefore, after the scribing process, a first panel 11 corresponding to the first panel region 11 and a second panel 12 corresponding to the second panel region 12 may be obtained. Each MPS line 20 may remain on each of the cut panels 11 and 12.

[0066] In one aspect of the present invention, the first panel region 11 can be referred to as one of the first array substrate 11, the first display panel 11 and the first panel 11, and the second panel region 12 can be referred to as one of the second array substrate 12, the second display panel 12 and the second panel 12.

[0067] The first panel 11 and the second panel 12 may be obtained by cutting the mother panel 10 during a scribing process.

[0068] As described above, the efficiency of the glass can be improved by obtaining multiple panels from the mother panel 10. For example, in a 23.8-inch model, 32 panels can be obtained from the mother panel 10.

[0069] During the scribing process, tangent can be performed without spacing between panel areas to improve the efficiency of the glass and obtain the maximum number of UPS (units per sheet). In order to produce as many panels as possible from the mother panel 10, there may be no spacing between panel areas in the longitudinal direction (Y-axis direction). Therefore, tangent can be performed during the scribing process. Figure 1 and Figure 2 , the panels 11 , 12 , and 13 may be arranged in the mother panel 10 such that adjacent panel areas share at least one side with each other.

[0070] MPS lines 20 for inspecting disconnection and short defects of each signal line are formed between first and second panel regions 11 and 12 adjacent to each other in a longitudinal direction (Y-axis direction) of mother panel 10. MPS lines 20 are connected to each MPS pad 22.

[0071] The MPS line 20 extends from the MPS pad 22 outside the second panel area 12 along the longitudinal direction (Y-axis direction), then bends toward the lateral direction (X-axis direction) perpendicular to the longitudinal direction, then extends into the second panel area 12, then bends toward the longitudinal direction (Y-axis direction), and then extends into the first panel area 11.

[0072] Then, the MPS line 20 bends in the lateral direction (X-axis direction) and then extends in the lateral direction (X-axis direction) within the first panel region 11. Figure 2 , in the upper area of ​​the first panel area 11 , the MPS line 20 may be bent in the transverse direction (X-axis direction) and then extend to the right end in the transverse direction (X-axis direction).

[0073] Hereinafter, one aspect of the present disclosure will be described on the first panel 11 , in which static electricity is induced due to the MPS line 20 .

[0074] like Figure 2 As shown, the first panel 11 may include a first GIP (Gate In Panel) 111, a first non-pad area (eXception PAD) (hereinafter referred to as XPD) 112, a first display area (active area) (hereinafter referred to as A / A) 113, a first data driver (hereinafter referred to as D-dr) 114 and a first line (Line on Glass) (hereinafter referred to as LoG 115).

[0075] In the display panel, a GIP, a non-pad area XPD, a data driver D-dr, and a line LoG may be disposed on a base substrate including a display area A / A and a non-display area N / A.

[0076] The first GIP 111 can apply scan signals to the gate lines of the first display area 113. For example, the first GIP 111 can sequentially apply gate voltages to the pixels on a horizontal line basis in response to receiving a gate control signal GCS from a timing controller T-con. The first GIP 111 can be implemented as a shift register having multiple stages that sequentially output high-level gate voltages during each first horizontal period. The timing controller T-con can control the first GIP 111 and the first data driver 114. For example, the timing controller T-con receives an image signal, a clock signal, and timing signals (e.g., a vertical synchronization signal and a horizontal synchronization signal) applied from an external device, and generates a gate control signal GCS and a data control signal DCS based on the received signals, and supplies the generated control signals to the first GIP 111 and the first data driver 114. In this regard, the horizontal synchronization signal indicates the time it takes to display one line of the screen, and the vertical synchronization signal indicates the time it takes to display one frame of the screen. In addition, control signals for the gate driver and each driver can be generated based on the clock signal. In addition, the timing controller T-con can be connected to an external system through a predetermined interface and can receive image-related signals and timing signals output from the external system at high speed without noise. The interface may include an interface operating in an LVDS (low voltage differential signal) scheme or a TTL (transistor-transistor logic) interface scheme.

[0077] In the first non-pad area 112 , a plurality of lines, such as a ground line, a common voltage line Vcom Line, and an ESD (ElectroStatic Discharge) circuit, may be disposed.

[0078] In the first display area 113, a plurality of gate lines can extend in a lateral direction, a plurality of data lines can extend in a longitudinal direction, and each of the sub-pixels can be disposed at each of the intersections between the plurality of gate lines and the plurality of data lines.

[0079] The first data driver 114 can apply a data signal to the plurality of data lines. The first data driver 114 can be attached to a data pad in the form of, for example, a driver chip (or driver-IC).

[0080] The first lines 115 can include a first-first line 115 disposed left of the data driver 114 and a first-second line 115 disposed right of the data driver 114.

[0081] The first lines 115 can be directed toward the first GIP 111. During the TFT inspection, the first lines 115 can transmit an MPS signal to the first GIP 111. Furthermore, the first lines 115 can include lines connecting the MPS pad 22 and the first GIP 111 to each other. In this case, the first lines 115 can transmit the MPS signal from the MPS pad 22 to the first GIP 111.

[0082] Some of the MPS lines 20 can be connected to the first-first line 115, while others of them can be connected to the first data driver 114, and yet others of them can be connected to the first-second line 115. One of the MPS lines connected to the first data driver 114 can be used to transmit a data signal, while another MPS line can be used to transmit a touch signal. The MPS lines 20 connected to the first-first line 115 and the first-second line 115 are shown as single lines in Figure 2 However, the number of the MPS lines 20 connected to the first-first line 115 and the first-second line 115 can be multiple. Two or more lines can be connected to the first data driver 114.

[0083] In the same manner as the first panel 11, the second panel 12 can include a second GIP 121, a second non-pad area 122, a second display area 123, a second data driver 124, and a second line 125.

[0084] Furthermore, in the same manner as the first panel 11, the third panel 13 can include a third GIP 131, a third non-pad area 132, a third display area 133, a third data driver 134, and a third line 135.

[0085] Each of the second GIP 121 and the third GIP 131 can have the same structure and the same function as the first GIP 111.

[0086] Each of the second non-pad region 122 and the third non-pad region 132 may have the same structure and the same function as the first non-pad region 112 .

[0087] Each of the second display area 123 and the third display area 133 may have the same structure and the same function as the first display area 113 .

[0088] Each of the second data driver 124 and the third data driver 134 may have the same structure and the same function as the first data driver 114 .

[0089] Each of the second and third lines 125 and 135 may have the same structure and the same function as the first line 115 .

[0090] Each of the first line 115, the second line 125, and the third line 135 may include a plurality of lines, such as a ground line GND, clock signal lines CLK1 to CLK8, a reset line RESET, and a common voltage line Vcom. Furthermore, in addition to the aforementioned lines, each of the first line 115, the second line 125, and the third line 135 may further include a start voltage line Vst, gate low voltage related lines VGL_UD and VGL2, gate high voltage related lines VGH_O, VGH_E, and VGH, and the like.

[0091] like Figure 3 As shown, in one aspect of the present disclosure, a scribing process can be performed in which a laser is irradiated on a scribing line at a boundary between the first panel region 11 and the second panel region 12, and a laser is irradiated along a scribing line at a boundary between the first panel region 11 and the second panel region 12, and the scribing process is tangent to the first panel region 11 and the second panel region 12.

[0092] Therefore, after the scribing process, the first panel 11 and the second panel 12 may be obtained in a separate manner, and the MPS line 20 cut as described above may remain on each of the panels 11 and 12 .

[0093] like Figure 4 As shown, the first panel 11 according to one aspect of the present disclosure may include an electrostatic discharge portion 100 for discharging static electricity induced by the MPS lines 20 remaining after the scribing process.

[0094] The electrostatic discharge part 100 may have a structure in which the MPS line 20 and the ESD circuit are respectively connected to each other through the discharge line 140 .

[0095] The first panel 11 according to one aspect of the present disclosure can be cut from the mother panel 10 along the scribing line during the scribing process and can be one of the two panels 11 and 12 arranged in the vertical direction. For example, after cutting, the first panel area 11 below the scribing line becomes the first panel 11, and the second panel area 12 above the scribing line becomes the second panel 12.

[0096] Therefore, the MPS line 20 remains in the upper region of the first panel 11 and the lower region of the second panel 12. In the upper region of each of the first panel 11 and the second panel 12, the MPS line 20 extends from the upper end in the longitudinal direction (Y-axis direction), bends in the transverse direction (X-axis direction), and then extends in the transverse direction to the right end. In the lower region of each of the first panel 11 and the second panel 12, the MPS line 20 extends from the left end in the transverse direction (X-axis direction), bends in the longitudinal direction (Y-axis direction), and extends in the longitudinal direction to the lower end.

[0097] In the first panel 11, when static electricity is generated in the non-display area, the remaining MPS lines 20 induce static electricity and can be applied to the common voltage Vcom line through the ground line, causing voltage distortion. However, in the first panel 11 according to one aspect of the present disclosure, the static electricity induced by the MPS lines 20 can flow to the ESD circuit through the electrostatic discharge unit 100, thereby preventing voltage distortion. In one aspect of the present disclosure, during the tangent process, the first and second panels 11 and 12 share a side in the longitudinal direction (Y-axis direction), so the MPS lines 20 remain in each of the first and second panels 11 and 12. Therefore, the MPS lines 20 remaining in the first panel 11 can be connected to the ESD circuit of the first panel 11 via the discharge line 140, thereby preventing static electricity from being applied to the common voltage Vcom line through the MPS lines 20.

[0098] In a model where the panel area is not arranged in a manner that applies tangent but is arranged in a manner that the panel area is generally arranged, the MPS line does not remain on the separated panels arranged in the vertical direction when cutting along the scribe line. Dummy pixels may remain on the upper panel, or keys and blank spaces for different purposes may remain on it. GIP, non-pad area, display area, etc. may remain on the lower panel. The functions of GIP, non-pad area, and display area are the same as those of the above-mentioned GIP, non-pad area, and display area.

[0099] However, the first and second panels 11 and 12 according to one aspect of the present disclosure may be arranged in a tangent-applying manner to obtain as many panels as possible from the mother panel 10. Therefore, after the scribing process, the MPS line 20 remains on each of the first and second panels 11 and 12.

[0100] Therefore, when static electricity is generated in the non-display area of the first panel 11, static electricity is induced due to the MPS line 20 remaining on the first panel 11. Therefore, a structure for preventing static electricity from affecting the display area A / A is required. Therefore, the MPS line 20 remaining on the first panel 11 can be connected to the ESD circuit through the discharge line 140, thereby eliminating the static electricity problem.

[0101] Figure 5 A configuration of an electrostatic discharge portion in a display panel according to one aspect of the disclosure is illustrated. Figure 5 The electrostatic discharge portion 100 in Figure 4 is illustrated in more detail.

[0102] Referring to Figure 5 , the electrostatic discharge portion 100 according to one aspect of the disclosure can include an MPS region 110, a grounding region 120, an ESD region 130, and a discharge line 140 on a base substrate 102.

[0103] In this regard, the base substrate 102 can include a display area A / A and a non-display area N / A.

[0104] The MPS region 110 can be disposed in an upper region of the non-display area N / A. Further, at least the MPS line 20 can be disposed in the MPS region 110.

[0105] The ESD region 130 can be disposed between the MPS region 110 and the display area (A / A) 113. Further, the ESD region 130 includes an ESD (Electrostatic Discharge) circuit. Two or more ESD (Electrostatic Discharge) circuits in the ESD region can discharge static electricity generated in the display area A / A and the non-display area N / A.

[0106] The discharge line 140 can connect the MPS line 20 and the ESD circuit to each other, respectively.

[0107] The discharge line 140 can be made of the same material as that of the pixel electrode Pixel. For example, the discharge line 140 can be made of indium tin oxide (ITO).

[0108] The grounding region 120 can be disposed between the MPS region 110 and the ESD region 130. Further, a grounding electrode 122 can be disposed in the grounding region 120.

[0109] The ESD circuit can include at least one pixel ESD circuit 136 and at least one discharge ESD circuit 137.

[0110] The ESD region 130 may include at least one pixel ESD circuit 136 , at least one discharge ESD circuit 137 , and at least one redundant ESD circuit 138 .

[0111] Each of the at least one pixel ESD circuit 136 may have one end connected to each pixel of the display area 113 and the other end connected to the ground electrode 122. Therefore, the pixel ESD circuit 136 may discharge static electricity generated or induced in the display area 113 to the ground electrode 122.

[0112] Each of the at least one discharge ESD circuits 137 may have one end connected to each of the discharge lines 140 and the other end connected to the ground electrode 122. Thus, the discharge ESD circuits 137 may discharge static electricity introduced from the MPS line 20 through the discharge line 140 to the ground electrode 122.

[0113] At least the redundant ESD circuit 138 can be used to maintain a constant spacing between ESD circuits or can be used redundantly. In addition, the redundant ESD circuit 138 can be connected to the discharge line 140 or each pixel of the display area 113 when necessary.

[0114] At least one discharge ESD circuit 137 may be connected to the ground electrode 122 through a ground connection line 137 a .

[0115] A common voltage line Vcom may be provided between the ESD region 130 and the display region 113. The common voltage line Vcom extends horizontally and may be connected to each pixel of the display region 113 at each of the top and bottom of the display region 113. In this case, the common voltage line Vcom may be implemented as a gate line Gate.

[0116] Figure 6A FIG. 1 is a diagram illustrating a connection area MPS between one discharge line and one MPS line in an MPS area of ​​an electrostatic discharge portion according to an aspect of the present disclosure. Figure 6B is a diagram illustrating a plan view of a connection region MPS in the MPS region of an electrostatic discharge part according to one aspect of the present disclosure. Figure 6C is a diagram illustrating a cross-sectional view cut along line AA′ of a connection region MPS in an MPS region of an electrostatic discharge part according to one aspect of the present disclosure.

[0117] Reference Figures 6A to 6C In the connection region MPS in the MPS region 110 of the electrostatic discharge unit 100 according to one aspect of the present disclosure, one MPS line 20 extending in the transverse direction and one discharge line 140 extending in the longitudinal direction are connected to each other.

[0118] In the connection region MPS in the MPS region 110, one MPS line 20 is electrically connected to one discharge line 140 via the first contact hole 112. Figure 6B shown.

[0119] In the MPS region 110 , at least one discharge line 140 may be connected to at least the MPS line 20 via the first contact holes 112 , respectively.

[0120] The MPS line 20 may be made of the same material as the plurality of gate lines and may be formed in the same process as the gate lines on the base substrate 102. The plurality of gate lines may be made of the same material as the gate metal Gate.

[0121] At least the MPS line 20 in the MPS region 110 may be made of the same material as the gate metal Gate and may be formed on the base substrate 102 .

[0122] like Figure 6C As shown, in the connection region MPS of the MPS region 110, the MPS line 20 on the base substrate 102 can be made of the same material as the gate metal Gate. Furthermore, in the connection region MPS, the gate insulating layer 106 can be formed on the MPS line 20 made of the same material as the gate metal Gate, and the planarization layer PLN can be formed on the gate insulating layer 106. Furthermore, in the connection region MPS, a first via 112 extends through the planarization layer PLN and the gate insulating layer 106. A discharge line 140 can be formed on the planarization layer PLN. Furthermore, in the connection region MPS, the discharge line 140 can extend through the first via 112 and can be connected to the MPS line 20 made of the same material as the gate metal Gate.

[0123] Figure 7A is a diagram illustrating a discharge line in a grounding region of an electrostatic discharge portion according to one aspect of the present disclosure. Figure 7B is a diagram illustrating a cross-sectional view taken along line BB′ in a ground region of an electrostatic discharge portion according to one aspect of the present disclosure.

[0124] Reference Figure 7A In the electrostatic discharge unit 100 according to one aspect of the present disclosure, in the ground region 120 , at least one discharge line 140 may extend in the longitudinal direction while overlapping the ground electrode 122 extending in the transverse direction.

[0125] In this case, the ground electrode 122 and the at least one discharge line 140 may overlap each other while being electrically insulated from each other by the insulating layer. The insulating layer may be implemented as a planarization layer PLN.

[0126] Reference Figure 7BIn the electrostatic discharge unit 100 according to one aspect of the present disclosure, in the ground region 120, a ground electrode 122 made of the same material as the gate metal Gate may be provided on the base substrate 102. The gate insulating layer 106 may be formed on the ground electrode 122 made of the same material as the gate metal Gate. In addition, in the ground region 120, a planarization layer PLN may be formed on the gate insulating layer 106, and at least one discharge line 140 may be formed on the planarization layer PLN.

[0127] Figure 8A FIG. 1 is a diagram illustrating a discharge ESD circuit ESD in an ESD region of an electrostatic discharge unit according to an aspect of the present disclosure. Figure 8B : is a diagram showing a circuit configuration example of one discharge ESD circuit ESD in an ESD region of an electrostatic discharge unit according to one aspect of the present disclosure.

[0128] Reference Figure 8A , the ESD region 130 according to one aspect of the present disclosure may include at least one pixel ESD circuit 136 and at least one discharge ESD circuit 137 .

[0129] At least the discharging ESD circuits 137 may be connected to at least one discharging line 140 , respectively.

[0130] The MPS line 20 can be made of the same material as the gate metal gate and can be formed using the same process as the gate metal gate. The discharge line 140 can be made of the same material as the pixel electrode formed in the display area 113. The discharge line 140 can be made of a transparent conductive material. The discharge line 140 can be made of a combination of metal and oxide, or a metal oxide.

[0131] One end of one discharging ESD circuit 137 may be connected to the discharging line 140 , and the other end thereof may be connected to the ground electrode 122 through a ground connection line 137 a .

[0132] Reference Figure 8B , one discharge ESD circuit 137 in the ESD region 130 according to one aspect of the present disclosure may include at least one thin film transistor T1 , T2 , and T3 .

[0133] Each of the at least one thin film transistor T1, T2, and T3 may have one end connected to the discharge line 140 in the connection region and the other end connected to the ground connection line 137a in the connection region.

[0134] The first electrode of the first thin film transistor T1 may be connected to the discharge line 140 and the first electrode of the third thin film transistor T3. The second electrode of the first thin film transistor T1 may be connected to the first electrode of the third thin film transistor T3. The third electrode of the first thin film transistor T1 may be connected to the first electrode of the second thin film transistor T2 and the second electrode of the third thin film transistor T3.

[0135] The second electrode of the second thin film transistor T2 may be connected to the third electrode of the third thin film transistor T3 , and the third electrode of the second thin film transistor T2 may be connected to the second electrode of the second thin film transistor T2 and the third electrode of the third thin film transistor T3 .

[0136] In this case, the third electrode of the second thin film transistor T2 may be connected to the ground electrode 122 through the ground connection line 137 a .

[0137] One discharge line 140 may be made of a transparent conductive material such as indium tin oxide (ITO). However, the present disclosure is not limited thereto.

[0138] Figure 9 is a diagram illustrating a line structure of one pixel in a display area according to one aspect of the present disclosure. Figure 10 It is shown along Figure 9 FIG is a cross-sectional view taken along line DD' of the line structure.

[0139] Reference Figure 9 In a pixel, the source electrode SE and the drain electrode DE of the thin film transistor can be separated from each other by a predetermined distance. In addition, the drain electrode DE can be connected to the pixel electrode PXL via a contact hole PAS. The pixel electrode PXL can be made of a transparent metal material. For example, the pixel electrode PXL can be made of indium tin oxide (ITO). However, the present disclosure is not limited thereto. The pixel electrode can be made of metals such as copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), and molybdenum (Mo), or alloys thereof.

[0140] In addition, the gate electrode Gate may be provided to overlap with the source electrode SE and the drain electrode DE of the thin film transistor. In addition, the gate electrode Gate may be formed to protrude from the gate line Gate.

[0141] In addition, a common voltage line Vcom may be provided, and the pixel electrode PXL may be provided to overlap the common voltage line Vcom.

[0142] Reference Figure 10A pixel may include a channel region and an array region. A buffer layer BUF may be provided on a base substrate SUB, and a gate electrode GE and a common voltage electrode Vcom may be provided on the buffer layer. The gate electrode GE may be provided in the channel region, and the common voltage electrode Vcom may be provided in the array region.

[0143] In addition, in one pixel, a gate insulating layer GI may be disposed on the gate electrode GE and the common voltage electrode Vcom, and an active layer ACT may be disposed on the gate insulating layer GI. A source electrode SE and a drain electrode DE may be disposed on the active layer ACT. The source electrode SE and the drain electrode DE may be disposed on the active layer ACT and may be spaced apart from each other by a predetermined distance.

[0144] In addition, in one pixel, a planarization layer PLN may be disposed on the source electrode SE, the drain electrode DE, and the active layer ACT, and a pixel electrode PXL may be disposed on the planarization layer.

[0145] In this case, in the channel region, the contact hole PAS hole may extend through a portion of a planarization layer disposed on the drain electrode DE. The pixel electrode PXL may be connected to the drain electrode DE via the contact hole.

[0146] Therefore, when the pixel electrode PXL is formed on the planarization layer in one pixel, at least one discharge line 140 of the electrostatic discharge part 100 of the non-display area N / A may be made of the same material as the pixel electrode PXL.

[0147] As described above, according to the present disclosure, even if static electricity is introduced into the display panel due to the presence of an MPS line on the display panel, the static electricity from the MPS line can flow into the ESD circuit through the discharge line. Therefore, voltage distortion caused by the MPS line can be prevented, thereby preventing defects related to static electricity.

[0148] In the above aspects, the present disclosure has been applied to LCD display devices. However, the present disclosure is not limited thereto and may be applied to OLED display devices.

[0149] As described above, according to the present disclosure, a display panel and a display device including the same can be provided, which can suppress panel defects caused by static electricity induced by inspection lines remaining on the panel after a cutting process of a mother glass in a manufacturing process of the display device.

[0150] The scope of protection of the present disclosure should be understood through the scope of the claims, and all technical concepts within the scope of their equivalents should be understood to be included within the scope of the present disclosure. Although aspects of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not necessarily limited to these aspects. The present disclosure can be implemented in various modified ways without departing from the scope of the technical concept of the present disclosure. Therefore, the aspects disclosed in the present disclosure are not intended to limit the technical concept of the present disclosure, but are intended to describe the present disclosure. The scope of the technical concept of the present disclosure is not limited by these aspects. Therefore, it should be understood that the above aspects are illustrative and not restrictive in all aspects. The scope of protection of the present disclosure should be interpreted by the claims, and all technical concepts within the scope of the present disclosure should be interpreted to be included within the scope of the present disclosure.

Claims

1. A display panel obtained by tangent-forming a mother panel having a plurality of panel regions arranged adjacent to each other during a scribing process, the display panel comprising: A base substrate including a display area and a non-display area; a multi-mode search MPS area disposed in an upper area of ​​the non-display area, wherein the MPS area has at least one MPS line; an ESD region in which at least one electrostatic discharge (ESD) circuit is provided, wherein the at least one ESD circuit discharges static electricity generated in the display region and the non-display region; and an electrostatic discharge portion, the electrostatic discharge portion including at least one discharge line connecting the at least one MPS line and the at least one ESD circuit, The at least one ESD circuit includes at least one pixel ESD circuit, one end of the at least one pixel ESD circuit is connected to each pixel in the display area and the other end is connected to a ground electrode.

2. The display panel according to claim 1, wherein Each of the at least one discharge line is made of the same material as a pixel electrode of the display panel.

3. The display panel according to claim 1, wherein: The electrostatic discharge portion further includes a grounding region between the MPS region and the ESD region, and Wherein, the grounding area has the grounding electrode.

4. The display panel according to claim 3, wherein: The at least one ESD circuit comprises: At least one discharge ESD circuit has one end connected to the discharge line and the other end connected to the ground electrode.

5. The display panel according to claim 4, wherein: The at least one discharging ESD circuit is connected to the ground electrode through a ground connection line.

6. The display panel according to claim 1, further comprising: A common voltage line is provided between the ESD area and the display area, Wherein, the common voltage line is connected to each pixel in the display area.

7. The display panel according to claim 1, wherein: The at least one discharge line in the MPS region is connected to the at least one MPS line through a first contact hole.

8. The display panel according to claim 7, wherein: The at least one MPS line in the MPS region is disposed on the base substrate and is made of a gate metal.

9. The display panel according to claim 8, wherein: The MPS area also includes: A gate insulating layer provided on the gate metal, a planarization layer disposed on the gate insulating layer, a first through hole extending through the planarization layer and the gate insulating layer, wherein the at least one discharge line is disposed on the planarization layer and is connected to the at least one MPS line through the first through hole, and The at least one MPS line is made of the same material as the gate metal.

10. The display panel according to claim 3, wherein: The at least one discharge wire in the ground region extends in a longitudinal direction while overlapping the ground electrode extending in a transverse direction.

11. The display panel according to claim 10, wherein: The grounding area includes: a gate metal disposed on the base substrate; a gate insulating layer disposed on the gate metal; and a planarization layer disposed on the gate insulating layer, Wherein, the at least one discharge line is arranged on the planarization layer.

12. The display panel according to claim 5, wherein: Each of the at least one discharge ESD circuit includes at least one thin film transistor having one end connected to the discharge line in a connection region and the other end connected to the ground connection line in the connection region.

13. The display panel according to claim 1, wherein: The MPS line is made of the same material as the gate metal and is formed in the same process as the gate metal.

14. The display panel according to claim 1, wherein: The discharge wire is made of transparent conductive material.

15. The display panel according to claim 1, wherein The discharge wire is made of a combination of metal and oxide or metal oxide.

16. A display device comprising: a display panel obtained by tangenting a mother panel having a plurality of panel areas arranged adjacent to each other in a scribing process, Wherein, the display panel includes: a base substrate including a display area and a non-display area disposed outside the display area, and a pixel defined in each intersection between a plurality of gate lines and a plurality of data lines in the display area; a multi-mode search MPS area disposed in an upper area of ​​the non-display area, wherein at least one MPS line is disposed in the MPS area; An ESD region in which at least one electrostatic discharge (ESD) circuit is provided, wherein the at least one ESD circuit discharges static electricity generated in the display region and the non-display region; a ground region between the MPS region and the ESD region, wherein a ground electrode is provided in the ground region; and an electrostatic discharge portion comprising at least one discharge line for connecting the at least one MPS line to the at least one ESD circuit; and an in-plane gate GIP for supplying a scan signal to the plurality of gate lines; and a data driver for supplying a data signal to the plurality of data lines, The at least one ESD circuit includes at least one pixel ESD circuit, one end of the at least one pixel ESD circuit is connected to each pixel in the display area and the other end is connected to a ground electrode.

17. A display panel comprising: a display area configured to display an image; a multi-mode search MPS area, the MPS area including a plurality of MPS lines configured to check for disconnection and short circuit of each signal line of a thin film transistor array in the display area; an electrostatic discharge (ESD) region, the ESD region comprising: a plurality of discharge ESD circuits configured to discharge static electricity generated in the display region and a non-display region disposed outside the display region; and a plurality of redundant ESD circuits configured to maintain a constant spacing between the plurality of discharge ESD circuits; a ground region including a ground electrode connected to the plurality of discharge ESD circuits through a ground connection line; and a plurality of discharge lines electrically connecting the plurality of MPS lines and the plurality of discharge ESD circuits and electrically connected to the ground electrode, The ESD region further includes a plurality of pixel ESD circuits connected to each pixel in the display region and the ground electrode. 18 . The display panel of claim 17 , further comprising a common voltage line disposed between the ESD area and the display area and connected to each pixel of the display area.

19. The display panel according to claim 17, wherein: The plurality of discharge lines are formed of a transparent conductive material.

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