A method and apparatus for chip power management

Abstract

The application discloses a chip power management method and device, wherein the chip power management method comprises the following steps: when a low-power mode state machine is in an idle state, receiving a sleep request sent by a central processing unit; according to the sleep request, controlling the low-power mode state machine to switch from the idle state to an exception shielding state; according to a detected enabling signal, adjusting the state of a gated system clock of the chip and a power supply domain, the enabling signal comprising at least one of the following: a running mode enabling signal, a sleep mode enabling signal, a stop mode enabling signal and a standby mode enabling signal; the power supply domain comprising a main power supply domain and a backup power supply domain; when the standby mode enabling signal is detected, controlling a voltage manager in the backup power supply domain to keep a working state, and controlling a voltage manager in the main power supply domain to be powered off, so as to reduce the power consumption of the chip.

Description

Technical Field

[0001] This application relates to the field of chip design, and more particularly to a method and apparatus for chip power management. Background Technology

[0002] With the continuous development of IoT technology, microcontroller unit (MCU) chips and sensors are widely used in systems. MCUs are also known as single-chip microcomputers or microcontrollers. Meanwhile, users are increasingly demanding low-power operation from MCU chips. Therefore, reducing chip power consumption is a pressing issue that needs to be addressed. Summary of the Invention

[0003] In view of this, the main objective of this application is to provide a method and apparatus for chip power management, thereby reducing the power consumption of the chip.

[0004] The first aspect of this application provides a method for chip power management, which is implemented by a power controller, and the method specifically includes: When the low-power mode state machine is in an idle state, it receives a sleep request sent by the central processing unit. Based on the hibernation request, control the low-power mode state machine to switch from the idle state to the abnormal shielding state; Based on the detected enable signal, the state of the chip's gating system clock and power supply domain are adjusted. The enable signal includes at least one of the following: running mode enable signal, sleep mode enable signal, stop mode enable signal, and standby mode enable signal; the power supply domain includes: main power domain and backup power domain. When a standby mode enable signal is detected, the voltage manager in the backup power domain is kept in working state, and the voltage manager in the main power domain is powered off.

[0005] In some implementations of the first aspect of this application, the gated system clock is preset to shield anomalies for a certain number of clock cycles, and the method further includes: When a standby mode enable signal is detected, an asynchronous reset request sent by the chip's wake-up source is received; The system controls the low-power mode state machine to switch back to the idle state based on the asynchronous reset request, and also controls the central processing unit interrupt.

[0006] In some implementations of the first aspect of this application, the power supply domain further includes a power gating domain, and the method further includes: When a sleep mode enable signal is detected, the gating system clock is activated, and the non-volatile memory is switched to standby mode. It receives the power-down signal from the Power Gating domain and controls the voltage manager of the backup power domain to enter a low-drive state based on the power-down signal.

[0007] In some implementations of the first aspect of this application, the gating system clock includes a module operating clock, and the method further includes: When a sleep mode enable signal is detected, the fast clock is turned off according to the preset register, and the module's operating clock is switched to a slow clock.

[0008] In some implementations of the first aspect of this application, after switching the module's operating clock to a slow clock, the method further includes: Receive wake-up commands sent by any one of the following modules: clock alarm module, watchdog alarm module, and chip reset module; The wake-up command controls the low-power state machine to exit its current mode.

[0009] Configure the register parameters and generate the configuration results; Power off the power supply domain based on the configuration results.

[0010] In some implementations of the first aspect of this application, the method further includes: After the module's operating clock switches to a slow clock, the backup power domain is powered.

[0011] A second aspect of this application provides a chip power management apparatus, which includes: a power controller, a central processing unit, a low-power mode state machine, and a power supply domain, the power supply domain including a main power domain and a backup power domain. The power controller is used to receive a sleep request sent by the central processing unit when the low-power mode state machine is in an idle state. The power controller is also used to control the low-power mode state machine to switch from an idle state to an abnormal shielded state based on a hibernation request. The power controller is also used to adjust the state of the chip's gating system clock and power supply domain according to the detected enable signal. The enable signal includes at least one of the following: operating mode enable signal, sleep mode enable signal, stop mode enable signal, and standby mode enable signal. The power controller is also used to control the voltage manager in the backup power domain to remain in operation and to control the voltage manager in the main power domain to be powered off when a standby mode enable signal is detected.

[0012] A third aspect of this application provides a chip power management apparatus, the apparatus comprising: The receiving module is used to receive a sleep request sent by the central processing unit when the low-power mode state machine is in an idle state. The state switching module is used to control the low-power mode state machine to switch from the idle state to the abnormal shielding state according to the hibernation request. The adjustment module is used to adjust the state of the chip's gating system clock and power supply domain according to the detected enable signal. The enable signal includes at least one of the following: operating mode enable signal, sleep mode enable signal, stop mode enable signal, and standby mode enable signal. The power supply domain includes: main power domain and backup power domain. The control module is used to control the voltage manager in the backup power domain to remain in working state and to control the voltage manager in the main power domain to be powered off when a standby mode enable signal is detected.

[0013] In some implementations of the third aspect of this application, the gated system clock can be preset with several clock cycles to shield against anomalies, and the control module is also used for: When a standby mode enable signal is detected, an asynchronous reset request sent by the chip's wake-up source is received; The system controls the low-power state machine to switch back to the idle state based on the asynchronous reset request, and also controls the central processing unit interrupt.

[0014] In some implementations of the third aspect of this application, the power supply domain further includes a power gating domain, and the state switching module is also used for: When a sleep mode enable signal is detected, the gating system clock is activated, and the non-volatile memory is switched to standby mode. It receives the power-down signal from the Power Gating domain and controls the voltage manager of the backup power domain to enter a low-drive state based on the power-down signal.

[0015] In some implementations of the third aspect of this application, the gate control system clock may further include a module operating clock, and the state switching module is further used for: When the sleep mode enable signal is detected, the module's operating clock is switched to a slow clock according to the preset fast clock in the register. Receive wake-up commands sent by any one of the following modules: clock alarm module, watchdog alarm module, and chip reset module; The wake-up command controls the low-power state machine to exit its current mode.

[0016] In some implementations of the third aspect of this application, the apparatus may further include a configuration parameter module for configuring the parameters of the registers and generating configuration results.

[0017] In some implementations of the third aspect of this application, the device may further include a power-off module for performing a power-off operation on the power supply domain according to the configuration result.

[0018] In some implementations of the third aspect of this application, the control module is also used to control the backup power domain to supply power after the module's operating clock switches to a slow clock.

[0019] The fourth aspect of this application provides a computer device, characterized in that the device includes a memory and a processor, the processor being configured to execute a program stored in the memory and perform a method as described in any of the first aspects of this application.

[0020] Compared with the prior art, the technical solution provided in this application has the following beneficial effects: This application includes power management designs for different operating scenarios, enabling the chip to operate in different scenarios according to different power consumption requirements, and reducing chip power consumption by switching between clock cycles.

[0021] In addition to the advantages mentioned above, this application designs two power-off methods—automatic hardware control and software polling control—to mitigate risks. On the software side, registers are configured via software programs to handle the power-down of relevant circuits. After each configuration, the status register is queried to confirm the current power domain state. On the hardware side, the power state of relevant power gating domains is pre-configured after the chip enters stop mode, so that the relevant power domains will automatically power down when the chip enters stop mode and automatically power on upon wake-up. This combined hardware and software approach reduces the risks during the chip wake-up process. Attached Figure Description

[0022] Figure 1 A schematic flowchart illustrating a chip power management method provided in an embodiment of this application; Figure 2 A flowchart illustrating another chip power management method provided in an embodiment of this application; Figure 3 A flowchart illustrating another chip power management method provided in an embodiment of this application; Figure 4 A schematic diagram of another chip power management device provided in an embodiment of this application; Figure 5 A schematic diagram of the structure of a central processing unit provided in an embodiment of this application; Figure 6 A schematic diagram illustrating the composition of another chip power management device provided in an embodiment of this application; Figure 7 This is a schematic diagram of the structure of a computer device provided in an embodiment of this application. Detailed Implementation

[0023] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0024] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in a sequence other than that illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0025] In the embodiments provided in this application, the Synopsys ARC series processor HS4xFS CPU can be used. Two CPU clusters are employed, one configured as a single-core and the other as a quad-core. The ARC HS4xFS processor has a single-core performance of 3.0 DMIPS. One HS4xFS CPU cluster can be configured with a maximum of four CPU cores, operating at 340MHz. The maximum DMIPS is: 3.0 DMIPS / MHz x 340MHz x 5 cores = 5100 DMIPS.

[0026] In this embodiment of the application, during the implementation of chip power management, a chip power management device may include the following hardware equipment: A power controller is used to control the power supply in a chip, such as dividing the power supply domain into a main power domain and a backup power domain, and controlling when to control the main power domain and when to control the backup power domain.

[0027] A low-power mode state machine indicates that the non-volatile memory is in a low-power state.

[0028] The Central Processing Unit (CPU) is one of the main components of an electronic computer, and its core part. Its main functions are to interpret computer instructions and process data in computer software. All operations in a computer are handled by the CPU, which is responsible for reading, decoding, and executing instructions.

[0029] The power supply domain, including the main power domain and the backup power domain, is used for power supply and can also be called a power supply module.

[0030] It should be noted that a low-power mode state machine can also be called a low-power state machine. In some embodiments of this application, the power controller may also employ other control devices, which does not limit the scope of protection of this application.

[0031] In existing technologies, some circuits in chips operate at high clock frequencies. During high-frequency synthesis, synthesis tools often use numerous low-threshold components to optimize timing paths, leading to a significant increase in static power consumption and potentially causing leakage. This application addresses this issue by designing power management solutions for different operating scenarios, enabling the chip to operate under varying power requirements. By combining power gating with clock switching, the chip's power consumption is reduced. This approach results in lower power consumption compared to existing technologies that directly incorporate components.

[0032] Please see Figure 1 Because existing technologies often employ a large number of low-threshold devices to optimize timing paths, resulting in a significant increase in static power consumption, this embodiment of the application provides a chip power management method comprising the following steps: S101: When the low-power mode state machine is in an idle state, it receives a sleep request sent by the central processing unit; Upon receiving a hibernation request, the CPU can enter hibernation mode, at which point it stops running, while peripherals either continue running or stop depending on the application. The analog-to-digital converter (ADC) is one of the chip's peripherals, essentially powered externally.

[0033] S102: Based on the hibernation request, control the low-power mode state machine to switch from the idle state to the abnormal shielding state; An abnormal shielding state refers to a shielding anomaly that occurs within a certain number of clock cycles, preventing interruption when entering a low-power mode.

[0034] S103: Adjust the state of the chip's gating system clock and power supply domain based on the detected enable signal; Specifically, to avoid anomalies such as interrupts or events occurring when entering the low-power chip, which could affect the state machine's flow, the gated system clock can be preset to shield anomalies for a certain number of clock cycles. When the low-power mode state machine detects the standby mode enable signal, the low-power mode state machine is switched back to the idle state by the chip's wake-up source using an asynchronous reset, at which point the central processing unit is interrupted.

[0035] Specifically, the enable signal may include a running mode enable signal, a hibernation mode enable signal, a stop mode enable signal, and a standby mode enable signal.

[0036] It should be noted that the power supply domain includes the main power domain and the backup power domain, which are used to supply power or transmit electrical signals. In some other embodiments, the power supply domain may also include a power gating domain, which, when a sleep mode enable signal is detected, starts the gating system clock and switches the non-volatile memory to standby state. When a power-down signal is received from the Power Gating domain, the voltage manager is controlled to enter a low-drive state according to the power-down signal.

[0037] S104: When a standby mode enable signal is detected, the voltage manager of the backup power domain is kept in working state, and the voltage manager of the main power domain is powered off.

[0038] Before entering standby mode, the gating system clock must be changed to a slow clock before entering low-power mode. In standby mode, power is supplied by the EVR in the backup power domain, and the timing clock is an internal 70kHz backup clock. The backup power domain contains an ECC-protected STB RAM, powered by the EVR, which does not lose power in standby mode and can be used to store critical chip information.

[0039] Figure 1 The process shown adjusts the clock and switches states according to the signals of each mode, avoiding the need to introduce devices to solve the high-frequency path problem and avoiding the generation of static power consumption.

[0040] Please see Figure 2 This application also provides another method for chip power management. To avoid the risks associated with using the PowerGating method, two power-off methods are designed: hardware automatic control and software polling control. In this case, the gate system clock also includes the module running clock. Therefore, this embodiment of the application specifically includes the following steps: S201: When a sleep mode enable signal is detected, the fast clock is turned off according to the preset register, and the module's operating clock is switched to a slow clock.

[0041] The power consumption of the chip in sleep mode can be further reduced by configuring registers in the device used for chip power management to determine whether to power down different power domains in the CPU. The chip can be divided into at least one power domain, each with its own switch, which can be controlled by software. The wake-up domain is a domain that is never powered off; components within this domain are always operational, ready to detect the occurrence of an event and wake up other modules except those affected by the event.

[0042] Specifically, the clock is located inside the chip, which contains multiple clocks. Higher frequency clocks consume more power, while lower frequency clocks consume less power. The power consumption corresponds to the clock speed, so to reduce power consumption, it is necessary to switch clocks, that is, switch the high-power clock to the low-power clock for operation.

[0043] It should be noted that when a sleep mode enable signal is received, the device can enter sleep mode. At this time, the central processing unit is running, and other peripherals are working normally.

[0044] S202: Receive a wake-up command sent by any one of the following modules: clock alarm module, watchdog alarm module, and chip reset module; The clock alarm module, watchdog alarm module, and chip reset module refer to several exit methods for the low-power mode state machine to exit its current mode. Besides these methods, other methods can also be used, depending on the specific mode the low-power mode state machine is currently in. The wake-up command controls the low-power state machine to exit its current mode.

[0045] It should be noted that the wake-up method can be an alarm signal emitted by a buzzer or other alarm methods, and it is powered by the backup power domain. When the main power domain is shut down, the clock will also be turned off, but the slow clock corresponding to the backup power domain will not be powered down. After switching to the slow clock, it can work normally.

[0046] Wake-up is a protective mechanism; it is activated by an alarm when an anomaly or situation requiring special handling occurs. Specifically, a watchdog alarm refers to a watchdog timeout alarm that requires special handling to ensure the correct operation of the microcontroller when the software or firmware does not provide a watchdog. Here, the microcontroller refers to a computer system integrated into a single integrated circuit.

[0047] S203: Configure the parameters of the register and generate the configuration result; It's important to note that register parameters are variables declared using `register` that serve as function arguments, which helps improve function execution speed. However, the keyword `register` is merely a suggestion to the compiler. Some compilers may ignore this suggestion and instead use register allocation algorithms to find the most suitable candidate and place it in the available registers on the chip. Register parameters are meant to remind the compiler to place the variable in a register whenever possible to improve processing speed. The configuration of register parameters can be determined based on actual needs.

[0048] Specifically, the configuration results can be saved in various ways to save the parameters configured in the register, and can also be displayed in various ways for subsequent analysis.

[0049] S204: Perform a power outage operation on the power supply domain based on the configuration results.

[0050] Specifically, the configuration results can determine which part of the power domain needs to be powered down, such as the main power domain being powered down and the backup power domain being powered up, or vice versa. This allows power to be supplied only to the parts that are needed, while power is cut off to the parts that are not, further reducing the power consumption of the chip when entering different modes.

[0051] In other embodiments of this application, the parameters of the register can be preset or modified and updated, which will not be elaborated here.

[0052] In some implementations, S204 can be executed periodically.

[0053] The execution order of S201-S204 can be sequential or simultaneous.

[0054] exist Figure 2 In the embodiments shown in this application, in order to prevent [the spread of the virus], this method enables the terminal device to autonomously control its own identity information, ensuring the randomness of the terminal device's identity information and providing a higher security level compared to existing technical solutions.

[0055] See Figure 3 The control low-power mode state transition diagram is described. In this specific application scenario, a combination of software and hardware is used to manage the chip's power supply. Specifically, chip power management is implemented through the following steps: By default, the chip enters run mode after a reset. In run mode, the CPU retrieves values ​​from the program memory area and executes the program code. Power control allows the chip to operate in different scenarios according to varying power requirements. Based on these different operating scenarios, the chip can be categorized into the following power consumption scenarios: The hibernation sequence is as follows: Software controls the CPU to enter sleep mode -> gated system clock -> NVM memory enters standby mode -> PowerGating domain powers down -> OSC oscillator enters standby mode -> EVR voltage manager enters low drive mode Specifically, the wake-up sequence is as follows: External wake-up (e.g., I / O change) -> EVR / OSC resumes working state -> Release system clock (after OSC stabilizes) -> Power Gating domain powers on -> NVM resumes working state Run mode: This refers to the operating mode. When switching to run mode, the clock is turned on, the CPU executes the program normally, and peripheral modules decide whether to run based on application needs. Peripheral modules can also refer to the software modules of peripheral devices mentioned later.

[0056] Sleep mode: This refers to hibernation mode. When switching to hibernation mode, the CPU stops running, while peripherals remain running or stop depending on the application. In this mode, the CPU stops working, the clock source is running, and other peripherals operate normally. Power consumption can be reduced by disabling the fast clock and switching the module's operating clock to a slow clock through register settings. See Table 1 below for specific control details of this mode. Table 1

[0057] Stop mode: This refers to the stop mode. When switching to stop mode, the chip clock source stops, and the OSC (oscillator), EVR (voltage management), NVM (memory), etc., enter standby mode. See Table 2 below for details on the control of this mode. Table 2

[0058] In this mode, the CPU stops working, all clocks are turned off, and the analog circuits of other chips are shut down according to the application, i.e., the module clocks are turned off.

[0059] Standby mode: This refers to standby mode. When in standby mode, only the core power supply is powered down; it can also be understood as main power supply. For details on the control of this mode, please refer to Table 3. Table 3

[0060] It should be noted that before entering standby mode, the system clock must be switched to a low-speed clock before proceeding with the low-power mode entry operation. In standby mode, power is supplied by the EVR in the backup power domain, and the timing clock is the internal 70kHz backup clock. The backup power domain contains an ECC-protected STB RAM, powered by the EVR in the backup power domain. This RAM does not lose power in standby mode and can be used to store critical chip information.

[0061] exist Figure 3 In the embodiment shown in this application, the software configures registers through software programs to power down related circuits. After each configuration, the status register needs to be queried to confirm the current power domain status. The power domain power-on operation also uses the same operation. The hardware pre-configures the power status of related power gating domains after the chip enters stop mode. After entering stop mode, the related power domains will automatically power down and automatically power on after waking up. In this way, the chip's power consumption is reduced.

[0062] like Figure 4 As shown, this application embodiment also provides an example of the composition of a chip power management device, including: a power controller 401, a central processing unit 402, and a power supply domain 403, wherein the power supply domain 403 includes a main power domain 4031 and a backup power domain 4032. The device may also include a low-power mode state machine 404; The power controller 401 is used to receive a sleep request sent by the central processing unit when the low-power mode state machine 404 is in an idle state. The power controller 401 is also used to control the low-power mode state machine 404 to switch from an idle state to an abnormal shielding state according to a hibernation request. The power controller 401 is also used to adjust the state of the chip's gating system clock and the power supply domain according to the detected enable signal. The enable signal includes at least one of the following: operating mode enable signal, sleep mode enable signal, stop mode enable signal, and standby mode enable signal. The power controller 401 is also used to control the voltage manager in the backup power domain to remain in operation and to control the voltage manager in the main power domain to be powered off when a standby mode enable signal is detected.

[0063] It should be noted that the CPU 402 can employ two clusters, one configured with a single core and the other with four cores. For a detailed architecture diagram of the CPU 402, please refer to [link to CPU 402 architecture diagram]. Figure 5 .

[0064] It is understood that the structure illustrated in this embodiment does not constitute a specific limitation on the device. In other embodiments, the device may include more or fewer components than illustrated, or combine or separate other components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0065] like Figure 6 As shown in the embodiments of this application, another example of the composition of a chip power management device is provided, including: a receiving module 601, a state switching module 602, an adjustment module 603, and a control module 604; The receiving module 601 is used to receive a sleep request sent by the central processing unit when the low-power mode state machine is in an idle state. The state switching module 602 is used to control the low-power mode state machine to switch from the idle state to the abnormal shielding state according to the hibernation request. The adjustment module 603 is used to adjust the state of the chip's gating system clock and power supply domain according to the detected enable signal. The enable signal includes at least one of the following: operating mode enable signal, sleep mode enable signal, stop mode enable signal, and standby mode enable signal. The power supply domain includes: main power domain and backup power domain. The control module 604 is used to control the voltage manager in the backup power domain to remain in working state and to control the voltage manager in the main power domain to be powered off when a standby mode enable signal is detected.

[0066] In some specific implementations, the gate control system clock can be preset to shield anomalies for a certain number of clock cycles. The control module 604 is also used for: When a standby mode enable signal is detected, an asynchronous reset request sent by the chip's wake-up source is received; The system controls the low-power state machine to switch back to the idle state based on the asynchronous reset request, and also controls the central processing unit interrupt.

[0067] In some specific implementations, the power supply domain also includes a power gating domain, and the state switching module 602 is further used for: When a sleep mode enable signal is detected, the gating system clock is activated, and the non-volatile memory is switched to standby mode. It receives the power-down signal from the Power Gating domain and controls the voltage manager of the backup power domain to enter a low-drive state based on the power-down signal.

[0068] In some specific implementations, the gate control system clock may also include a module operating clock, and the state switching module 602 is also used for: When the sleep mode enable signal is detected, the module's operating clock is switched to a slow clock according to the preset fast clock in the register. Receive wake-up commands sent by any one of the following modules: clock alarm module, watchdog alarm module, and chip reset module; The wake-up command controls the low-power state machine to exit its current mode.

[0069] In some specific implementations, the device may also include a configuration parameter module for configuring the parameters of the registers and generating configuration results.

[0070] In some specific implementations, the device may also include a power-off module, which is used to perform a power-off operation on the power supply domain according to the configuration results.

[0071] In some specific implementations, the control module 604 is also used to control the backup power domain to supply power after the module's operating clock switches to a slow clock.

[0072] It is understood that the structure illustrated in this embodiment does not constitute a specific limitation on the device. In other embodiments, the device may include more or fewer components than illustrated, or combine or separate other components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0073] like Figure 7 As shown in the figure, this application embodiment also provides a computer device, including: a memory 701 and a processor 702; Among them, memory 701 is used to store programs; Processor 702 is used to execute programs in memory to achieve the above-mentioned... Figures 1 to 3 This describes a chip power management method.

[0074] Finally, it should be noted that in the embodiments of this application, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A method for chip power management, characterized in that, The method is implemented by a power controller, and the method includes: When the low-power mode state machine is in an idle state, it receives a sleep request sent by the central processing unit. Based on the sleep request, control the low-power mode state machine to switch from the idle state to the abnormal shielding state; Based on the detected enable signal, the state of the chip's gating system clock and power supply domain are adjusted. The enable signal includes at least one of the following: running mode enable signal, sleep mode enable signal, stop mode enable signal, and standby mode enable signal; the gating system clock includes the module running clock, and the power supply domain includes: main power domain and backup power domain. When the standby mode enable signal is detected, the voltage manager in the backup power domain is kept in working state, and the voltage manager in the main power domain is powered off. When the sleep mode enable signal is detected, the fast clock is turned off according to the preset register, and the module's operating clock is switched to a slow clock.

2. The method according to claim 1, characterized in that, The gate control system clock is preset to shield abnormalities for a certain number of clock cycles, and the method further includes: When the standby mode enable signal is detected, the power controller receives an asynchronous reset request sent by the wake-up source of the chip; Based on the asynchronous reset request, control the low-power mode state machine to switch back to the idle state, and control the central processing unit interrupt.

3. The method according to claim 1, characterized in that, The power supply domain also includes a power gating domain, and the method further includes: When the sleep mode enable signal is detected, the gated system clock is activated, and the non-volatile memory is switched to standby mode; Receive the power-down signal of the Power Gating domain, and control the voltage manager of the backup power domain to enter a low-drive state according to the power-down signal.

4. The method according to claim 1, characterized in that, After switching the module's operating clock to a slow clock, the method further includes: Receive wake-up commands sent by any one of the following modules: clock alarm module, watchdog alarm module, and chip reset module; The wake-up command controls the low-power mode state machine to exit its current mode.

5. The method according to claim 1, characterized in that, The method further includes: Configure the parameters of the register and generate the configuration result; Power off the power supply domain based on the configuration results.

6. The method according to claim 4, characterized in that, The method further includes: After the module's operating clock switches to a slow clock, the backup power domain is controlled to supply power.

7. A device for chip power management, characterized in that, The device includes a power controller, a central processing unit, a low-power mode state machine, and a power supply domain, which includes a main power domain and a backup power domain. The power controller is configured to receive a sleep request sent by the central processing unit when the low-power mode state machine is in an idle state. The power controller is also configured to switch the idle state to an abnormal shielding state according to the hibernation request; The power controller is also used to adjust the state of the chip's gating system clock and power supply domain according to the detected enable signal. The enable signal includes a running mode enable signal, a sleep mode enable signal, a stop mode enable signal, and a standby mode enable signal. The gating system clock includes the module running clock. The power controller is also configured to, when the standby mode enable signal is detected, control the voltage manager in the backup power domain to remain in working state, and control the voltage manager in the main power domain to be powered off. The power controller is also configured to, when the sleep mode enable signal is detected, shut down the fast clock according to a preset register and switch the module's operating clock to a slow clock.

8. A device for chip power management, characterized in that, The device includes: The receiving module is used to receive a sleep request sent by the central processing unit when the low-power mode state machine is in an idle state. The state switching module is used to control the low-power mode state machine to switch from the idle state to the abnormal shielding state according to the sleep request; An adjustment module is used to adjust the state of the chip's gating system clock and power supply domain according to the detected enable signal. The enable signal includes at least one of the following: operating mode enable signal, sleep mode enable signal, stop mode enable signal, and standby mode enable signal. The gating system clock includes the module operating clock, and the power supply domain includes: main power domain and backup power domain. The control module is used to control the voltage manager in the backup power domain to remain in working state and to control the voltage manager in the main power domain to be powered off when the standby mode enable signal is detected. The state switching module is also used to switch the module's operating clock to a slow clock by turning off the fast clock according to a preset register when the sleep mode enable signal is detected.

9. A computer device, characterized in that, The device includes a memory and a processor, the processor being configured to execute a program stored in the memory, performing the method as described in any one of claims 1-6.

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