A method for improving the communication rate of hybrid verification of SoC or ASIC

Abstract

The present invention relates to the field of integrated circuit verification technologies, and particularly to a method for improving the communication rate of hybrid verification of an SoC or an ASIC, including a simulation accelerator and a Qemu simulator; the simulation accelerator runs on a host, and the host registers an RPC server based on the RPC protocol standard; the Qemu simulator provides a running environment for a client based on a memory-simulated embedded SoC hardware platform and provides a qapi application programming interface for a virtual device; the client provides a hybrid verification service for a user; the virtual device uses the qapi application programming interface provided by the Qemu simulator to simulate the virtual device, and the virtual device registers an RPC client based on the RPC protocol standard; a multiple cache module is used to provide a multiple cache function, including caching data information, address information, and bitmap information; a data prefetching and caching module is used to provide a function of prefetching data and caching data; the OPS of the virtual device is implemented through the interaction between the RPC client of the virtual device and the RPC server of the host. The present invention has high verification efficiency, strong scalability, strong portability, and high compatibility.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit verification, and particularly to a method for improving the communication rate of SoC or ASIC hybrid verification. Background Art

[0002] With the continuous development of integrated circuit technology, SoC / ASIC is more and more widely used in various fields. Due to the complexity of SoC / ASIC, the verification of SoC / ASIC is particularly necessary. In the SoC / ASIC verification strategy, most designs of SoC / ASIC are verified based on a simulator (simulation software) and an emulator (hardware emulator). In this verification strategy, it is impossible to verify the embedded software before the SoC / ASIC is fabricated into a chip (i.e., before silicon). With the continuous improvement and development of verification technology, a hybrid verification (i.e., realizing the collaborative hybrid verification of pre-silicon hardware and embedded software) solution has been proposed and implemented. The main implementation method of hybrid verification is: verifying SoC / ASIC through an analog processor and a hardware emulator. The current mainstream solution is to use qemu (quick emulator, an analog processor written by Fabrice Bellard and distributed under the GPL license) combined with an emulator based on SEC-MI (Standard Co-Emulation Modeling Interface) (hereinafter referred to as semu) for verification. Specifically: verifying the embedded software through qemu virtual target category CPU; verifying the RTL-based (RTL: Register Transfer Level) hardware design through semu. However, this solution has the following problems:

[0003] In hybrid verification, although it is possible to simulate the Guest OS (client, such as linux) to achieve the simulation verification of pre-silicon hardware and embedded software, due to the limitation of qemu, the communication rate between qemu and semu can only reach a few KB to dozens of KB per second. In the case of large data volume transmission, the rate is too slow, which is far from the rate during the actual use of SoC / ASIC. Summary of the Invention

[0004] Aiming at the problems in the prior art, the present invention aims to provide a method for improving the communication rate of SoC or ASIC hybrid verification, which can increase the communication rate between qemu and semu to several MB per second, and solve the problem that the rate is too slow in the case of large data volume transmission and is far from the rate during the actual use of SoC / ASIC.

[0005] To achieve the above technical objectives, the technical solution of the present invention is: A method for improving the communication rate of mixed verification of SoC or ASIC, including a simulation accelerator and a Qemu simulator;

[0006] The simulation accelerator runs on the host, and the host registers an RPC server based on the RPC protocol standard;

[0007] The Qemu simulator provides a running environment for the client based on memory simulation of the embedded SoC hardware platform, and provides a qapi application programming interface for the virtual device; the client uses the embedded SoC hardware platform simulated by the Qemu simulator, runs the system on the embedded SoC hardware platform, and provides mixed verification services for users through the running system; the virtual device uses the qapi application programming interface provided by the Qemu simulator to simulate the virtual device, and the virtual device registers an RPC client based on the RPC protocol standard; the multiple cache module is used to provide a multiple cache function when writing data to the virtual device, including caching data information, address information, and bitmap information; the data prefetch and cache module is used to provide a function of prefetching data and caching data when reading data from the virtual device;

[0008] The OPS of the virtual device is realized by the interaction between the RPC client and the RPC server of the host.

[0009] Further, the client providing mixed verification services for users at least includes providing programming and running scenarios of embedded application programs and kernel drivers for users.

[0010] Further, the running environment of the Qemu simulator is a Windows system, a Linux system, or a Unix system.

[0011] Further, the RPC client and the RPC server receive and send data based on socket sockets.

[0012] Further, the embedded SoC hardware platform provides one or more of vexpress-a9 ARM single boards, zc706 single boards, and zcu102 single boards.

[0013] Further, the multiple cache module is associated with a first timer for setting the cache interval time.

[0014] Further, when the interval time set by the first timer arrives, the virtual device traverses the bitmap information cached in the multiple cache modules, obtains whether data needs to be sent according to the bitmap information, and converts the continuous address information into the starting address information and the data length through the cached address information, and then transmits the data information to be transmitted, the starting address information, and the data length to the RPC server at one time through the RPC client.

[0015] Further, the data prefetching and caching module is associated with a second timer for setting the invalidation processing interval time of the cached information in the data prefetching and caching module.

[0016] Further, the virtual device obtains data with a length consistent with the cache space size of the data prefetching and caching module through the RPC client, caches it in the cache of the data prefetching and caching module, and records the starting address of the data at the same time.

[0017] Further, when the client obtains the virtual device data through a system call, it first calculates whether the required data is already cached in the cache of the data prefetching and caching module. If it is already cached, the client directly obtains the data from the cache of the data prefetching and caching module; if it is not cached, the virtual device first obtains data with a length consistent with the cache size of the data prefetching and caching module through the RPC client and caches it, and then the client obtains the data from the cache of the prefetching and caching module.

[0018] As can be seen from the above description, the present invention has the following advantages:

[0019] 1. Support embedded SoC hardware platforms with multiple architectures;

[0020] 2. Support the communication rate improvement of various types of analog devices such as TYPE_DEVICE, TYPE_SYS_BUS_DEVICE, TYPE_PCIE_BUS, TYPE_I2C_BUS, etc., and improve the verification efficiency;

[0021] 3. Support the communication behavior rate improvement of various registers, DDR, etc. of the SoC platform, and improve the verification efficiency;

[0022] 4. Easy to implement, strong scalability, and strong portability;

[0023] 5. Support multiple platforms such as windows, linux, unix, etc., and have good compatibility;

[0024] 6. Improve the communication rate through multiple cache modules and data prefetching and caching modules;

[0025] 7. Significantly improve the verification efficiency of SoC or ASIC. Brief Description of the Drawings

[0026] Figure 1 It is a schematic diagram of the architecture of the present invention. Detailed implementation manners

[0027] Combined with Figure 1 , a specific embodiment of the present invention will be described in detail, but the claims of the present invention are not limited in any way.

[0028] As Figure 1 shown, a method for improving the communication rate of hybrid verification of SoC or ASIC includes a simulation accelerator Semu and a Qemu emulator;

[0029] On the simulation accelerator Semu side:

[0030] The simulation accelerator Semu runs on the host Host and is used for hybrid verification. The host Host registers an RPC server RpcServer based on the RPC protocol standard.

[0031] On the Qemu emulator side:

[0032] The Qemu emulator sets or selects the mode as the system mode sys mode, provides a running environment for the guest operating system Guest OS based on memory simulation of the embedded SoC hardware platform, and provides a QAPI application programming interface for the virtual device Virtual device. The running environment of the Qemu emulator can be a Windows system, a Linux system, or a Unix system. The embedded SoC hardware platform provides single boards with various architectures such as vexpress-a9 ARM single boards, zc706 single boards, and zcu102 single boards.

[0033] The guest operating system Guest OS uses the embedded SoC hardware platform simulated by the Qemu emulator, runs the system on the embedded SoC hardware platform, and provides hybrid verification services for users through the running system, including providing programming and running scenarios for embedded application programs and kernel drivers for users.

[0034] The virtual device Virtual device uses the QAPI application programming interface provided by the Qemu emulator to simulate the virtual device, and the virtual device registers an RPC client RpcClient based on the RPC protocol standard.

[0035] The multi-cache module Multi Cache is used to provide a multi-cache function when writing data to the virtual device Virtual device, including caching data information, address information, and bitmap information. The multi-cache module is associated with a first timer Timer1 for setting the cache interval time.

[0036] The data prefetching and caching module (including data prefetching Preload and caching Cache) is used to provide the functions of prefetching data and caching data when reading data from the virtual device Virtual device. The data prefetching and caching module is associated with a second timer Timer2, which is used to set the invalidation processing interval time of the cached information in the data prefetching and caching module.

[0037] During operation:

[0038] The OPS of the virtual device (i.e., operations, including common I / O behaviors such as read, write, access, etc.) are implemented through the interaction between the RPC client RpcClient of the virtual device and the RPC server RpcServer of the host. The RPC client RpcClient and the RPC server RpcServer receive and send data based on the socket socket, and the TCP long connection method is used when establishing the socket connection.

[0039] When the interval time set by the first timer Timer1 arrives, the virtual device Virtual device traverses the bitmap information cached in the multi-cache module Multi Cache. According to the bitmap information, it obtains whether the data needs to send information, and converts the continuous address information into the starting address information and data length through the cached address information. Then, the data information to be transmitted, the starting address information, and the data length are transmitted to the RPC server RpcServer through the RPC client RpcClient at one time.

[0040] The virtual device Virtual device obtains data with a length equal to the cache space size of the data prefetching and caching module through the RPC client RpcClient, and caches it in the cache Cache of the data prefetching and caching module, and records the starting address of the data at the same time.

[0041] When the client Guest OS obtains the data of the virtual device through the system call Sys Call, it first calculates whether the required data is already in the cache Cache of the data prefetch and cache module. If it is already cached, the client Guest OS directly obtains the data from the cache Cache of the data prefetch and cache module. If it is not cached, the virtual device first obtains the data with the same length as the cache size of the data prefetch and cache module through the RPC client and caches it (at this time, the data to be read must be in the cache Cache), and then the client Guest OS obtains the data from the cache Cache. When the interval time set by the second timer Timer2 arrives, the virtual device invalidates the data cached in the Cache to prevent the data in the Cache from being out of sync with the data of the Host. It should be noted that when obtaining the data with the length of the cache size, even if the length of the data read this time is less than the cache size, the data of this length is also read.

[0042] Based on multiple cache modules and the data prefetch and cache module, the present invention can significantly improve the communication rate when writing and reading data, thereby greatly improving the efficiency of hybrid verification.

[0043] The embedded SoC hardware platform of the present invention simultaneously provides single boards of multiple architectures such as vexpress-a9 ARM single board, zc706 single board, and zcu102 single board, which is convenient for customers to choose, improves the convenience of verification, and thus improves the verification efficiency.

[0044] In the specific implementation of the present invention, the Qemu emulator can run on the host where the simulation accelerator Semu is located (i.e., localPC), or it can also run on a remote host (i.e., remote PC), supporting both local and remote modes.

[0045] From the above description, it can be seen that the present invention has the following advantages:

[0046] 1. Support embedded SoC hardware platforms of multiple architectures;

[0047] 2. Support the improvement of the communication rate of various types of analog devices such as TYPE_DEVICE, TYPE_SYS_BUS_DEVICE, TYPE_PCIE_BUS, and TYPE_I2C_BUS, and improve the verification efficiency;

[0048] 3. Support the improvement of the communication behavior rate of various registers, DDR, etc. of the SoC platform, and improve the verification efficiency;

[0049] 4. Easy to implement, strong scalability, and strong portability;

[0050] 5. Support multiple platforms such as windows, linux, and unix, with good compatibility;

[0051] 6. The communication rate is improved through multiple cache modules, data prefetching, and caching modules;

[0052] 7. Significantly improve the verification efficiency of SoC or ASIC.

[0053] It can be understood that the above specific description of the present invention is only for explaining the present invention and is not limited to the technical solutions described in the embodiments of the present invention. Those of ordinary skill in the art should understand that the present invention can still be modified or equivalently replaced to achieve the same technical effect; as long as the usage requirements are met, they are all within the protection scope of the present invention.

Claims

1. A method for improving the communication rate of mixed verification of SoC or ASIC, characterized in that: It includes a simulation accelerator and a Qemu emulator; The simulation accelerator runs on the host, and the host registers an RPC server based on the RPC protocol standard; The Qemu emulator provides a running environment for the guest machine based on memory simulation of the embedded SoC hardware platform and provides a qapi application programming interface for virtual devices; The guest machine uses the embedded SoC hardware platform simulated by the Qemu emulator, runs a system on the embedded SoC hardware platform, and provides a hybrid verification service for users through the running system; the virtual device uses the qapi application programming interface provided by the Qemu emulator to simulate a virtual device, and the virtual device registers an RPC client based on the RPC protocol standard; the multiple cache module is used to provide a multiple cache function when writing data to the virtual device, including caching data information, address information, and bitmap information; the data prefetch and cache module is used to provide a function of prefetching data and caching data when reading data from the virtual device; The OPS of the virtual device is implemented through the interaction between the RPC client and the RPC server of the host.

2. The method for improving the communication rate of the SoC or ASIC hybrid verification according to claim 1, wherein: The hybrid verification service provided by the guest machine for users at least includes providing programming and running scenarios for embedded application programs and kernel drivers for users.

3. The method for improving the communication rate of hybrid verification of SoC or ASIC according to claim 1, characterized in that: The running environment of the Qemu emulator is a Windows system, a Linux system, or a Unix system.

4. The method for improving the communication rate of the SoC or ASIC hybrid verification according to claim 1, characterized in that: The RPC client and the RPC server receive and send data based on a socket socket.

5. The method for improving the communication rate of the mixed verification of SoC or ASIC according to claim 1, characterized in that: The embedded SoC hardware platform provides one or more of a vexpress-a9 ARM single board, a zc706 single board, and a zcu102 single board.

6. The method for improving the communication rate of hybrid verification of SoC or ASIC according to claim 1, wherein: The multiple cache module is associated with a first timer for setting the cache interval time.

7. The method for improving the communication rate of SoC or ASIC hybrid verification according to claim 6, wherein: When the interval time set by the first timer arrives, the virtual device traverses the bitmap information cached in the multiple cache module, obtains whether the data needs to be sent according to the bitmap information, and converts the continuous address information into start address information and data length through the cached address information, and then transmits the data information, start address information, and data length that need to be transmitted to the RPC server through the RPC client at one time.

8. The method for improving the communication rate of the SoC or ASIC hybrid verification according to claim 1, characterized in that: The data prefetch and cache module is associated with a second timer for setting the invalidation processing interval time of the cached information in the data prefetch and cache module.

9. The method for improving the communication rate of the SoC or ASIC hybrid verification according to claim 8, wherein: The virtual device obtains data with a length consistent with the cache size of the data prefetch and cache module through the RPC client and caches it in the cache of the data prefetch and cache module, and records the start address of the data at the same time.

10. The method for improving the communication rate of hybrid verification of SoC or ASIC according to claim 9, wherein: When the guest machine obtains virtual device data through a system call, it first calculates whether the required data is already cached in the cache of the data prefetch and cache module. If it is cached, the guest machine directly obtains the data from the cache of the data prefetch and cache module; if it is not cached, the virtual device first obtains data with a length consistent with the cache size of the data prefetch and cache module through the RPC client and caches it, and then the guest machine obtains the data from the cache of the prefetch and cache module.

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