A Method for Modeling the Irradiation Effect of a Processor and Constructing a Simulation System

Abstract

A method for constructing a processor radiation effect model and simulation system comprises the following steps: first, selecting or designing a processor, and obtaining processor instruction set data and architecture data; then, extracting processor core data based on the processor instruction set data and architecture data, and establishing a processor core model based on the processor core data; then, extracting processor peripheral data based on the processor instruction set data and architecture data, and establishing a processor peripheral model based on the processor peripheral data; then, implementing time synchronization and data transmission functions between the processor core model and the peripheral model, and completing the construction of a processor normal model model and simulation system; then, modifying the processor core model and the processor peripheral model based on the type of faulty processor caused by the radiation effect; and finally, establishing a processor radiation effect model based on the location and probability function of the radiation effect fault. The present invention reflects the behavioral characteristics of the processor, simplifies the model complexity, and realizes the function of simulating processor device degradation caused by the radiation effect.

Description

Technical Field

[0001] The present invention belongs to the technical field of modeling of integrated circuit radiation effect models, and in particular relates to a method for constructing a processor radiation effect modeling and simulation system. Background Art

[0002] At present, with the rapid development of semiconductor technology, various simulation and device models are widely used in aerospace, nuclear industry, particle physics and other fields. They are in various electromagnetic and high-energy particle radiation environments, and are affected by various radiation effects such as total dose radiation, single particle radiation and transient effects. Their working reliability and life cycle are subject to severe tests.

[0003] In recent years, with the development of computer simulation technology, the simulation of radiation effects of electronic systems has provided strong support for the system's radiation resistance design and theoretical research, shortening the R&D cycle and reducing development costs. For processor devices, the conventional RTL functional modeling method ([1] Qureshi YM, Simon WA, Zapater M, et al. Gem5-X: A Many-core Heterogeneous Simulation Platform for Architectural Exploration and Optimization [J]. ACM Transactions on Architecture and Code Optimization, 2021 (4).) has high accuracy. However, the structures of processors of different architectures vary greatly, and the core implementation is complex. The RTL functional modeling method ([2] PowerProbe: Run-time power modeling through automatic RTL instrumentation [C] / / 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018, pp. 743-748.) requires detailed internal information of the processor, and the core information of new processors involves intellectual property information, which is often difficult to obtain. At the same time, this method is difficult to model the processor core and takes a long time. Some processors officially provide netlist files for researchers to simulate. Based on this file, basic simulation of the general functions of the processor can be completed. However, the simulation speed using netlist files is slow and not suitable for simulation of complex scenarios. At the same time, netlist files are difficult to modify and it is not easy to inject radiation effect faults.

[0004] In summary, the problems and defects of the existing radiation effect modeling methods for processor device models are as follows: (1) In the current research on radiation effect modeling of device models, model design is difficult, the computational overhead is high, and the scale of the simulated circuit is limited. At the same time, since the model involves the manufacturer's intellectual property information, the data required for modeling is difficult to obtain; (2) The key parts of most open source models are difficult to change, and it is impossible to add radiation effects on this basis, and it is impossible to establish a radiation effect model; (3) Virtual machine technology greatly improves simulation efficiency, but it is difficult to model the working details of the processor in detail. Summary of the Invention

[0005] In order to overcome the shortcomings of the above-mentioned existing technologies, the purpose of the present invention is to provide a method for constructing a processor radiation effect model and simulation system, which can not only reflect the behavioral characteristics of the processor in detail, but also simplify the model complexity. Its simulation speed is greatly improved compared with the RTL model. In addition, this method can perform data bit flipping and data bit clamping fault injection on the internal register structure, on-chip storage structure and peripheral storage structure of the processor model. Combined with customized fault location and fault probability algorithms, it can simulate the degradation of processor devices caused by radiation effects, providing a path and reference for the radiation-resistant design and research of device models.

[0006] In order to achieve the above object, the technical solution adopted by the present invention is:

[0007] A method for modeling and simulating a processor radiation effect model comprises the following steps:

[0008] Step 1: Select or design a processor;

[0009] Step 2: Get processor instruction set data and architecture data;

[0010] Step 3: Extract processor core data based on processor instruction set data and architecture data;

[0011] Step 4: Establish a processor core model based on the processor core data;

[0012] Step 5: Extract processor peripheral data based on processor instruction set data and architecture data;

[0013] Step 6: Establish a processor peripheral model based on the processor peripheral data;

[0014] Step 7: Implement the time synchronization and data transmission functions between the processor core model and the peripheral model, and complete the modeling and simulation system construction of the processor normal state model;

[0015] Step 8: Modify the processor core model and processor peripheral model based on the type of processor failure caused by the radiation effect;

[0016] Step 9: Establish a processor radiation effect model based on the radiation effect failure location and probability function.

[0017] The purpose of steps 1 and 2 is to obtain the instruction set data and architecture data of a certain processor in preparation for subsequent modeling work; the processor data collection method includes: using digital verification simulation methods such as UVM or direct programming and testing methods of real devices, combined with the official data manual of the processor architecture, to measure the processor instruction set data and processor architecture data.

[0018] The purpose of step 3 is to summarize and extract the data required for processor core modeling, prepare for subsequent processor core modeling, analyze the processor instruction set data and architecture data obtained in step 2, and extract the various data required to establish the processor core model, including: processor instruction set data; processor internal register structure data; processor on-chip storage structure data; processor internal integer and floating-point operation unit data; processor interrupt mechanism data and other data related to processor functions.

[0019] The purpose of step 4 is to build a processor core model, which reflects the basic functional simulation around the processor pipeline. Based on the data obtained in step 3, the following data structures or functions are established:

[0020] 4.1) Establish a structure to simulate the physical storage structure of the processor, and map the processor's internal registers, on-chip storage and other storage structures to the host memory;

[0021] 4.2) Establish kernel functions based on various processor functions, including register reading and writing, integer data operations, external memory access, etc.

[0022] 4.3) Based on the working principle of the processor pipeline, a pipeline simulation function from instruction fetch to execution is established, and the processor pipeline operation is simulated through a function sequential call mechanism based on an event queue;

[0023] 4.4) Based on the processor interrupt control mechanism, establish an interrupt simulation function to simulate the processor interrupt;

[0024] The establishment of the pipeline simulation function includes the following basic functions: instruction fetch function, instruction decoding function, disassembly function, and function execution function; the function of the instruction fetch function is to obtain the execution instruction of this cycle based on the execution result of the previous instruction cycle; the function of the instruction decoding function is to call the corresponding disassembly function and function execution function according to the value result of the instruction fetch function; the function of the disassembly function is to decompile the assembly instruction corresponding to the instruction based on the instruction decoding result and the instruction access target; the function of the function execution function is to call the corresponding function function according to the decoding result to realize the simulation of the processor core function.

[0025] The purpose of step 5 is to summarize and extract the data required for processor peripheral modeling to prepare for subsequent processor peripheral modeling; by analyzing the processor instruction set data and architecture data obtained in step 2, the relevant data required to establish the processor peripheral model is extracted, including: processor on-chip interconnect bus protocol data, interrupt manager data, processor on-chip peripheral data, and processor external function interface mapping data.

[0026] The purpose of step 6 is to establish a processor peripheral model, which includes the processor on-chip bus management structure model, the processor interrupt controller model and the processor functional peripherals. These three models are a series of necessary units to simulate the basic functions of the processor. At the same time, the establishment of this type of model is completed through hardware description language modeling.

[0027] The purpose of step 7 is to build a joint simulation platform for the joint simulation of the processor core model and the processor peripheral model, thereby establishing a complete processor simulation model and simulation system in a non-radiation environment; the processor core model is modeled by the host function and host memory based on a high-level language, which occupies an independent simulation process; the processor peripheral model is modeled by the hardware description language and can run on various commercial or non-commercial hardware simulation platforms, that is, it also occupies an independent simulation process.

[0028] Since the processor core model and processor peripheral model established by high-level language and hardware description language are simulated under two processes respectively, a simulation process synchronization mechanism based on the process communication mechanism of the host is established. The functions of the simulation process synchronization mechanism include: a time synchronization mechanism, which maps the time unit of the simulation time under the processor peripheral model to the number of processor instruction executions under the core model; a data transmission mechanism, which maps the memory access data of the processor core model to the bus timing of the processor peripheral model (including address lines, control lines, and data lines).

[0029] The purpose of step 8 is to add fault models of various data storage modules in the processor core and peripherals under irradiation environment to provide support for simulating processor device degradation caused by irradiation effects; according to the data bit flip, data bit clamping, and data transmission delay faults that may be caused by the processor in the actual working environment: add register and on-chip memory data modification functions to the processor core model to provide fault injection function; add bus delay module, clamping fault injection module, and bit flip module to the processor peripheral model.

[0030] The purpose of step 9 is to establish an irradiation effect fault injection module based on the irradiation effect occurrence location and probability function. This model supports simulating different fault locations and fault types during the simulation process by adding random fault injection scripts or serialized fault injection scripts. Finally, this module is added to the processor simulation model in a non-radiation environment to establish a processor irradiation effect model.

[0031] The present invention has the following beneficial effects: Because it employs a method for separate modeling and joint simulation of the processor core and peripherals, a universal core simulation model can be established for processors with a specified instruction set. Furthermore, fine-grained peripheral simulation models can be established based on the specific processor architecture. This method simplifies the processor modeling process, while achieving higher simulation speeds than RTL models. It also supports the injection and simulation of radiation-effect faults in the processor's internal register structure, on-chip memory structure, peripherals, and buses. This invention provides model support for functional simulation of electronic systems in irradiated environments. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a flow chart of an embodiment of the present invention.

[0033] Figure 2 It is a schematic diagram of the structure of the processor core model according to an embodiment of the present invention.

[0034] Figure 3 It is a record fragment of instruction execution when the processor core of an embodiment of the present invention is running.

[0035] Figure 4 This is a register data record fragment when the processor core is running in an embodiment of the present invention.

[0036] Figure 5 It is a schematic diagram of the structure of the processor peripheral model according to an embodiment of the present invention.

[0037] Figure 6 This is the waveform resulting from the radiation effect bit flip fault injection into the AHB bus portion of the processor according to an embodiment of the present invention.

[0038] Figure 7 This is the waveform resulting from continuous bit flip fault injection due to the radiation effect on the interrupt signal line of the processor according to an embodiment of the present invention. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the embodiments and drawings. It should be understood that the embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0040] like Figure 1 As shown, a method for modeling and simulating a processor radiation effect model includes the following steps:

[0041] S101: Select or design a processor device;

[0042] S102: Acquire processor instruction set data and architecture data;

[0043] S103: Extracting processor kernel data based on processor instruction set data and architecture data;

[0044] S104: Establishing a processor core model according to the processor core data;

[0045] S105: Extracting processor peripheral data based on processor instruction set data and architecture data;

[0046] S106: Establishing a processor peripheral model according to the processor peripheral data;

[0047] S107: Implementing the time synchronization and data transmission functions between the processor core model and the peripheral model, completing the modeling and simulation system construction of the processor normal state model;

[0048] S108: Modify the processor core model and the processor peripheral model according to the type of faulty processor caused by the radiation effect;

[0049] S109: Establishing a processor radiation effect model based on the radiation effect failure occurrence location and probability function.

[0050] In Example 1, a Sparcv8 architecture Leon3 processor is used as a test and modeling device. In order to obtain the working data of the original electronic device, the method of direct measurement of the real device is combined with the official data manual of the Leon3 architecture and the official manual of the sparc instruction set to obtain the necessary data for modeling, including the instruction set corresponding encoding, instruction classification and various instruction functions, interrupt mechanism and interrupt jump table, register structure, instruction delay slot mechanism, etc. Then, the obtained processor instruction set and architecture data are analyzed to extract the target instruction set instruction encoding and instruction function, the number and switching mechanism of the processor general register window, the processor floating-point operation rules and operation flow, the processor interrupt jump related registers and working mode, and the processor jump instruction delay slot mechanism related data. Based on the obtained data, the following data structure or function should be established:

[0051] (1) Establish a structure to simulate the physical storage structure of the processor, and map the processor's internal registers, on-chip storage and other storage structures to the host memory;

[0052] (2) Establish kernel function functions based on various instruction functions in the instruction set, including register reading and writing, floating-point data operations, external memory access, interrupt return and other Sparcv8 instruction set related function functions;

[0053] (3) According to the working principle of the processor pipeline, a pipeline simulation function from instruction fetch to execution is established, including the following basic functions: instruction fetch function, instruction decoding function, disassembly function, and function execution function, to realize the simulation of the processor core function.

[0054] In addition, based on the actual processor memory needs in operation, the virtual on-chip storage is regarded as part of the processor core, and a virtual on-chip storage structure model is established to support the core functional unit to directly access the data of the on-chip storage model through function calls. Through the above method, the processor core model structure is established as follows Figure 2 As shown in Figure 2, the kernel simulator occupies an independent process to simulate the processor pipeline operation, which can simulate the basic operation of the Sparcv8 instruction set and record the instruction execution sequence and register data changes during the operation. Some of the instruction execution records and register data records are shown in Figure 2. Figure 3 、 4 shown.

[0055] Then analyze the initially obtained processor instruction set and architecture data to determine: processor on-chip interconnect bus protocol data. In this embodiment, the processor adopts AHB and APB communication protocols; processor interrupt controller working mode, including priority determination mode and interrupt retention and clearing mechanism; processor on-chip peripheral information, including register address allocation and function allocation of functional peripherals such as serial port peripherals, I2C peripherals, timer peripherals, etc.; processor external function interface mapping. Based on the obtained data, a processor peripheral model is established using hardware description language. In this embodiment, the target Sparc architecture processor adopts AHB and APB protocols to complete the communication between the processor core and peripherals; it has an independent interrupt controller that meets the requirements of the Sparc architecture; the processor includes two serial port peripherals, a set of timer peripherals with a specific structure, and a 1553B protocol communication peripheral. In this embodiment, the above-mentioned peripheral and interrupt controller models are established using Verilog language, and an AHB-APB bridge model is designed. The advantage of this modeling method is that it can support the expansion of various peripheral open source IPs or user IPs on the processor bus in subsequent development. The simulation of the processor peripheral model occupies an independent process, and the simulation is completed through ModelSim. Its structural diagram is shown as follows. Figure 5 shown.

[0056] Then, a simulation process synchronization mechanism based on the process communication mechanism of the host is established between the processor core model and the processor peripheral model. The method is as follows: a time synchronization function and a data transmission function are added under the processor core model. The time synchronization function is responsible for time synchronization with the processor peripheral model; the data transmission function is responsible for transmitting processor access data to the peripheral access process and receiving peripheral return data; a special core connection module is added under the processor peripheral model. The module is responsible for receiving access data from the processor core model, then unpacking the data and sending the access data to the processor peripheral model; for the data and interrupt signal data returned by the processor peripheral model, the module is also responsible for data packaging and transmitting it to the processor core model; at the same time, the module is responsible for simulation time synchronization between the processor core model and the peripheral model.

[0057] Fault models for various data storage modules within the processor core and peripherals under irradiation conditions were then established and added to the corresponding models to support simulation of processor device degradation caused by irradiation. Based on the data bit flipping, data bit clamping, and data transmission delay faults that may be caused by the processor under actual operating conditions, register and on-chip memory data modification functions were added to the processor core model to provide fault injection capabilities. Bus delay modules, clamping fault injection modules, and bit flip modules were added to the processor peripheral models.

[0058] Finally, combined with the test data, according to the radiation effect occurrence location and probability function, an radiation effect fault injection module is established. This module supports simulating different fault locations and different fault types during the simulation process by adding random fault injection scripts or serialized fault injection scripts. Finally, the module is added to the processor simulation model to obtain the processor radiation effect model. In this embodiment, radiation fault injection is performed on the AHB communication part and the interrupt signal transmission part of the processor peripherals. The AHB communication part performs a partial bit flip fault injection on the data of the address bus, which is manifested as the lower four bits of the address line being affected and becoming 0x2. A continuous bit flip fault is added to the interrupt signal transmission part, which is manifested as the signal line waveform being continuously flipped over a period of time. The fault injection result waveform is shown in the figure below. Figure 6 、 7 shown.

Claims

1. A method for modeling and simulating a processor radiation effect model, characterized in that: The following steps are involved: Step 1: Select or design a processor; Step 2: Get processor instruction set data and architecture data; Step 3: Extract processor core data based on processor instruction set data and architecture data; Step 4: Establish a processor core model based on the processor core data; Step 4: Based on the data obtained in step 3, establish the following data structure or function: 4.1) Establish a structure to simulate the physical storage structure of the processor, and map the various storage structures of the processor's internal registers and on-chip storage to the host memory; 4.2) Establish kernel functions based on various processor functions, including register reading and writing, integer data operations, and external memory access functions; 4.3) Based on the working principle of the processor pipeline, a pipeline simulation function from instruction fetch to execution is established, and the processor pipeline operation is simulated through a function sequential calling mechanism based on an event queue; 4.4) Based on the processor interrupt control mechanism, establish an interrupt simulation function to simulate the processor interrupt; The establishment of the pipeline simulation function includes the following basic functions: instruction fetch function, instruction decoding function, disassembly function, and function execution function; the instruction fetch function is used to obtain the execution instruction of this cycle according to the execution result of the previous instruction cycle; the instruction decoding function is used to call the corresponding disassembly function and function execution function according to the value of the instruction fetch function; the disassembly function is used to decompile the assembly instruction corresponding to the instruction according to the instruction decoding result and the instruction access target; the function execution function is used to call the corresponding function function according to the decoding result to realize the simulation of the processor core function; Step 5: Extract processor peripheral data based on processor instruction set data and architecture data; Step 6: Establish a processor peripheral model based on the processor peripheral data; The processor peripheral model established in step 6 includes the processor on-chip bus management structure model, the processor interrupt controller model, and the processor functional peripherals. These three models are units that simulate the basic functions of the processor and are modeled using the hardware description language. Step 7: Implement the time synchronization and data transmission functions between the processor core model and the peripheral model, and complete the modeling and simulation system construction of the processor normal state model; Step 8: Modify the processor core model and processor peripheral model based on the type of processor failure caused by the radiation effect; Step 8: Based on the data bit flip, data bit clamping, and data transmission delay faults that may be caused by the processor in the actual working environment, register and on-chip memory data modification functions are added to the processor core model to provide fault injection capabilities; Add bus delay module, clamp fault injection module and bit flip module to the processor peripheral model; Step 9: Establish a processor radiation effect model based on the radiation effect failure location and probability function.

2. The method according to claim 1, wherein: Step 2: The processor data collection method includes: using UVM's digital verification simulation method or a real device direct programming test method, combined with the official data manual of the processor architecture, to measure the processor instruction set data and processor architecture data.

3. The method according to claim 1, wherein: Step 3 analyzes the processor instruction set data and architecture data obtained in step 2, and extracts the various data required to establish the processor core model, including: processor instruction set data; processor internal register structure data; processor on-chip storage structure data; processor internal integer and floating-point operation unit data; processor interrupt mechanism data and various data related to the processor function.

4. The method according to claim 1, wherein: Step 5 extracts the relevant data required to establish the processor peripheral model by analyzing the processor instruction set data and architecture data obtained in step 2, including: processor on-chip interconnect bus protocol data, interrupt manager data, processor on-chip peripheral data, and processor external function interface mapping data.

5. The method according to claim 1, wherein: Step 7: Establish a complete processor simulation model and simulation system in a non-radiation environment; the processor core model is modeled by host functions and host memory based on a high-level language, which occupies an independent simulation process; The processor peripheral model is modeled using a hardware description language and runs on various commercial or non-commercial hardware simulation platforms, also occupying an independent simulation process. Therefore, a simulation process synchronization mechanism based on the process communication mechanism of the host is established. The functions of the simulation process synchronization mechanism include: a time synchronization mechanism that maps the time unit of the simulation time in the processor peripheral model to the number of processor instructions executed in the core model; The data transmission mechanism maps the memory access data of the processor core model with the bus timing of the processor peripheral model, including address lines, control lines, and data lines.

6. The method according to claim 1, wherein: Step 9: Based on the radiation effect occurrence location and occurrence probability function, establish a radiation effect fault injection module. This module supports simulating different fault locations and different fault types during the simulation process by adding random fault injection scripts or serialized fault injection scripts. Finally, add this module to the processor simulation model in a non-radiation environment to establish a processor radiation effect model.

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