A thermal modeling method for double-sided heat dissipation planar interconnection module based on diffusion thermal resistance

Abstract

The application discloses a double-sided heat dissipation planar interconnection module thermal modeling method based on diffusion thermal resistance, which comprises the following steps: firstly, COMSOL is used to simulate heat flow distribution and temperature distribution under a simple layout; and then, a special heat transfer path caused by thermal coupling effect, edge effect and packaging structure is considered, and a fast thermal modeling method is established. The application has small calculation amount, fast calculation speed and strong adaptability to module structure, and is suitable for fast thermal modeling of the double-sided heat dissipation planar interconnection module in a design stage.

Description

Technical Field

[0001] This invention belongs to the field of power electronic devices, and specifically relates to a thermal modeling method for a double-sided heat dissipation planar interconnect module based on diffusion thermal resistance. Background Technology

[0002] With the development of new energy vehicles, rail transit, smart grids and next-generation mobile communications, the requirements for power semiconductor modules are also increasing. This is mainly reflected in the need for power modules with higher power and better reliability. However, traditional power modules currently have problems such as large parasitic parameters in the packaging and large junction thermal resistance, which cannot fully utilize the performance of power semiconductors. Therefore, the development of power modules with new packaging structures has become necessary. The double-sided heat dissipation planar interconnect module is a new packaging structure with the advantages of small parasitic parameters and strong heat dissipation capacity. However, due to its complex structure, the characterization of its thermal model is difficult.

[0003] Regarding methods for module thermal modeling, the thermal network model method establishes a Foster or Cauer thermal network by considering a one-dimensional heat transfer path. This model performs well when describing single-chip modules, but it can cause significant errors in multi-chip parallel modules due to thermal coupling.

[0004] For accurate modeling of module temperature, the industry generally uses the finite element method, based on commercial finite element software such as COMSOL and ANSYS. However, this method has problems such as large computational load and long computation time, which will limit the efficiency of module optimization and iteration during the design phase.

[0005] Some scholars at home and abroad have proposed a thermal modeling method based on Fourier series, which simplifies the module geometric model, writes the heat conduction equation, and describes the heat flow of the power module by expanding the function to be solved into a Fourier series. This method is only applicable to traditional packaging structures and not to new packaging structures. Summary of the Invention

[0006] The purpose of this invention is to provide a thermal modeling method for double-sided heat dissipation planar interconnect modules based on diffusion thermal resistance, so as to solve the problems existing in the prior art. This invention requires less computation, has a fast calculation speed, and is highly adaptable to the module structure, making it suitable for rapid thermal modeling in the design stage of double-sided heat dissipation planar interconnect modules.

[0007] To achieve the above objectives, the present invention adopts the following technical solution:

[0008] A thermal modeling method for a double-sided heat dissipation planar interconnect module based on diffusion thermal resistance includes the following steps;

[0009] S1: Set the thickness of each layer of the planar interconnect module DBC, chip model, interconnect structure, solder layer type and thickness, set the ambient temperature and convective heat transfer coefficient, set the structure of the module, set the loss of each chip, and set the initial value of heat loss transferred from the chip to the top DBC and bottom DBC.

[0010] S2: In COMSOL, model the bottom DBC, chip and corresponding solder layer of the chip. The model only considers the bottom DBC and one chip, and the chip is located in the center of the DBC. Assign a set value to the chip and simulate to obtain the average chip temperature and average copper layer temperature when the copper layer on the DBC has different areas, as well as the vertical heat flux distribution and temperature rise distribution of the lower surface of the upper copper layer when the copper layer area on the bottom DBC is the largest.

[0011] S3: Based on the module's structure, obtain the copper layer where the chip is located. Based on the size of the copper layer and the results in S2, obtain the corresponding average temperature rise of the chip and the average temperature rise of the copper layer.

[0012] S4: Considering the thermal coupling effect and edge effect between chips, and combining the results obtained in S2, calculate the temperature rise of chips on the same DBC copper layer due to thermal coupling and edge effect;

[0013] S5: Based on the heat flux distribution and average temperature information obtained in S2, obtain the temperature rise of another copper layer and the chip on another copper layer caused by the heat loss of the chip on the same copper layer in the bottom DBC. Combine the calculation results of S3 and S4 to complete the thermal model of the bottom heat transfer channel.

[0014] S6: In COMSOL, model the top DBC, chip, copper busbar, and the solder layer used to connect the three. The model only considers the DBC, one chip, and copper busbar, with the chip center located at the center of the DBC. The chip is connected to the top DBC through the copper busbar and solder layer. Simulate to obtain the average temperature of the chip and the vertical heat flux when the copper layer area is at its maximum when the copper layer under the top DBC is of different sizes.

[0015] S7: Consider the thermal coupling effect and edge effect between the copper layers under the top DBC, and calculate the temperature rise of the chip on the same DBC copper layer due to the thermal coupling effect and edge effect of the copper layers under the top DBC based on the average temperature and heat flux information calculated in S6, and complete the thermal model of the top heat transfer channel.

[0016] S8: Considering the phenomenon of heat transfer from the bottom DBC to the top DBC via the copper busbar, estimate the average temperature at the connection between the copper busbar and the bottom DBC based on the heat flux distribution obtained in S2. Estimate the average temperature at the connection between the copper busbar and the top DBC based on the thermal resistance of the copper busbar and the heat transferred from the chip to the top DBC through the copper busbar. Calculate the heat loss transferred from the bottom DBC to the top DBC via the copper busbar based on the thermal resistance of the copper busbar.

[0017] S9: The bottom heat transfer channel thermal model established in S5, the top heat transfer channel thermal model established in S7, and the supplementary model in S8 together form the thermal model of the double-sided heat dissipation planar interconnect module. By giving various parameters of the interconnect module, the temperature rise and heat transfer of each chip can be obtained. The specific process is as follows: Based on the heat loss from the bottom DBC to the top DBC calculated in S8, considering the heat transfer from the copper busbar between the two DBCs, the temperature rise of each chip is calculated using the bottom heat transfer channel thermal model and the top heat transfer channel thermal model respectively. The calculation results of the two models are compared. If the error is less than the set value, the chip temperature rise calculated by the bottom heat transfer channel thermal model and the value of heat transferred from the chip to the top DBC and bottom DBC are output, and the modeling is completed; otherwise, the ratio of heat transferred from the chip to the top DBC and bottom DBC is iteratively adjusted and re-substituted into the model for calculation.

[0018] Furthermore, in step S2, in the constructed model, the chip is located at the center of the DBC, and the chip is assigned P. test =50W power loss. The copper layer on the DBC is kept at the center of the DBC, with its length varying from its longest point to the chip length and its width varying from its widest point to the chip width. The average chip temperature and average copper layer temperature are simulated. The vertical heat flux distribution F(x,y) and temperature rise distribution θ on the lower surface of the copper layer are also simulated when the copper layer area is maximized. spread (x,y), where x and y represent the coordinates of a point on the copper layer with the chip center as the origin.

[0019] Further, in step S3, an interpolation method is used to fit the average temperature rise of the chip and the average temperature rise of the copper layer in S2, to obtain a fitting function θ of the average temperature rise of the chip and the average temperature rise of the solder layer with respect to the length and width of the copper layer. die (L Cu W Cu ) and θ trace (L Cu W Cu ), where θ die θ represents the average temperature rise of the chip. trace L represents the average temperature rise of the weld layer. Cu W is the length of the copper layer. Cu Given the width of the copper layer, obtain the length and width of the largest rectangle that the copper layer containing the chip can contain. Substitute these widths into the fitting function to calculate the average temperature rise of the chip and the average temperature rise of the copper layer. The largest rectangular copper layer that the copper layer connected to chip i through the solder layer can contain is called the copper layer containing chip i, denoted as Gi.

[0020] Furthermore, in step S4, the coupling thermal resistance caused by the thermal coupling effect between chips is considered by the following formula:

[0021]

[0022] Where i, j are the chip numbers on the same copper layer, R ij θ represents the coupling thermal resistance between chip j and chip i. spread This represents the temperature rise distribution on the lower surface of the copper layer on the DBC, x cj y cj S represents the center coordinates of chip j. cj When the integral sign is present, it represents the region where chip j is located; otherwise, it represents the area of ​​chip j.

[0023] Edge effects are considered using the following formula: the heat diffused when the chip is in the center of the copper layer is:

[0024]

[0025] The heat dissipated by chip i when it is in its actual location is:

[0026]

[0027] Among them, S traceGi x represents the region of the copper layer where chip i is located. ci y ci Let θ represent the center coordinates of chip i. Considering edge effects, the temperature rise of chip i is θ. die P ei / P e0 , where θ die This represents the average temperature rise of the chip, calculated based on the size of the copper layer containing the chip.

[0028] Considering both edge effects and coupling effects, and scaling proportionally to a heat loss of 50W for chip i, the temperature rise of chip i caused by the influence of other chips on the same copper layer and its own heat loss is:

[0029]

[0030] In the formula, θ testchip P represents the average chip temperature when the DBC copper layer area is at its maximum in S2. ei and P ej R represents the power consumption of diffusion at chips i and j, respectively. ji θ represents the coupling thermal resistance between chip i and chip j. die_i and θ die_j The functions θ are calculated based on the size of the copper layer where chips i and j are located, respectively. die (L Cu W Cu The value of P test To apply a loss to S2, P Dj and P DiThese represent the heat loss transferred from the bottom heat transfer channel to chips i and j, respectively.

[0031] Furthermore, in step S5, considering the thermal coupling between chips on different copper layers, and taking chips i and m on different copper layers, if the copper layer on DBC is in its maximum state, then the temperature rise effect of chip i on the portion of its copper layer Gi is as follows:

[0032]

[0033] Based on the law of energy conservation, the correction coefficient for the influence of chip i on the copper layers outside its copper layer is obtained as follows:

[0034]

[0035] Where, ΔT isolation S represents the average temperature rise on the upper surface of the DBC insulating layer when a set loss is applied to the chip in S2. isolation θ represents the area of ​​the upper surface of the DBC insulation layer. traceGi S represents the average temperature rise of the copper layer containing chip i, obtained in S3. traceGi This represents the area of ​​the copper layer containing chip i;

[0036] Therefore, the effect of chip i on the temperature rise of the copper layer where chip m is located is as follows:

[0037]

[0038] Similarly, the effect of chip i on the temperature rise of chip m is obtained as follows:

[0039]

[0040] Scaling the data proportionally to a heat loss of 50W for chip i, the impact of other chips not on the same copper layer as chip i on the temperature rise of chip i is obtained as follows:

[0041]

[0042] Where P Dm This refers to the heat loss transferred from the bottom heat transfer channel of chip m.

[0043] Therefore, the temperature rise of chip i due to the heat loss of all chips is:

[0044] θ diei_all =θ diei_same +θ diei_diff

[0045] Scaling proportionally to a heat loss of 50W for chip i, the temperature rise of the copper layer containing chip i due to the heat loss of all chips is:

[0046]

[0047] Where j represents all chips on the same copper layer as i, including i; m represents chips on different copper layers than chip i.

[0048] Therefore, the sum of the one-dimensional thermal resistance and diffusion thermal resistance from chip i to its copper layer is calculated as follows:

[0049]

[0050] According to N on the copper layer where chip i is located i The sum of the heat losses of each chip is N. i P test Scaling proportionally, the diffusion thermal resistance between the copper layer containing chip i and the ceramic substrate is:

[0051]

[0052] Where, N i This indicates the number of chips on the copper layer where chip i is located; j represents all chips on the same copper layer as i, including i; m represents chips on different copper layers than chip i.

[0053] Finally, the temperature rise of chip i is calculated using the following formula, and the same applies to other chips;

[0054]

[0055] Among them, R residue This represents the one-dimensional equivalent heat of the bottom DBC ceramic layer, the lower copper layer, and the heat convection process.

[0056] Obstruction;

[0057] At this point, the thermal model of the bottom heat transfer channel has been established.

[0058] Further, in step S6, the chip is located at the center of the DBC, and a loss of 20W is applied to the chip. The copper layer under the top DBC is controlled to consist of only one copper layer. The length of this layer varies from its longest length to the length required to fully contact the copper busbar connected to the chip in the longitudinal direction, and the width varies from its widest length to the length required to fully contact the copper busbar connected to the chip in the width direction. The average chip temperature is simulated, and the vertical heat flux distribution F on the upper surface of the copper layer of the top DBC is recorded when the area of ​​the upper copper layer is at its maximum. up Temperature distribution θ on the upper surface of the DBC copper layer up If the copper busbar has different shapes, then each shape will be simulated.

[0059] Further, in step S7, considering the thermal coupling effect on the copper layer under the top DBC, the solder layer at the location where the copper busbar corresponding to chip i is connected to the top DBC is denoted as Solderi_up, with its center position being (x ciup y ciup The center position is defined as the geometric center of the chip, Solderi_up represents all the solder layers connecting the copper busbar corresponding to chip i to the top DBC, and the coupling thermal resistance R is... cij_up j and i are connected on the same top DBC lower copper layer, and the calculation is as follows:

[0060]

[0061] Among them, S solderj_up The area under the integral sign represents the region where the weld layer is located; otherwise, it represents the area of ​​this region.

[0062] When calculating the chip temperature, simply replace the chip's one-dimensional thermal resistance with the thermal resistance shared by the chip and the copper busbar. The rest is the same as the thermal model of the bottom heat transfer channel, thus completing the thermal model of the top heat transfer channel.

[0063] Furthermore, in step S8, considering the heat transferred from the bottom DBC to the top DBC via the copper busbar, the temperature at the contact point between the top DBC and the copper busbar is first estimated using the following formula:

[0064]

[0065]

[0066] Among them, T LU The estimated average temperature at the contact points between the top DBC and all copper busbars, where i and j represent the chips connected to the top DBC, and N... i T represents the number of chips connected to the top DBC copper layer to which chip i is connected. UpPathi P represents the temperature of chip i calculated by the thermal model of the top heat transfer channel. Ui This indicates the heat transferred by chip i through the top heat transfer channel; R Cu R represents the equivalent thermal resistance of the copper busbars of all chips on this copper layer. SingleBondingi R represents the thermal resistance of a single copper busbar. cij_upk R represents the coupling thermal resistance between the copper busbar connecting chip i and the copper busbar connecting chip j and the contact point with the DBC, and R cij_upk =R cij_up ;

[0067] Next, use the following formula to estimate the temperature at the contact point between the copper busbar and the bottom DBC:

[0068]

[0069] Among them, (x cpi ,y cpi (x) represents the center coordinates of the copper busbar connected to chip i and the bottom DBC solder joint. cj ,y cj ) represents distance (x) cpi ,y cpi The center coordinates of the nearest chip j, L chip and W chip T represents the length and width of the chip. DownPathi This indicates the temperature of chip i calculated by the thermal model of the bottom DBC heat transfer channel;

[0070] T RD The average temperature at the contact point between the copper busbars connected to all chips in parallel with chip i at the bottom DBC and the bottom DBC is calculated using the following formula:

[0071]

[0072] Therefore, the heat loss P conducted by the copper busbars of all chips connected in parallel with chip i from the bottom DBC to the top DBC can be calculated. Ex for:

[0073] P Ex =(T RD -T LU ) / R CuP

[0074]

[0075] Among them, R SingleBondingPi R represents the thermal resistance of a single copper busbar. cij_upP This represents the coupling thermal resistance between the copper busbar connecting chip i and the copper busbar connecting chip j at the contact point with the DBC, and R cij_upP =R cij_up .

[0076] Furthermore, in step S8, considering the heat transferred from the bottom DBC to the top DBC via the copper busbar, the temperature at the contact point between the top DBC and the copper busbar is first estimated using the following formula:

[0077]

[0078]

[0079] Among them, T LU The estimated average temperature at the contact points between the top DBC and all copper busbars, where i and j represent the chips connected to the top DBC, and N... i T represents the number of chips connected to the top DBC copper layer to which chip i is connected. UpPathiP represents the temperature of chip i calculated by the thermal model of the top heat transfer channel. Ui R represents the heat transferred by chip i through the top heat transfer channel. Cu R represents the equivalent thermal resistance of the copper busbars of all chips on this copper layer. SingleBondingi R represents the thermal resistance of a single copper busbar. cij_upk R represents the coupling thermal resistance between the copper busbar connecting chip i and the copper busbar connecting chip j and the contact point with the DBC, and R cij_upk =R cij_up ;

[0080] Next, use the following formula to estimate the temperature at the contact point between the copper busbar and the bottom DBC:

[0081]

[0082] Among them, (x cpi ,y cpi (x) represents the center coordinates of the copper busbar connected to chip i and the bottom DBC solder joint. cj ,y cj ) represents distance (x) cpi ,y cpi The center coordinates of the nearest chip j, L chip and W chip T represents the length and width of the chip. DownPathi This indicates the temperature of chip i calculated by the thermal model of the bottom DBC heat transfer channel;

[0083] T RD The average temperature at the contact point between the copper busbars connected to all chips in parallel with chip i at the bottom DBC and the bottom DBC is calculated using the following formula:

[0084]

[0085] Therefore, the heat loss P conducted by the copper busbars of all chips connected in parallel with chip i from the bottom DBC to the top DBC can be calculated. Ex for:

[0086] P Ex =(T RD -T LU ) / R CuP

[0087]

[0088] Among them, R SingleBondingPi R represents the thermal resistance of a single copper busbar. cij_upP This represents the coupling thermal resistance between the copper busbar connecting chip i and the copper busbar connecting chip j at the contact point with the DBC, and R cij_upP =R cij_up .

[0089] Further, in step S9, based on the heat loss transferred from the bottom DBC to the top DBC via the copper busbar calculated in S8, and considering heat transfer between the two DBCs via the copper busbar, the temperature rise of each chip is calculated using both the bottom heat transfer channel thermal model and the top heat transfer channel thermal model. The corrected formula for calculating the junction temperature of the bottom heat transfer channel is as follows, and the top heat transfer channel is modified similarly to calculate T'. UpPathi :

[0090]

[0091] In the formula, P * ExGi This indicates the heat transferred from the bottom DBC copper layer Gi, where chip i is located, to the top DBC via the copper busbar;

[0092] Compare the calculation results of the two models. If the error is less than the threshold, output the chip temperature rise calculated by the bottom heat transfer channel thermal model, and the value of heat transferred from the chip to the top DBC and bottom DBC. Otherwise, adjust the ratio of heat transferred from the chip to the top DBC and bottom DBC, and continue with steps S5, S7, S8, and S9. The adjustment process is as follows, taking any chip i as an example:

[0093] E i =T′ UpPathi -T′ DownPathi

[0094]

[0095]

[0096] Among them, P Ui n and P Di n ζ represents the heat loss transferred from chip i to the top DBC and bottom DBC heat transfer channels during the nth iteration, respectively, and ζ represents the iteration speed, ranging from 0.1 to 0.3.

[0097] Compared with the prior art, the present invention has the following beneficial technical effects:

[0098] This invention uses a diffusion-based thermal resistance method. First, COMSOL is used to simulate the heat flow and temperature distribution under a simple layout. Then, considering the thermal coupling effect, edge effect, and the unique heat transfer path brought about by the packaging structure, a rapid thermal modeling method is established. Unlike other methods, this method requires less computation, has a fast calculation speed, and is highly adaptable to module structures. It is suitable for rapid thermal modeling in the design stage of double-sided heat dissipation planar interconnect module. Attached Figure Description

[0099] Figure 1This is a diagram showing the packaging structure of a double-sided heat dissipation planar interconnect module;

[0100] Figure 2 The diagrams show two copper busbar shapes, where (a) is the first copper busbar shape and (b) is the second copper busbar shape.

[0101] Figure 3 This is a schematic diagram of chip labeling and DBC layout;

[0102] Figure 4 This is a finite element simulation example diagram when the area of ​​the upper copper layer in S2 is maximized;

[0103] Figure 5 Example diagram of finite element simulation in S6;

[0104] Figure 6 This is a diagram showing the heat transfer path from the bottom DBC to the copper busbar and then to the top DBC.

[0105] Figure 7 A flowchart for establishing the thermal model of this double-sided heat dissipation planar interconnect module. Detailed Implementation

[0106] To explain the invention in more detail, the following will be illustrated with reference to the accompanying drawings. Figure 1 The invention will be further described in detail using the double-sided heat dissipation planar interconnect module shown as an example.

[0107] The thermal modeling method for double-sided heat dissipation planar interconnect modules based on diffusion thermal resistance proposed in this invention includes the following steps:

[0108] S1: Given the thickness of each layer of the planar interconnect module DBC, chip model, interconnect structure, solder layer type and thickness, ambient temperature, convective heat transfer coefficient, and given the structure of the module, the loss of each chip, and the initial value of the heat loss transferred from the chip to the top DBC and bottom DBC.

[0109] S2: In COMSOL, model the bottom DBC, the chip, and the corresponding solder layer. The model only considers the bottom DBC and one chip, with the chip located at the center of the DBC. Assign a power loss of 50W to the chip and simulate to obtain the average chip temperature and average copper layer temperature for different areas of the copper layer on the DBC. Simulate to obtain the vertical heat flux distribution and temperature rise distribution on the lower surface of the upper copper layer when the copper layer area on the bottom DBC is the largest.

[0110] S3: Based on the module's structure, obtain the copper layer where the chip is located. Based on the size of the copper layer and the results in S2, obtain the corresponding average temperature rise of the chip and the average temperature rise of the copper layer.

[0111] S4: Considering the thermal coupling effect and edge effect between chips, and combining the results obtained in S2, calculate the temperature rise of chips on the same DBC copper layer due to thermal coupling and edge effect.

[0112] S5: Based on the heat flux distribution and average temperature information obtained in S2, obtain the temperature rise of another copper layer and the chip on another copper layer caused by the heat loss of the chip on the same copper layer in the bottom DBC. Combine the calculation results of S3 and S4 to complete the thermal model of the bottom heat transfer channel.

[0113] S6: In COMSOL, model the top DBC, chip, copper busbar, and the solder layer used to connect the three. The model only considers the DBC, one chip, and copper busbar, with the chip center located at the center of the DBC. The chip is connected to the top DBC through the copper busbar and solder layer. Simulate to obtain the average temperature of the chip and the vertical heat flux when the copper layer area is at its maximum when the copper layer under the top DBC is of different sizes. The chip loss is set to 20W in the simulation.

[0114] S7: Considering the thermal coupling effect and edge effect between the copper layers under the top DBC, and based on the average temperature and heat flux information calculated in S6, calculate the temperature rise of the chip on the same DBC copper layer due to the thermal coupling effect and edge effect of the copper layers under the top DBC, and complete the thermal model of the top heat transfer channel.

[0115] S8: Considering the phenomenon of heat transfer from the bottom DBC to the top DBC via the copper busbar, estimate the average temperature at the connection between the copper busbar and the bottom DBC based on the heat flux distribution obtained in S2. Estimate the average temperature at the connection between the copper busbar and the top DBC based on the thermal resistance of the copper busbar and the heat transferred from the chip to the top DBC through the copper busbar. Calculate the heat loss transferred from the bottom DBC to the top DBC via the copper busbar based on the thermal resistance of the copper busbar.

[0116] S9: The bottom heat transfer channel thermal model established in S5, the top heat transfer channel thermal model established in S7, and the supplementary model in S8 together form the thermal model of the double-sided heat dissipation planar interconnect module. By giving various parameters of the interconnect module, the temperature rise and heat transfer loss of each chip can be obtained. The specific process is as follows: According to S8, the heat loss transferred from the bottom DBC through the copper busbar to the top DBC is calculated. Considering the heat transfer from the copper busbar between the two DBCs, the temperature rise of each chip is calculated using the bottom heat transfer channel thermal model and the top heat transfer channel thermal model respectively. The calculation results of the two models are compared. If the error is less than a certain level, the chip temperature rise calculated by the bottom heat transfer channel thermal model and the value of heat transferred from the chip to the top and bottom DBCs are output. Otherwise, the ratio of heat transferred from the chip to the top and bottom DBCs is iteratively adjusted and re-substituted into the model for calculation.

[0117] In step S1, the module, from top to bottom, includes a DBC, a copper busbar, a chip, and another DBC, with any two connected by solder, such as... Figure 1 As shown, this module is a half-bridge module with a DBC size of 48mm*38mm. The heat transfer coefficient of both the upper and lower heat transfer surfaces is h = 10000W / (m²). 2. K), the ambient temperature was set to 25℃, the solder was SAC305, the thickness was 50μm, the chip used was Cree CPM3-1200-0013A, the DBC copper layer and ceramic layer thickness were 0.3mm and 0.68mm respectively, and two different shapes of copper busbars appeared in this module as follows Figure 2 As shown, the length of the section where the copper busbar is bent at both ends and directly connected to the DBC via solder does not significantly affect its thermal conductivity. Therefore, copper busbars of different lengths at this location are considered to be of the same shape. Each bridge arm has three chips, and the chip labels and DBC layout are as follows. Figure 3 As shown, assume the chip's heat loss is P. All =[P All1 ,P All2 ,P All3 ,P All4 ,P All5 ,P All6 The heat loss dissipated through the bottom heat transfer channel is P. D =[P D1 ,P D2 ,P D3 ,P LD4 ,P LD5 ,P LD6 The heat loss through the top heat transfer channel is P. U =[P U1 ,P U2 ,P U3 ,P U4 ,P U5 ,P U6 Assume that the initial heat loss ratios of the chip dissipating heat to the top and bottom heat transfer channels are 75% and 25%, respectively.

[0118] In step S2, the chip is located at the center of the DBC, and a power loss of 50W is applied to the chip. The copper layer on the DBC is kept at the center of the DBC, so that the length of the copper layer varies from its longest length to the chip length, and the width varies from its widest width to the chip width. The average temperature of the chip and the average temperature of the copper layer are simulated, and the vertical heat flux distribution F(x,y) and temperature rise distribution θ on the lower surface of the copper layer are obtained by simulation when the area of ​​the copper layer on the DBC is maximized. spread (x,y), Figure 4 This is a simulation geometry diagram created in COMSOL when the area of ​​the upper copper layer is maximized.

[0119] In step S3, an interpolation method is used to fit the average temperature rise of the chip and the average temperature rise of the copper layer in S2, obtaining the fitting function θ of the average temperature rise of the chip and the average temperature rise of the solder layer with respect to the length and width of the copper layer. die (L Cu W Cu ) and θ trace (L Cu W Cu To calculate the average temperature rise of the chip and the average temperature rise of the copper layer, the method obtains the length and width of the largest rectangle that the copper layer containing the chip can contain. This rectangle is then used to define the copper layer containing the chip. Figure 3 As shown, the copper layer containing chips 1, 2, and 3 is denoted as trace12, and the copper layer containing chips 4, 5, and 6 is denoted as trace11, i.e., G1=G2=G3=12, G4=G5=G6=11.

[0120] In step S4, the coupling thermal resistance caused by the thermal coupling effect between chips is considered by the following formula.

[0121]

[0122] Where i and j are the chip numbers on the same copper layer.

[0123] Edge effects are considered using the following formula. Taking trace12, where chips 1, 2, and 3 are located, as an example, the heat that can be dissipated when the chip is in the center of its copper layer is:

[0124]

[0125] Where S trace12 This represents the region where trace12 is located, and also represents the area of ​​trace12. In the above formula, this region represents the amount of heat that chip i can dissipate when it is in its actual location.

[0126]

[0127] Considering edge effects, the temperature rise of chip i should be θ. die P ei / P e0 (i = 1, 2, 3)

[0128] Considering both edge effects and coupling effects, taking chip 1 as an example, the temperature rise caused by the influence of other chips on the same copper layer and its own losses can be obtained as follows (scaled proportionally with chip 1's heat loss being 50W).

[0129]

[0130] In the formula, θ testchipP represents the average chip temperature when the DBC copper layer area is at its maximum in S2. test A loss of 50W is applied to S2. The calculation method for other chips is similar.

[0131] In step S5, thermal coupling between chips on different copper layers needs to be considered. Taking chips i and m on different copper layers, if the copper layer on DBC is in its maximum state, then the temperature rise effect of chip i on its copper layer is:

[0132]

[0133] Based on the law of energy conservation, the correction coefficient for the influence of chip i on the copper layers outside its copper layer can be obtained as follows:

[0134]

[0135] Where, ΔT isolation S represents the average temperature rise on the upper surface of the DBC insulating layer when a 50W loss is applied to the chip in S2. isolation θ represents the area of ​​the upper surface of the DBC insulation layer. traceGi S represents the average temperature rise of the copper layer containing chip i, obtained in S3. traceGi This represents the area of ​​the copper layer where chip i is located.

[0136] Therefore, the effect of chip i on the temperature rise of the copper layer where chip m is located can be obtained as follows:

[0137]

[0138] Similarly, the effect of chip i on the temperature rise of chip m can also be obtained as follows:

[0139]

[0140] Taking chip 1 as an example, the influence of other chips (chips 4, 5, 6) that are not on the same copper layer as chip 1 on the temperature rise of chip 1 can be obtained as follows (scaled proportionally based on a heat loss of 50W for chip 1).

[0141]

[0142] Therefore, the temperature rise of chip 1 due to the heat loss of all chips is...

[0143] θ die1_all =θ die1_same +θ die1_diff

[0144] Taking chip 1 as an example, the temperature rise of the copper layer trace12 where chip 1 is located due to the heat loss of all chips is (scaled proportionally based on the heat loss of chip 1 being 50W).

[0145]

[0146] Therefore, the sum of the one-dimensional thermal resistance and diffusion thermal resistance from chip 1 to its copper layer can be calculated as follows:

[0147]

[0148] The diffusion thermal resistance between the copper layer containing chip 1 and the ceramic substrate is (scaled proportionally based on the sum of the heat losses of chips 1, 2, and 3 being 150W).

[0149]

[0150] Finally, the temperature rise of chip 1 can be calculated using the following formula, and the same applies to other chips.

[0151]

[0152] At this point, the thermal model of the bottom heat transfer channel has been established.

[0153] In step S6, the top DBC, chip, copper busbar, and solder layers used for connection between the three are modeled in COMSOL. The model only considers the DBC, with the chip located at the center of the DBC. The chip is assigned a P... test2 =20W loss, control the top DBC copper layer to have only one copper layer, and vary its length from its longest length to the length required to fully contact the copper busbar connected to the chip in the longitudinal direction, and its width from its widest length to the length required to fully contact the copper busbar connected to the chip in the width direction, for example. Figure 5 As shown. The average temperature of the simulated chip is recorded, and the vertical heat flux distribution F on the upper surface of the DBC copper layer is recorded when the area of ​​the upper copper layer is at its maximum. up Temperature distribution θ on the upper surface of the DBC copper layer up If the copper busbar has different shapes, then each shape needs to be simulated.

[0154] In step S7, considering the thermal coupling effect between chips connected to the copper layer under the same top DBC via copper busbars, the solder layer at the connection point between the copper busbar and the top DBC for chip i,j is denoted as Solderi_up, with the center position being (x ciup y ciup The center position is defined as the geometric center of the chip, Solderi_up represents all the solder layers connecting the copper busbar corresponding to chip i to the top DBC, and the coupling thermal resistance R is... cij_up (j and i are connected on the same top DBC copper layer) The calculation is as follows:

[0155]

[0156] Among them, S solderj_upThe area under the integral sign represents the region where the weld layer is located; otherwise, it represents the area of ​​this region.

[0157] The chip temperature calculation method simply requires replacing the chip's one-dimensional thermal resistance with the thermal resistance shared by the chip and the copper busbar, thus completing the thermal model of the top heat transfer channel.

[0158] In step S8, consider the heat transferred from the bottom DBC to the top DBC via the copper busbar. The heat transfer path is as follows: Figure 6 As shown (only chips 1 and 4 and their copper busbars are displayed), this phenomenon occurs on the copper busbars corresponding to chips 1, 2, and 3 in this layout. Therefore, the temperature at the contact point between the top DBC and the copper busbar can be estimated using the following formula.

[0159]

[0160]

[0161] Among them, T LU The estimated average temperature at the contact points between the top DBC and all copper busbars is given by T, where i and j represent the chips connected to the top DBC. UpPathi P represents the temperature of chip i calculated by the thermal model of the top heat transfer channel. Ui This represents the heat transferred from chip i through the top heat transfer channel. R Cup R represents the equivalent thermal resistance of the copper busbars of all chips on this copper layer. SingleBondingi This represents the thermal resistance of a single copper busbar, which is 5.20 K / W in this example. cij_upk This represents the coupling thermal resistance between the copper busbar connected to chip i and the copper busbar connected to chip j. In this scheme, R is considered to be... cij_upk =R cij_up .

[0162] Next, use the following formula to estimate the temperature at the contact point between the copper busbar and the bottom DBC.

[0163]

[0164] Among them, (x cpi ,y cpi (x) represents the center coordinates of the copper busbar connected to chip i and the bottom DBC solder joint. cj ,y cj ) represents distance (x) cpi ,y cpi The coordinates of the nearest chip j. chip and W chip This indicates the length and width of the chip. For example... Figure 1 As shown, in this module, the chips closest to the copper busbars connected to chips 1, 2, and 3 and the bottom DBC solder joint are chips 4, 5, and 6, respectively.

[0165] TRD This represents the average temperature at the contact point between the copper busbars connected to all chips in parallel with chip i at the bottom DBC and the bottom DBC. It is calculated using the following formula.

[0166]

[0167] Therefore, the heat loss P conducted by the copper busbars of all chips connected in parallel with chip i (i = 1, 2, 3) from the bottom DBC to the top DBC can be calculated. Ex for

[0168] P Ex =(T RD -T LU ) / R CuP

[0169] R CuP =(3R) SingleBondingP +2R c21_dbc2 +2R c32_dbc2 +2R c31_dbc2 ) / 9

[0170] Among them, R singleBondingP The thermal resistance of the copper busbar in transferring heat from the bottom DBC to the top DBC heat transfer channel is 5.489 K / W.

[0171] In step S9, based on the heat loss calculated in S8 from the bottom DBC to the top DBC via the copper busbar, and considering heat transfer between the two DBCs via the copper busbar, the temperature rise of each chip is calculated using both the bottom heat transfer channel thermal model and the top heat transfer channel thermal model. The corrected formula for calculating the junction temperature of the bottom heat transfer channel is as follows. The top heat transfer channel is modified similarly, and T' is calculated. UpPathi .

[0172]

[0173] In the formula, P * ExGi This represents the heat transferred from the bottom DBC copper layer of chip i to the top DBC via the copper busbar. For this module, for chips 1, 2, and 3, there is no copper busbar directly transferring heat from trace12 to the top DBC; therefore, P... * ExG1 =P * ExG2 =P * ExG3 =0.

[0174] Compare the calculation results of the two models. If the error is less than a certain level, output the chip temperature rise calculated by the bottom heat transfer channel thermal model, and the value of heat transferred from the chip to the top DBC and bottom DBC. Otherwise, adjust the ratio of heat transferred from the chip to the top DBC and bottom DBC, and continue with steps S5, S7, S8, and S9. The adjustment process is as follows, taking any chip i as an example.

[0175] E i =T′ UpPathi -T′ DownPathi

[0176]

[0177]

[0178] P Ui n and P Di n ζ represents the heat loss transferred from chip i to the top DBC and bottom DBC heat transfer channels during the nth iteration, respectively, and ζ represents the iteration speed, which is taken as 1 / 7 in this paper.

[0179] After completing the thermal modeling, assign a chip loss P. All = [86.275W, 82.9848W, 88.3108W, 98.4435W, 96.1152W, 97.9825W]. Table 1 shows a comparison between the junction temperature calculated by this method and the average junction temperature obtained from the finite element software COMSOL simulation.

[0180] Table 1 Comparison of the average temperature rise calculation results of the method of the present invention and the finite element software chip.

[0181] T1 T2 T3 T4 T5 T6 Method of the present invention / ℃ 79.30175 86.89603 80.88781 93.12482 101.6685 93.45487 Finite element software / ℃ 76.787 84.319 78.635 90.73 98.792 89.616 error 3.27％ 3.06％ 2.86％ 2.64％ 2.91％ 4.28％

[0182] The finite element software takes 10 seconds to complete, while the modeling method of this invention takes about 0.25 seconds. The iterative calculation process generally requires 2-4 iterations for electrothermal co-simulation. The method proposed in this invention can significantly reduce the time required for electrothermal co-simulation while ensuring a certain level of accuracy (5%).

[0183] The above description, in conjunction with specific examples, provides a more detailed explanation of the specific embodiments of the present invention. All descriptions are illustrative and should not be construed as limiting the scope of the invention. The scope of protection of the present invention is defined by the appended claims, and any modifications based on the claims constitute the scope of protection of the present invention.

Claims

1. A thermal modeling method for a double-sided heat dissipation planar interconnect module based on diffusion thermal resistance, characterized in that, Includes the following steps; S1: Set the thickness of each layer of the planar interconnect module DBC, chip model, interconnect structure, solder layer type and thickness, set the ambient temperature and convective heat transfer coefficient, set the structure of the module, set the loss of each chip, and set the initial value of heat loss transferred from the chip to the top DBC and bottom DBC. S2: In COMSOL, model the bottom DBC, chip and corresponding solder layer of the chip. The model only considers the bottom DBC and one chip, and the chip is located in the center of the DBC. Assign a set value to the chip and simulate to obtain the average chip temperature and average copper layer temperature when the copper layer on the DBC has different areas, as well as the vertical heat flux distribution and temperature rise distribution of the lower surface of the upper copper layer when the copper layer area on the bottom DBC is the largest. S3: Based on the module's structure, obtain the copper layer where the chip is located. Based on the size of the copper layer and the results in S2, obtain the corresponding average temperature rise of the chip and the average temperature rise of the copper layer. S4: Considering the thermal coupling effect and edge effect between chips, and combining the results obtained in S2, calculate the temperature rise of chips on the same DBC copper layer due to thermal coupling and edge effect; S5: Based on the heat flux distribution and average temperature information obtained in S2, obtain the temperature rise of another copper layer and the chip on another copper layer caused by the heat loss of the chip on the same copper layer in the bottom DBC. Combine the calculation results of S3 and S4 to complete the thermal model of the bottom heat transfer channel. S6: In COMSOL, model the top DBC, chip, copper busbar, and the solder layer used to connect the three. The model only considers the DBC, one chip, and copper busbar, with the chip center located at the center of the DBC. The chip is connected to the top DBC through the copper busbar and solder layer. Simulate to obtain the average temperature of the chip and the vertical heat flux when the copper layer area is at its maximum when the copper layer under the top DBC is of different sizes. S7: Consider the thermal coupling effect and edge effect between the copper layers under the top DBC, and calculate the temperature rise of the chip on the same DBC copper layer due to the thermal coupling effect and edge effect of the copper layers under the top DBC based on the average temperature and heat flux information calculated in S6, and complete the thermal model of the top heat transfer channel. S8: Considering the phenomenon of heat transfer from the bottom DBC to the top DBC via the copper busbar, estimate the average temperature at the connection between the copper busbar and the bottom DBC based on the heat flux distribution obtained in S2. Estimate the average temperature at the connection between the copper busbar and the top DBC based on the thermal resistance of the copper busbar and the heat transferred from the chip to the top DBC through the copper busbar. Calculate the heat loss transferred from the bottom DBC to the top DBC via the copper busbar based on the thermal resistance of the copper busbar. S9: The bottom heat transfer channel thermal model established in S5, the top heat transfer channel thermal model established in S7, and the supplementary model in S8 together form the double-sided heat dissipation planar interconnect module thermal model. By giving various parameters of the interconnect module, the temperature rise and heat transfer of each chip can be obtained. The specific process is as follows: Based on the heat loss from the bottom DBC to the top DBC calculated in S8, considering the heat transfer from the copper busbar between the two DBCs, the temperature rise of each chip is calculated using the bottom heat transfer channel thermal model and the top heat transfer channel thermal model respectively. The calculation results of the two models are compared. If the error is less than the set value, the chip temperature rise calculated by the bottom heat transfer channel thermal model and the value of heat transferred from the chip to the top DBC and the bottom DBC are output, and the modeling is completed. Otherwise, iteratively adjust the ratio of heat transfer from the chip to the top DBC and bottom DBC, and resubmit the values ​​into the model for calculation.

2. The thermal modeling method for a double-sided heat dissipation planar interconnect module based on diffusion thermal resistance according to claim 1, characterized in that, In step S2, the chip is located at the center of the DBC in the established model, and the chip is given... P test With a power loss of 50W, the copper layer on the DBC is kept at the center of the DBC, and the length of the copper layer varies from its longest length to the chip length, and the width varies from its widest width to the chip width. The average temperature of the chip and the average temperature of the copper layer are simulated, and the vertical heat flux distribution on the lower surface of the copper layer is obtained when the copper layer area is maximized. F ( x , y ) and temperature rise distribution θ spread ( x , y ),in x , y This represents the coordinates of a point on the copper layer with the chip center as the origin.

3. The thermal modeling method for a double-sided heat dissipation planar interconnect module based on diffusion thermal resistance according to claim 2, characterized in that, In step S3, an interpolation method is used to fit the average temperature rise of the chip and the average temperature rise of the copper layer in S2, obtaining fitting functions of the average temperature rise of the chip and the average temperature rise of the solder layer with respect to the length and width of the copper layer. θ die ( L Cu , W Cu )and θ trace ( L Cu , W Cu ),in θ die Indicates the average temperature rise of the chip. θ trace Indicates the average temperature rise of the weld layer. L Cu The length of the copper layer. W Cu Given the copper layer width, obtain the length and width of the largest rectangle that the copper layer containing the chip can contain. Substitute these values ​​into the fitting function to calculate the average temperature rise of the chip and the average temperature rise of the copper layer. Then, apply the chip... i The largest rectangular copper layer that can be contained within the copper layers connected by solder layers is called a chip. i The copper layer in question is denoted as Gi .

4. The thermal modeling method for a double-sided heat dissipation planar interconnect module based on diffusion thermal resistance according to claim 3, characterized in that, In step S4, the coupling thermal resistance caused by the thermal coupling effect between chips is considered by the following formula: in i , j The numbering of chips on the same copper layer. R ij Indicates chip j For chips i The coupling thermal resistance, θ spread This represents the temperature rise distribution on the lower surface of the copper layer on the DBC. x cj , y cj Indicates chip j The center coordinates, S cj When indicated by an integral sign, it is represented as a chip. j The location is indicated by the chip; other cases indicate the chip. j The area; Edge effects are considered using the following formula: the heat diffused when the chip is in the center of the copper layer is: chip i The heat dissipated at the actual location is: in, S traceGi Indicates chip i The area where the copper layer is located, x ci , y ci Indicates chip i If the center coordinates are considered, then edge effects should be taken into account for the chip. i The temperature rise is ,in θ die This indicates the average temperature rise of the chip, which is calculated based on the size of the copper layer on which the chip is located. Simultaneously considering edge effects and coupling effects, according to chip i The heat loss is scaled proportionally to 50W to obtain the chip. i The temperature rise caused by the wear and tear of other chips on the same copper layer and its own losses is as follows: In the formula, θ testchip This represents the average chip temperature when the DBC copper layer area is at its maximum in S2. P ei and P ej chips i and j The power consumption of diffusion, R ji Indicates chip i For chips j The coupling thermal resistance, θ die_i and θ die_j According to the chip i and j The function calculated based on the size of the copper layer. θ die ( L Cu , W Cu The value of ) P test Apply loss to S2, P Dj and P Di chips i , j Losses transferred from the bottom heat transfer channel.

5. The thermal modeling method for a double-sided heat dissipation planar interconnect module based on diffusion thermal resistance according to claim 4, characterized in that, In step S5, considering the thermal coupling between chips on different copper layers, chips on different copper layers are selected. i and m If the copper layer on the DBC is in its maximum state, then the chip i Regarding its copper layer G i The temperature rise in that region has the following impact: Based on the law of conservation of energy, the chip is obtained. i The correction factor that affects the copper layers other than the copper layer is: Where, Δ T isolation This represents the average temperature rise on the upper surface of the DBC insulating layer when a set loss is applied to the chip in S2. S isolation This represents the area of ​​the upper surface of the DBC insulation layer. θ traceGi This indicates the chip obtained in S3. i The average temperature rise of the copper layer is as follows. S traceGi Indicates chip i The area of ​​the copper layer in question; Therefore, the effect of chip i on the temperature rise of the copper layer where chip m is located is as follows: Similarly, to obtain the chip i For chips m The effects of temperature rise are: By chip i The heat loss is scaled proportionally to 50W to obtain the chip i Other chips not on the same copper layer i The effects of temperature rise are: in P Dm For chips m Heat loss due to heat transfer from the bottom heat transfer channel; This yields the chip. i The temperature rise caused by the heat loss of all chips is: By chip i The heat loss is scaled proportionally to 50W. The temperature rise of the copper layer containing chip i due to the heat loss of all chips is: in, j Indicates and i All chips on the same copper layer, including i ; m Display and chip i Chips on different copper layers; Therefore, the chip is calculated. i The sum of the one-dimensional thermal resistance and the diffusion thermal resistance of the copper layer to which it is located is: By chip i On the copper layer N i The sum of the heat losses of each chip is N i P test Proportional scaling, chip i The diffusion thermal resistance between the copper layer and the ceramic substrate is: in, N i Indicates chip i The number of chips on the copper layer j Indicates and i All chips on the same copper layer, including i ; m Display and chip i Chips on different copper layers; Finally, the chip i The temperature rise is calculated using the following formula; the same applies to other chips. in, R residue This represents the one-dimensional equivalent thermal resistance of the bottom DBC ceramic layer, the lower copper layer, and the heat convection process. At this point, the thermal model of the bottom heat transfer channel has been established.

6. A thermal modeling method for a double-sided heat dissipation planar interconnect module based on diffusion thermal resistance according to claim 1, characterized in that, In step S6, the chip is located at the center of the DBC, and a power loss of 20W is applied to the chip. The copper layer under the top DBC is controlled to consist of only one copper layer. The length of this layer is varied from its longest length to the length required to fully contact the copper busbar connected to the chip in the longitudinal direction, and the width is varied from its widest length to the length required to fully contact the copper busbar connected to the chip in the width direction. The average chip temperature is simulated, and the vertical heat flux distribution on the upper surface of the copper layer of the top DBC is recorded when the area of ​​the upper copper layer is at its maximum. F up Temperature distribution on the upper surface of the DBC copper layer θ up If the copper busbar has different shapes, then each shape will be simulated.

7. The thermal modeling method for a double-sided heat dissipation planar interconnect module based on diffusion thermal resistance according to claim 1, characterized in that, In step S7, the thermal coupling effect on the copper layer under the top DBC is considered to connect the chip... i The solder layer corresponding to the connection between the copper busbar and the top DBC is denoted as Solder. i _up, the center position is ( x ciup y ciup The center position is defined as the geometric center of the chip, Solder. i _up is the chip i For all solder layers corresponding to the connection between the copper busbar and the top DBC, the coupling thermal resistance R cij_up , j and i Connected to the same top DBC under the copper layer, the calculation is as follows: in, S solderj_up The area under the integral sign represents the region where the weld layer is located; otherwise, it represents the area of ​​this region. When calculating the chip temperature, simply replace the chip's one-dimensional thermal resistance with the thermal resistance shared by the chip and the copper busbar. The rest is the same as the thermal model of the bottom heat transfer channel, thus completing the thermal model of the top heat transfer channel.

8. The thermal modeling method for a double-sided heat dissipation planar interconnect module based on diffusion thermal resistance according to claim 7, characterized in that, In step S8, considering the heat transferred from the bottom DBC to the top DBC via the copper busbar, the temperature at the contact point between the top DBC and the copper busbar is first estimated using the following formula: in, T LU This is the estimated average temperature at the contact points between the top DBC and all copper busbars. i , j Both indicate the chip connected to the top DBC. N i Indicates chip i The number of chips connected to the top DBC copper layer. T UpPathi This indicates the chip calculated by the top heat transfer channel thermal model. i temperature, P Ui Indicates chip i Heat transferred through the top heat transfer channel; R Cu This represents the equivalent thermal resistance of the copper busbars of all chips on the copper layer. R SingleBondingi This indicates the thermal resistance of a single copper busbar. R cij_upk Indicates chip i Connecting copper busbars and chips j The coupling thermal resistance between the copper busbar and the DBC contact point, and R cij_upk = R cij_up ; Next, use the following formula to estimate the temperature at the contact point between the copper busbar and the bottom DBC: in,( x cpi , y cpi ) indicates chip i The center coordinates of the connection between the copper busbar and the bottom DBC are ( x cj , y cj ) represents distance ( x cpi , y cpi Recent chips j The center coordinates, L chip and W chip Indicates the length and width of the chip. T DownPathi This indicates the chip calculated using the bottom DBC heat transfer channel thermal model. i Temperature; T RD This indicates that the bottom DBC is related to all chips. i The average temperature at the contact point between the copper busbar connected to the parallel chips and the bottom DBC is calculated using the following formula: Therefore, all the chips are calculated. i The copper busbars of the parallel-connected chips conduct heat loss from the bottom DBC to the top DBC. P Ex for: in, R SingleBondingPi This indicates the thermal resistance of a single copper busbar. R cij_upP Indicated in chip i Connecting copper busbars and chips j The coupling thermal resistance between the copper busbar and the DBC contact point, and R cij_upP = R cij_up .

9. A thermal modeling method for a double-sided heat dissipation planar interconnect module based on diffusion thermal resistance according to claim 7, characterized in that, In step S9, based on the heat loss transferred from the bottom DBC to the top DBC via the copper busbar calculated in S8, and considering heat transfer between the two DBCs via the copper busbar, the temperature rise of each chip is calculated using both the bottom heat transfer channel thermal model and the top heat transfer channel thermal model. The corrected formula for calculating the junction temperature of the bottom heat transfer channel is as follows, and the top heat transfer channel is modified similarly to calculate T. ’ UpPathi : In the formula, P * ExGi Indicates from chip i Located at the bottom DBC copper layer G i Heat is transferred to the top DBC via the copper busbar; Compare the calculation results of the two models. If the error is less than the threshold, output the chip temperature rise calculated by the bottom heat transfer channel thermal model, and the value of heat transferred from the chip to the top DBC and bottom DBC. Otherwise, adjust the ratio of heat transferred from the chip to the top DBC and bottom DBC, and continue steps S5, S7, S8, and S9. The adjustment process is as follows, using any chip... i For example: in, P Ui n and P Di n They represent the first n Chip during the next iteration i The heat loss transferred to the heat transfer channels of the top DBC and bottom DBC, ζ represents the iteration speed, which is 0.1~0.3.

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