Pixel island, display device, and light field display device

Abstract

The present disclosure provides a pixel island, a display device, and a light field display device. The pixel island includes: a driving layer including a power pad, a data pad, a clock pad, and a chip select pad; a logic processing circuit; and a plurality of pixel circuits. The power pad is used to supply power to the logic processing circuit and the pixel circuits; the data pad is used to provide data voltages to the pixel circuits; and the logic processing circuit is used to provide gate control signals to the pixel circuits based on clock signals from the clock pad and chip select signals from the chip select pad. A plurality of sub-pixels are electrically connected to the pixel circuits in a one-to-one correspondence.

Description

Technical Field

[0001] The present disclosure belongs to the field of display technology, and particularly relates to a pixel island, a display device, and a light field display device. Background Art

[0002] This section is intended to provide a background or context to the embodiments recited in the claims. No admission is made that anything herein is prior art by virtue of its inclusion in this section.

[0003] In the prior art, a large number of LED chips are transferred to a driver backplane to create a display panel for light field display. The transfer and die bonding process is time-consuming and has a low yield, resulting in high display panel costs. Summary of the Invention

[0004] The present disclosure provides a pixel island, a display device, and a light field display device.

[0005] The present disclosure provides the following technical solutions: a pixel island, comprising:

[0006] a driving layer comprising a power pad, a data pad, a clock pad, and a chip select pad, and comprising a logic processing circuit and a plurality of pixel circuits, wherein the power pad is used to supply power to the logic processing circuit and the pixel circuit, the data pad is used to provide a data voltage to the pixel circuit, and the logic processing circuit is used to provide a gate control signal to the pixel circuit according to a clock signal of the clock pad and a chip select signal of the chip select pad;

[0007] A plurality of sub-pixels are electrically connected to the pixel circuit in a one-to-one correspondence.

[0008] In some embodiments, the logic processing circuit is configured to sequentially generate gate control signals provided to the pixel circuit under the stimulation of rising and falling edges of the clock signal provided by the clock pad during a period in which the chip select signal maintains a valid voltage.

[0009] In some embodiments, the multiple sub-pixels are divided into sub-pixels of multiple colors, sub-pixels of the same color are distributed in the same rectangular area extending along a first direction, and sub-pixels of different colors are arranged along a second direction, and the first direction and the second direction are parallel to and intersecting with the plane of the driving layer.

[0010] In some embodiments, the light emitted by the sub-pixel is collimated light.

[0011] In some embodiments, the number of the data pads is equal to the number of colors of the sub-pixels, and each data pad is used to receive a data voltage of a sub-pixel of one color.

[0012] In some embodiments, the sub-pixel comprises: an LED.

[0013] The present disclosure provides the following technical solutions: a display panel, comprising a driving backplane and a plurality of the aforementioned pixel islands, the driving backplane comprising a plurality of power lines, a plurality of chip select signal lines and clock signal lines extending along a third direction, and a plurality of data lines extending along a fourth direction, the third direction and the fourth direction being two directions parallel to and intersecting with the plane in which the display panel is located, the power line being used to provide a power supply voltage to the power pad of the pixel island, the chip select signal line being used to provide a chip select signal to the chip select pad of the pixel island, the clock signal line being used to provide a clock signal to the clock pad of the pixel island, and the data line being used to provide a data voltage to the data pad of the pixel island.

[0014] In some embodiments, in the display panel, sub-pixels of the same color are distributed in a same rectangular area extending along the third direction, and sub-pixels of different colors are periodically arranged along the fourth direction.

[0015] In some embodiments, a column of the pixel islands arranged along the fourth direction is correspondingly connected to one or more data lines.

[0016] The present disclosure provides the following technical solution: a display device, comprising: a source driver chip, a gate driver chip, and the aforementioned display panel, wherein the source driver chip is used to drive the data line, and the gate driver chip is used to drive the chip select signal line and the clock signal line.

[0017] The present disclosure provides the following technical solution: a light field display device, comprising: a source driver chip, a gate driver chip, and the aforementioned display panel, wherein the source driver chip is used to drive the data line, and the gate driver chip is used to drive the chip select signal line and the clock signal line; the light field display device also includes a lens structure arranged on the light output surface of the display panel.

[0018] In some embodiments of the present disclosure, the transfer process of a single LED chip to a display substrate is replaced by a transfer process of a pixel island to a display substrate. The workload of the transfer process is greatly reduced. Furthermore, the quality inspection of a single LED chip is replaced by the quality inspection of a pixel island, which is easier to operate due to its larger size. Furthermore, when a single sub-pixel or a pixel circuit of a single sub-pixel is defective, only one pixel island needs to be scrapped or replaced without scrapping the entire display panel. This also helps to reduce the overall manufacturing cost of the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 2 is a top view of a pixel island according to an embodiment of the present disclosure.

[0020] Figure 2 yes Figure 1 Schematic diagram of the distribution of sub-pixels in a single LED chip in the pixel island shown.

[0021] Figure 3 4 is a circuit diagram of a driving layer in a pixel island according to an embodiment of the present disclosure.

[0022] Figure 4 is a cross-sectional view of a pixel island according to an embodiment of the present disclosure.

[0023] Figure 5 Schematic diagram of the connection relationship of some structures in the display device of an embodiment of the present disclosure.

[0024] Figure 6 2 is a driving timing diagram of the pixel island according to an embodiment of the present disclosure.

[0025] Figure 7 It is a variation of the driving layer in the pixel island of the embodiment of the present disclosure.

[0026] Figure 8 Schematic diagram of the structure of the light field display device provided by the embodiment of the present disclosure.

[0027] Among them, the figure markings are: R, red LED chip; G, green LED chip; B, blue LED chip; R1 to RN, independently controlled light-emitting areas in the red LED chip; VDD, VSS, power supply voltage; RST, EM, Gate1, Gate2, GateT, gate control signals; C1, capacitor; M1 to M7, transistors; SCS, chip select signal; CLK, clock signal; Data, data voltage; DataR, red sub-pixel data voltage; DataG, green sub-pixel data voltage; DataB, blue sub-pixel data voltage; 1, base layer; 2, circuit layer; 3, sub-pixel; P1, P2, power pad; P5, data pad; P3, chip select pad; P4, clock pad; LED1, light-emitting diode; L1, data line; L2, chip select signal line; L3, clock signal line; IC1, source driver chip; IC2, gate driver chip; I, ​​pixel island; 200, lens structure. DETAILED DESCRIPTION

[0028] The present disclosure will be further described below with reference to the embodiments shown in the accompanying drawings.

[0029] Figure 1 2 is a top view of a pixel island according to an embodiment of the present disclosure. Figure 2 yes Figure 1 Schematic diagram of the distribution of sub-pixels in a single LED chip in the pixel island shown. Figure 3 4 is a circuit diagram of a driving layer in a pixel island according to an embodiment of the present disclosure. Figure 4is a cross-sectional view of a pixel island according to an embodiment of the present disclosure.

[0030] refer to Figures 1 to 4 , an embodiment of the present disclosure provides a pixel island. The pixel island independently packages or combines multiple sub-pixels, the pixel circuits of the multiple sub-pixels, and the driving circuits of the pixel circuits into an independent product. The display substrate only needs to provide power signals, chip select signals, clock signals, and data voltages to the pixel island to drive the sub-pixels in the pixel island to light up sequentially or simultaneously. The preparation process of the display panel is simplified to the connection process of the pixel island and the display substrate, which greatly reduces the workload of the transfer and die bonding process. The workload of testing the yield of the pixel island is low and the reliability of the pixel island is stable. This helps to improve the efficiency of display panel production and also helps to improve the yield of the display panel.

[0031] refer to Figure 4 The driving layer in the pixel island includes a base layer 1 and a circuit layer 2. Base layer 1 is made of semiconductor materials such as silicon and gallium arsenide, or flexible insulating materials such as polyimide. The pixel circuit and logic processing circuit are located in circuit layer 2. Sub-pixels 3 are, for example, independently controllable light-emitting areas within a single LED chip.

[0032] refer to Figure 1 A single red LED chip R has multiple independently drivable light-emitting areas, thereby forming multiple red sub-pixels. A single green LED chip G has multiple independently drivable light-emitting areas, thereby forming multiple green sub-pixels. A single blue LED chip B has multiple independently drivable light-emitting areas, thereby forming multiple blue sub-pixels.

[0033] In some other embodiments, a single LED chip includes a single independently controllable light-emitting area, that is, a single LED chip forms a sub-pixel.

[0034] Individual LED chips are fabricated on the driver layer, for example, through a transfer and die-bonding process. Pixel islands are then packaged. The pixel islands are then used to fabricate display panels. Alternatively, after transferring individual LED chips to the driver layer, the pixel islands can be directly connected to the display substrate without packaging. Specifically, bonding or welding processes can be used to electrically connect the power pads, data pads, clock pads, and chip select pads to the exposed traces on the display substrate.

[0035] It should be noted that the sub-pixels are not limited to being formed by LED chips. In other embodiments, the sub-pixels in the pixel islands may also be formed by organic light emitting diodes or quantum dot light emitting diodes.

[0036] The power pad P1 is used, for example, to receive a first power supply voltage VDD, and the power pad P2 is used, for example, to receive a second power supply voltage VSS. The first power supply voltage VDD is, for example, a positive power supply voltage, and the second power supply voltage VSS is, for example, a negative power supply voltage. The power pads P1 and P2 are used to power the logic processing circuit and the pixel circuit. The number of power pads is not limited to two. In other embodiments, the pixel circuit also requires a half voltage (the midpoint voltage between the high-level power supply voltage and the low-level power supply voltage). Accordingly, the pixel island also includes a pad for receiving the half voltage (not shown in the figure).

[0037] Data pad P5 is used to provide a data voltage to the pixel circuit. The magnitude of the data voltage directly determines the brightness of the sub-pixel driven by the pixel circuit. The logic processing circuit is used to provide gate control signals to the pixel circuit based on the clock signal on clock pad P4 and the chip select signal on chip select pad P3.

[0038] Power pads P1, P2, data pad P5, chip select pad P3, and clock pad P4 are disposed on the surface of substrate layer 1 away from circuit layer 2. Power pads P1, P2, data pad P5, chip select pad P3, and clock pad P4 are electrically connected to circuit layer 2, for example, via vias penetrating substrate layer 1. In these embodiments, the light emission direction of the sub-pixel is, for example, from substrate layer 1 to circuit layer 2.

[0039] In other embodiments, power pads P1, P2, data pads P5, chip select pads P3, and clock pads P4 are disposed on the surface of the circuit layer 2 away from the base layer 1. Power pads P1, P2, data pads P5, chip select pads P3, and clock pads P4 extend beyond the sub-pixel 3, for example, in a direction from the base layer 1 to the circuit layer 2. In these embodiments, the light emission direction of the sub-pixel 3 is, for example, in a direction from the circuit layer 2 to the base layer 1.

[0040] The present disclosure does not limit how to specifically package the sub-pixels and the driving layer and the mechanical structure design of the power pad, data pad, clock pad, and chip select pad.

[0041] The plurality of sub-pixels in the pixel island are electrically connected to the pixel circuits in a one-to-one correspondence.

[0042] Figure 3The figure shows two pixel circuits in a pixel island. The pixel circuit includes seven P-type transistors M1 to M7, a capacitor C1, and a light-emitting diode LED1. Capacitor C1 has two terminals that receive a power supply voltage and are connected to the gate of transistor M1. The gate of transistor M3 receives a gate control signal EM, the first terminal of transistor M3 receives a power supply voltage VDD, and the second terminal of transistor M3 is connected to transistor M7 and the first terminal of transistor M1. The second terminal of transistor M7 receives a data voltage Data, and the gate of transistor M7 receives gate control signals Gate1 and Gate2. The second terminal of transistor M1 is connected to the first terminal of transistor M2 and the first terminal of transistor M7. The second terminal of transistor M2 is connected to the gate of transistor M1, and the gate of transistor M2 receives gate control signals Gate1 and Gate2. The gate of transistor M4 receives a gate control signal EM, the second terminal of transistor M4 is connected to the anode of light-emitting diode LED1, and the cathode of light-emitting diode LED1 receives a power supply voltage VSS. The gates of transistor M5 and transistor M6 both receive a gate control signal RST, and the first terminals of transistors M5 and M6 both receive a power supply voltage VSS. The second electrode of the transistor M5 is connected to the gate of the transistor M1. The second electrode of the transistor M6 is connected to the anode of the light emitting diode LED1.

[0043] observe Figure 3 In the pixel circuit on the left, when the gate control signal RST is low, the power supply voltage VSS is written to one end of capacitor C1 (i.e., the gate of transistor M1), and transistor M6 turns on, resetting the anode voltage of light-emitting diode LED1. When the gate control signal Gate1 is low, the corresponding transistor M7 turns on, and the data voltage is written to the gate of transistor M1 after threshold compensation. When the gate control signal EM is low, transistors M3 and M4 turn on, and the gate voltage of transistor M1 controls the current of light-emitting diode LED1, thereby controlling the brightness of light-emitting diode LED1.

[0044] observe Figure 3 In the pixel circuit on the right, when the gate control signal RST is low, the power supply voltage VSS is written to one end of capacitor C1 (i.e., the gate of transistor M1), and transistor M6 turns on, resetting the anode voltage of light-emitting diode LED2. When the gate control signal Gate2 is low, the corresponding transistor M7 turns on, and the data voltage is written to the gate of transistor M1 after threshold compensation. When the gate control signal EM is low, transistors M3 and M4 turn on, and the gate voltage of transistor M1 controls the current of light-emitting diode LED1, thereby controlling the brightness of light-emitting diode LED2.

[0045] The transistors in the above pixel circuits are all P-type transistors, and the effective voltage of their gate voltages is a low level voltage. In other embodiments, the transistors in the pixel circuits are all N-type transistors, and the effective voltage of their gate voltages is a high level voltage.

[0046] The logic processing circuit provides a gate control signal to each pixel circuit, so that each pixel circuit receives the data voltage Data in sequence.

[0047] In some embodiments, the logic processing circuit is configured to sequentially generate gate control signals provided to the pixel circuit under the stimulation of rising and falling edges of a clock signal provided by a clock pad during a period in which the chip select signal maintains a valid voltage.

[0048] In other words, when the chip select signal maintains a valid voltage, each edge of the clock signal triggers an edge of the gate control signal. In this way, the clock signal edge information is fully utilized and the clock signal frequency can be appropriately lowered.

[0049] In other embodiments, the logic processing circuit is configured to sequentially generate gate control signals for the pixel circuits in response to the rising edge of a clock signal provided by a clock pad during a period in which the chip select signal maintains an active voltage. The frequency of the clock signal is appropriately increased to shorten the time required to write data to all sub-pixels in a pixel island.

[0050] The logic processing circuit is configured to sequentially generate gate control signals for the pixel circuits in response to the falling edge of the clock signal provided by the clock pad while the chip select signal maintains an active voltage. The clock signal frequency needs to be appropriately increased to shorten the data writing time for all sub-pixels in the pixel island.

[0051] Figure 6 : is a driving timing diagram of the pixel island of the embodiment of the present disclosure. Figure 3 and Figure 6 In an exemplary embodiment, the operation timing of the logic processing circuit is as follows.

[0052] The high voltage of the chip select signal SCS is the active voltage. During the high voltage period of the chip select signal, the data voltage required by each sub-pixel in the pixel island is sequentially written to each sub-pixel. During the low voltage period of the chip select signal SCS, each sub-pixel remains illuminated. The detailed operating timing is as follows.

[0053] At the first rising edge of the clock signal CLK after the rising edge of the chip select signal SCS, the voltage of the gate control signal EM provided to each pixel circuit in the pixel island is set to a high level voltage. The transistors M3 and M4 in all pixel circuits in the pixel island are in the off state.

[0054] At the subsequent falling edge of the clock signal CLK, the voltage of the gate control signal RST provided to each pixel circuit in the pixel island is set to a low level voltage. The gate voltage of the transistor M1 and the anode voltage of the light-emitting diodes LED1, LED2, etc. in all the pixel circuits in the pixel island are reset.

[0055] At the second rising edge of the clock signal CLK after the rising edge of the chip select signal SCS, the voltage of the gate control signal RST provided to each pixel circuit in the pixel island is set to a high level voltage.

[0056] At the subsequent falling edge of the clock signal CLK, the gate control signal Gate1 provided to the first pixel circuit is set to a low-level voltage.

[0057] At the third rising edge of the clock signal CLK following the rising edge of the chip select signal SCS, the gate control signal Gate1 provided to the first pixel circuit is set to a high voltage. While the gate control signal Gate1 provided to the first pixel circuit remains at a low voltage, the transistor M7 in the first pixel circuit is turned on, and the threshold-compensated data voltage is written to the gate of the transistor M1 in the pixel circuit.

[0058] At the subsequent falling edge of the clock signal CLK, the gate control signal Gate2 provided to the second pixel circuit is set to a low level voltage.

[0059] At the fourth rising edge of the clock signal CLK following the rising edge of the chip select signal SCS, the gate control signal Gate2 provided to the first pixel circuit is set to a high voltage. While the gate control signal Gate2 provided to the second pixel circuit remains low, the transistor M7 in the second pixel circuit is turned on, and the threshold-compensated data voltage is written to the gate of the transistor M1 in the pixel circuit.

[0060] After the pixel voltage is written to all the pixel circuits in the pixel island in turn, the chip select signal SCS provided to the pixel island is set to a low-level voltage (invalid voltage in this embodiment) at the falling edge of the first clock signal CLK, and the gate control signal EM provided to all the pixel circuits in the pixel island is set to a low-level voltage (valid voltage in this embodiment), so that all the sub-pixels in the pixel island enter the light-emitting state.

[0061] In some other embodiments, the logic control circuit lights up the sub-pixels in the same pixel island sequentially or in a time-sharing manner. The present disclosure does not limit the timing of lighting up the sub-pixels in the pixel island.

[0062] The present disclosure does not limit the specific implementation form of the logic control circuit. For example, the circuit form of the logic control circuit can be designed by means of a state transition diagram. For another example, the logic control circuit includes a counter and a mapping table. The mapping table records the mapping relationship between the counting result of the counter and the gate control signal received by each pixel circuit. As the counting result of the counter increases, the state of each gate control signal received by each pixel circuit also changes. For another example, the logic control circuit includes a counter and multiple operation circuits for obtaining each gate control signal. Each operation circuit is used to map a specific counting result to a specific high-level state (digital 1) or a low-level state (digital 0).

[0063] In some embodiments, multiple sub-pixels are divided into sub-pixels of multiple colors, sub-pixels of the same color are distributed in the same rectangular area extending along a first direction, and sub-pixels of different colors are arranged along a second direction. The first direction and the second direction are parallel to and intersect with the plane of the driving layer.

[0064] exist Figure 1 In the illustrated embodiment, a single pixel island contains multiple red LED chips R, which are evenly distributed within a rectangular region extending along a first direction. Because the rectangular region is limited in size along the first direction, the multiple red LED chips R are staggered. If the rectangular region is sufficiently large along the first direction, the multiple red LED chips R can be arranged in a row along the first direction.

[0065] refer to Figure 2 Each red LED chip R integrates N sub-pixels R1, R2...RN.

[0066] In some other embodiments, a single pixel island includes one red LED chip R, and the red LED chip R integrates N sub-pixels R1, R2, ..., RN.

[0067] In some other embodiments, a single pixel island includes multiple red LED chips R, and a single red LED constitutes a red sub-pixel.

[0068] In some other embodiments, the sub-pixels in a single pixel island are organic light emitting diodes or quantum dot light emitting diodes.

[0069] In some embodiments, the light emitted by the sub-pixel is collimated light. For example, a collimating structure (not shown) can be provided in the pixel island. The collimating structure is, for example, a lens structure. The collimating structure is, for example, a black matrix. This disclosure does not limit how to control the light emission direction of the sub-pixel.

[0070] In some embodiments, the number of data pads is equal to the number of color types of sub-pixels, and each data pad receives a data voltage of a sub-pixel of one color.

[0071] Figure 7 It is a variation of the driving layer in the pixel island of the embodiment of the present disclosure. Figure 7 In these embodiments, the pixel island includes three data pads, one for receiving the red subpixel's data voltage DataR, the other for receiving the green subpixel's data voltage DataG, and the other for receiving the blue subpixel's data voltage DataG. Accordingly, in the display panel, the pixel island is connected to three data lines. This design reduces the time required to write data to the pixel island.

[0072] Figure 5 Schematic diagram of the connection relationship of some structures in the display device of an embodiment of the present disclosure.

[0073] refer to Figure 5 An embodiment of the present disclosure provides a display panel, including a driving backplane P and a plurality of the aforementioned pixel islands I. The driving backplane P includes a plurality of power lines (not shown), a plurality of chip select signal lines L2 and clock signal lines L3 extending along a third direction, and a plurality of data lines L1 extending along a fourth direction. The power lines are used to provide a power supply voltage to the power pads of the pixel islands. The third direction and the fourth direction are two directions parallel to and intersecting with the plane in which the display panel is located. The chip select signal line L2 is used to provide a chip select signal to the chip select pads of the pixel islands. The clock signal line L3 is used to provide a clock signal to the clock pads of the pixel islands. The data line L1 is used to provide a data voltage to the data pads of the pixel islands.

[0074] Specifically, in Figure 5 In the embodiment shown, the third direction is perpendicular to the fourth direction, and the pixel islands I are arranged in an array along the third direction and the fourth direction.

[0075] It should be noted that the data line L1 extending along the fourth direction means that the entire section of the data line L1 excluding the section in the fan-out area extends along the fourth direction. The section of the data line L1 excluding the section in the fan-out area may be a straight line or a serpentine line.

[0076] The top view boundary of the pixel island 1 is not limited to a rectangular shape. In other embodiments, the top view boundary of the pixel island 1 is, for example, a regular hexagon.

[0077] In some embodiments, in the display panel, sub-pixels of the same color are distributed in a same rectangular area extending along the third direction, and sub-pixels of different colors are periodically arranged along the fourth direction.

[0078] In other words, Figure 1 The first direction in Figure 5The third direction in is the same direction. Figure 5 In the display panel shown, the red LED chips R in a row of pixel islands arranged along the third direction are distributed within a rectangular area extending along the third direction; the green LED chips G in a row of pixel islands arranged along the third direction are distributed within a rectangular area extending along the third direction; and the blue LED chips B in a row of pixel islands arranged along the third direction are distributed within a rectangular area extending along the third direction. Figure 5 In the display panel shown, along the fourth direction, the region where the red sub-pixels are located, the region where the green sub-pixels are located, and the region where the blue sub-pixels are located are periodically arranged.

[0079] It should be noted that the present disclosure does not impose any special limitation on the arrangement of pixel islands in the display panel.

[0080] In the display panels of some embodiments of the present disclosure, when the refresh frequency is 60Hz, the data writing time of all pixel islands should be less than 16.67ms. Each LED chip R, G or B contains Q sub-pixels and has Q data writing cycles. Limited by the low-temperature polysilicon process level, the shortest data writing cycle is 0.8us. Assume that the pixel island includes a red LED chip R, a blue LED chip G and a green LED chip B, and then assume that the pixel island has a data pad. Then the data writing time of a pixel island is 3*Q*0.8us. If it is assumed that there are M rows of pixel islands arranged along the third direction in the display panel, then the total data writing time of the display panel is 3*Q*M*0.8us. It should satisfy 3*Q*M*0.8us<16.67ms. This limits the resolution of the display panel.

[0081] To improve the resolution of the display panel, in some embodiments, a plurality of data pads may be provided in the pixel islands. Accordingly, a column of pixel islands arranged along the fourth direction in the display panel is connected to a plurality of data lines.

[0082] refer to Figure 5 Based on the same inventive concept, an embodiment of the present disclosure also provides a display device, including: a source driver chip IC1, a gate driver chip IC2, and the aforementioned display panel P, the source driver chip IC1 is used to drive the data line L1 in the display panel P, and the gate driver chip IC2 is used to drive the chip select signal line L2 and the clock signal line L8.

[0083] The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or the like.

[0084] Figure 8 Schematic diagram of the structure of the light field display device provided by the embodiment of the present disclosure.

[0085] refer to Figure 8 Based on the same inventive concept, an embodiment of the present disclosure further provides a light field display device, comprising: a source driver chip IC1, a gate driver chip IC2, and the aforementioned display panel, wherein the source driver chip IC1 is used to drive the data line L1, and the gate driver chip IC2 is used to drive the chip select signal line L2 and the clock signal line L3; the light field display device further comprises a lens structure 200 arranged on the light emitting surface of the display panel P.

[0086] Figure 8 2 shows an exemplary lens structure 200 in a light field display device. A plurality of lens structures 200 respectively cover a column of pixel islands I arranged along the fourth direction.

[0087] The present disclosure does not limit the design of the lens structure 200 , and those skilled in the art may configure the lens structure 200 according to conventional design methods of light field display devices.

[0088] The various embodiments in the present disclosure are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on the differences from other embodiments.

[0089] The scope of protection of the present disclosure is not limited to the above-described embodiments. Obviously, those skilled in the art may make various modifications and variations to the present disclosure without departing from the scope and spirit of the present disclosure. If such modifications and variations fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such modifications and variations.

Claims

1. A pixel island, characterized in that: include: A driving layer, comprising a power pad, a data pad, a clock pad, and a chip select pad, as well as a logic processing circuit and a plurality of pixel circuits, wherein the power pad, the data pad, the clock pad, and the chip select pad are used to be electrically connected to traces on a driving backplane; the power pad is used to supply power to the logic processing circuit and the pixel circuit, the data pad is used to provide a data voltage to the pixel circuit, and the logic processing circuit is used to provide a gate control signal to the pixel circuit according to a clock signal from the clock pad and a chip select signal from the chip select pad; a plurality of sub-pixels, wherein the plurality of sub-pixels are electrically connected to the pixel circuit in a one-to-one correspondence; The driving layer includes a base layer and a circuit layer provided on the base layer, the logic processing circuit and the plurality of pixel circuits are provided in the circuit layer, the power pad, the data pad, the chip select pad and the clock pad are provided on a surface of the base layer away from the circuit layer, and the power pad, the data pad, the chip select pad and the clock pad are electrically connected to the circuit layer through vias penetrating the base layer; The plurality of sub-pixels are arranged on a surface of the circuit layer away from the base layer, and light emitting directions of the plurality of sub-pixels are in a direction from the base layer to the circuit layer.

2. The pixel island according to claim 1, wherein: The logic processing circuit is configured to sequentially generate gate control signals provided to the pixel circuit under the stimulation of rising and falling edges of the clock signal during a period in which the chip select signal maintains a valid voltage.

3. The pixel island according to claim 1, wherein: The multiple sub-pixels are divided into sub-pixels of multiple colors, sub-pixels of the same color are distributed in the same rectangular area extending along the first direction, and sub-pixels of different colors are arranged along the second direction. The first direction and the second direction are parallel to the plane of the driving layer and intersect with each other.

4. The pixel island according to claim 1, wherein: The light emitted by the sub-pixel is collimated light.

5. The pixel island according to claim 2, wherein: The number of the data pads is equal to the number of colors of the sub-pixels, and each data pad is used to receive a data voltage of a sub-pixel of one color.

6. The pixel island according to claim 1, wherein: The sub-pixel includes: an LED.

7. A display panel, characterized in that: It includes a driving backplane and a plurality of pixel islands according to any one of claims 1 to 6, the driving backplane includes a plurality of power lines, a plurality of chip select signal lines and clock signal lines extending along a third direction, and a plurality of data lines extending along a fourth direction, the power lines are used to provide power supply voltages to power pads of the pixel islands, the third direction and the fourth direction are two directions parallel to and intersecting with the plane of the display panel, the chip select signal lines are used to provide chip select signals to the chip select pads of the pixel islands, the clock signal lines are used to provide clock signals to the clock pads of the pixel islands, and the data lines are used to provide data voltages to the data pads of the pixel islands.

8. The display panel according to claim 7, wherein: In the display panel, sub-pixels of the same color are distributed in a same rectangular area extending along the third direction, and sub-pixels of different colors are periodically arranged along the fourth direction.

9. The display panel according to claim 7, wherein: A column of the pixel islands arranged along the fourth direction is correspondingly connected to one or more data lines.

10. A display device, characterized in that: include: A source driver chip, a gate driver chip, and a display panel according to any one of claims 7 to 9, wherein the source driver chip is used to drive the data line, and the gate driver chip is used to drive the chip select signal line and the clock signal line.

11. A light field display device, characterized in that: include: A source driver chip, a gate driver chip, and a display panel according to any one of claims 7 to 9, wherein the source driver chip is used to drive the data line, and the gate driver chip is used to drive the chip select signal line and the clock signal line; the light field display device further includes a lens structure arranged on the light output surface of the display panel.

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