Shift register and driving method thereof, gate driving circuit, display device

Abstract

The present disclosure provides a shift register and a driving method thereof, a gate driving circuit, and a display device. The shift register comprises: an input circuit; a first control circuit configured to transmit a signal of a second clock terminal to a first node in response to a signal of the second clock terminal and a signal of a seventh node; a second control circuit configured to transmit a signal of an input terminal to a second node in response to a signal of a third clock terminal; a third control circuit configured to provide a signal for a third node in response to a signal of the input terminal, a signal of the second clock terminal and a signal of the third clock terminal; a first output circuit configured to transmit a signal of a clock power terminal to an output terminal in response to a signal of the first node; a second output circuit configured to transmit a signal of a first power terminal to the output terminal in response to a signal of the second node; and a third output circuit configured to transmit a signal of a second power terminal to the output terminal in response to a first level signal of the third node.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, specifically to a shift register and its driving method, a gate driving circuit, and a display device. Background Technology

[0002] The application scope of OLED (Organic Light-Emitting Diode) displays is becoming increasingly broad. Some display products need to face different usage scenarios, and their refresh rate requirements are also very different. The screen needs to have good display effects at refresh rates ranging from a few Hz to 200-300 Hz.

[0003] In an OLED display substrate, the gate driving circuit is connected to multiple gate lines, providing scan signals to each gate line row by row. Multiple gate lines and multiple data lines intersect to define multiple pixels. Each pixel contains a pixel circuit and a light-emitting device. The operation of the pixel circuit includes data writing and compensation phases. During the data writing and compensation phases, the pixel circuit responds to the scan signal by writing data voltage and threshold voltage into a storage capacitor, thereby performing threshold compensation. Separating data writing and threshold compensation can effectively improve the refresh rate that a pixel can support; however, the pixel requires a scan signal with adjustable pulse width to compensate for the duration. Summary of the Invention

[0004] This disclosure presents a shift register and its driving method, a gate driving circuit, and a display device.

[0005] This disclosure provides a shift register, including:

[0006] The input circuit is configured to transmit the input signal to the seventh node in response to a first level signal at the first clock terminal.

[0007] The first control circuit is configured to transmit the signal from the second clock terminal to the first node in response to the first level signal of the second clock terminal and the first level signal of the seventh node.

[0008] The second control circuit is configured to transmit the input signal to the second node in response to the first level signal at the third clock terminal.

[0009] The third control circuit is configured to provide a signal to the third node in response to the signal at the input terminal, the signal at the second clock terminal, and the signal at the third clock terminal.

[0010] The first output circuit is configured to transmit a signal from the clock power supply terminal to the output terminal in response to a first level signal of the first node.

[0011] The second output circuit is configured to transmit a signal from the first power supply terminal to the output terminal in response to a first level signal from the second node; the first power supply terminal is used to provide the first level signal.

[0012] The third output circuit is configured to transmit a signal from the second power supply terminal to the output terminal in response to a first level signal from the third node; the second power supply terminal is used to provide a second level signal.

[0013] In some embodiments, the input circuit includes:

[0014] The first transistor has its control electrode connected to the first clock terminal, its first electrode connected to the input terminal, and its second electrode connected to the seventh node.

[0015] In some embodiments, the first control circuit includes:

[0016] The second transistor has its control electrode connected to the seventh node, its first electrode connected to the second clock terminal, and its second electrode connected to the fourth node.

[0017] The third transistor has its control electrode connected to the second clock terminal, its first electrode connected to the fourth node, and its second electrode connected to the first node.

[0018] The fifth capacitor has its two ends connected to the seventh node and the fourth node, respectively.

[0019] In some embodiments, the shift register further includes:

[0020] The fourth control circuit is configured to transmit the signal from the first clock terminal to the seventh node and the signal from the second power supply terminal to the first node in response to the first level signal of the second node.

[0021] In some embodiments, the fourth control circuit includes:

[0022] The fourth transistor has its control electrode connected to the second node, its first electrode connected to the seventh node, and its second electrode connected to the first clock terminal.

[0023] The fifth transistor has its control electrode connected to the second node, its first electrode connected to the first node, and its second electrode connected to the second power supply terminal.

[0024] In some embodiments, the second control circuit includes:

[0025] The sixth transistor has its control electrode connected to the third clock terminal, its first electrode connected to the input terminal, and its second electrode connected to the second node;

[0026] The second capacitor has its two ends connected to the second node and the first power supply terminal, respectively.

[0027] In some embodiments, the third control circuit includes:

[0028] A first control sub-circuit is configured to transmit a signal from the first power supply terminal to the sixth node in response to a first level signal from the second clock terminal; and to transmit a signal from the second clock terminal to the sixth node in response to a first level signal from the second node.

[0029] The second control sub-circuit is configured to transmit the signal at the third clock signal terminal to the third node in response to the first level signal of the sixth node and the first level signal of the third clock terminal.

[0030] The third control sub-circuit is configured to transmit the signal from the second power supply terminal to the third node in response to the first level signal at the input terminal and the first level signal at the second clock terminal.

[0031] The storage sub-circuit is configured to maintain the voltage between the third node and the second power supply terminal when the third node is floating.

[0032] In some embodiments, the first control sub-circuit includes:

[0033] The seventh transistor has its control electrode connected to the second clock terminal, its first electrode connected to the first power supply terminal, and its second electrode connected to the sixth node;

[0034] The eighth transistor has its control electrode connected to the second node, its first electrode connected to the second clock terminal, and its second electrode connected to the sixth node.

[0035] In some embodiments, the second control sub-circuit includes:

[0036] The ninth transistor has its control electrode connected to the sixth node and its first electrode connected to the third clock terminal;

[0037] The fourth capacitor has its two ends connected to the sixth node and the second terminal of the ninth transistor, respectively.

[0038] The tenth transistor has its control electrode connected to the third clock terminal, its first electrode connected to the second electrode of the ninth transistor, and its second electrode connected to the third node.

[0039] In some embodiments, the third control sub-circuit includes:

[0040] The fifteenth transistor has its control electrode connected to the second clock terminal and its first electrode connected to the input terminal.

[0041] The eleventh transistor has its control electrode connected to the second electrode of the fifteenth transistor, and the first electrode of the eleventh transistor is connected to the second power supply terminal; the second electrode of the eleventh transistor is connected to the third node.

[0042] In some embodiments, the storage sub-circuit includes a third capacitor, the two ends of which are respectively connected to the third node and the second power supply terminal.

[0043] In some embodiments, the first output circuit includes:

[0044] The twelfth transistor has its control electrode connected to the first node, its first electrode connected to the clock power supply terminal, and its second electrode connected to the output terminal.

[0045] The first capacitor has its two ends connected to the first node and the output terminal, respectively.

[0046] In some embodiments, the second output circuit includes a thirteenth transistor, whose control electrode is connected to the second node, its first electrode is connected to the first power supply terminal, and its second electrode is connected to the output terminal.

[0047] In some embodiments, the third output circuit includes: a fourteenth transistor, the control electrode of which is connected to the third node, the first electrode of which is connected to the output terminal, and the second electrode of which is connected to the second power supply terminal.

[0048] This disclosure also provides a method for driving the shift register as described above, including:

[0049] In the first stage, the input terminal and the first clock terminal provide a first level signal, and the second clock terminal and the third clock terminal provide a second level signal; the input circuit transmits the signal from the first clock terminal to the seventh node, and the third output circuit transmits the signal from the second power supply terminal to the output terminal;

[0050] In the second stage, the input terminal and the second clock terminal provide a first level signal, the first clock terminal and the third clock terminal provide a second level signal, and the clock power supply terminal provides a first level signal; the first control circuit transmits the signal from the second clock terminal to the first node, and the first output circuit transmits the first level signal from the clock power supply terminal to the output terminal;

[0051] In the third stage, the input terminal and the third clock terminal provide a first level signal, and the first clock terminal and the second clock terminal provide a second level signal; the second control circuit transmits the signal from the input terminal to the second node, and the second output circuit transmits the signal from the first level terminal to the output terminal;

[0052] In the fourth stage, the input terminal, the first clock terminal, and the third clock terminal provide a second level signal, the second clock terminal provides a first level signal, and the second output circuit transmits the signal from the first power supply terminal to the output terminal.

[0053] In the fifth stage, the input terminal, the first clock terminal, and the second clock terminal provide a second level signal, and the third clock terminal provides a first level signal; the third control circuit transmits the first level signal of the third clock terminal to the third node, and the third output circuit transmits the signal of the second power supply terminal to the output terminal.

[0054] This disclosure also provides a gate drive circuit including a plurality of cascaded shift registers as described above.

[0055] This disclosure also provides a display device including the gate driving circuit described above. Attached Figure Description

[0056] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the drawings:

[0057] Figure 1 This is a schematic diagram of a shift register provided in some embodiments of this disclosure.

[0058] Figure 2 This is a schematic diagram of a shift register provided in some other embodiments of this disclosure.

[0059] Figure 3 This is a schematic diagram of a shift register provided in some other embodiments of this disclosure.

[0060] Figure 4 Timing diagrams of shift registers provided in some embodiments of this disclosure.

[0061] Figure 5 A schematic diagram of the on / off states of each transistor in a shift register in the first stage, provided for some embodiments of this disclosure.

[0062] Figure 6 A schematic diagram of the on / off state of each transistor in a shift register in the second stage, provided for some embodiments of this disclosure.

[0063] Figure 7 A schematic diagram of the on / off state of each transistor in a shift register in the third stage, provided for some embodiments of this disclosure.

[0064] Figure 8A schematic diagram of the on / off state of each transistor in a shift register in the fourth stage, provided for some embodiments of this disclosure.

[0065] Figure 9 A schematic diagram of the on / off state of each transistor in a shift register in the fifth stage, provided for some embodiments of this disclosure.

[0066] Figure 10 This is a schematic diagram of a shift register provided in some other embodiments of this disclosure.

[0067] Figure 11 for Figure 10 The timing diagram of the shift register shown is shown.

[0068] Figure 12 This is a schematic diagram of a shift register driving method provided in some embodiments of this disclosure. Detailed Implementation

[0069] The specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit this disclosure.

[0070] The terms "first," "second," and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, terms such as "comprising" or "including" mean that the element or object preceding the word covers the element or object listed after the word and its equivalents, without excluding other elements or objects. Terms such as "coupled" or "connected" are not limited to physical or mechanical coupling, but can include electrical coupling, whether direct or indirect (e.g., other electronic components may exist between two coupled elements).

[0071] The transistors used in the embodiments of this disclosure can all be thin-film transistors, field-effect transistors, or other devices with the same characteristics. In this embodiment, the coupling method of the drain and source of each transistor can be interchanged; therefore, the drain and source of each transistor in this disclosure embodiment are actually indistinguishable. Here, one of the two terminals of the transistor other than the control terminal (i.e., the gate) is called the drain, and the other is called the source, only to distinguish between them. The thin-film transistors used in the embodiments of this disclosure can be N-type transistors or P-type transistors. In the embodiments of this disclosure, when an N-type thin-film transistor is used, its first terminal can be the source, and its second terminal can be the drain. In the following embodiments, the description uses a P-type thin-film transistor as an example.

[0072] In this disclosure, a "first level signal" refers to a signal input to the control electrode of a transistor that can control the transistor to conduct, and a "second level signal" refers to a signal input to the control electrode of a transistor that can control the transistor to cut off. In some embodiments, the first level signal can be a high-level signal and the second level signal can be a low-level signal; in other embodiments, the first level signal can be a low-level signal and the second level signal can be a high-level signal. Specifically, for an N-type transistor, the first level signal is a high-level signal and the first level potential is a high-level potential; the second level signal is a low-level signal and the second level potential is a low-level potential. For a P-type transistor, the first level signal is a low-level signal and the first level potential is a low-level potential; the second level signal is a high-level signal and the second level potential is a high-level potential.

[0073] The application of OLED (Organic Light-Emitting Diode) displays has gradually expanded from small and medium-sized watches, mobile phones, and tablets to computers (PCs) and monitors. Because PCs and similar devices face vastly different usage scenarios, their refresh rate requirements vary considerably. For example, text reading or power-saving modes generally require refresh rates below 10Hz, while web browsing and video playback demand 48-60Hz. Gaming and other scenarios require refresh rates of 120-144Hz or even above 240Hz. This necessitates screens with good display performance across refresh rates ranging from a few Hz to 200-300Hz.

[0074] In the display substrate, the gate driving circuit includes multiple cascaded shift registers connected to gate lines. These shift registers sequentially provide scan signals to multiple gate lines. Multiple gate lines and multiple data lines intersect to define multiple pixels. Each pixel contains a pixel circuit and a light-emitting device. The pixel circuit's operation includes data writing and compensation phases. During these phases, the pixel circuit responds to the scan signal by writing data voltage and threshold voltage into a storage capacitor, thereby performing threshold compensation. Separating data writing and threshold compensation effectively increases the refresh rate supported by the pixel; however, the pixel requires an adjustable pulse width scan signal to compensate for the duration. The structure of the light-emitting device can be varied and selected according to actual needs. For example, the light-emitting device can be an OLED, a quantum dot light-emitting diode (QLED), or a micro light-emitting diode (Micro LED), etc.

[0075] Taking a P-type transistor as an example, in related technologies with adjustable scan signal pulse widths, the falling edge time of the scan signal is relatively long, with a width exceeding 1H. Since this falling edge occurs at the initial moment of threshold compensation, a long falling edge time will affect the overall compensation effect of the pixel circuit.

[0076] Figure 1 This is a schematic diagram of a shift register provided in some embodiments of this disclosure, such as... Figure 1 As shown, the shift register includes: an input circuit 80, a first control circuit 10, a second control circuit 20, a third control circuit 30, a first output circuit 50, a second output circuit 60, and a third output circuit 70.

[0077] The input circuit 80 is connected to the first clock terminal CK1 and the input terminal IN of the shift register, and is configured to transmit the signal of the input terminal IN to the seventh node N7 in response to the first level signal of the first clock terminal CK1.

[0078] The first control circuit 10 is connected to the seventh node N7 and the second clock terminal CK2, and is configured to transmit the signal of the second clock terminal CK2 to the first node N1 in response to the first level signal of the second clock terminal CK2 and the first level signal of the seventh node N7. The seventh node N7 is the connection node between the input circuit 80 and the first control circuit 10, and the first node N1 is the connection node between the first control circuit 10 and the first output circuit 50.

[0079] The second control circuit 20 is connected to the input terminal IN and the third clock terminal CK3, and is configured to transmit the signal at the input terminal IN to the second node N2 in response to the first level signal at the third clock terminal CK3. The second node N2 is the connection node between the second control circuit 20 and the second output circuit 60.

[0080] The third control circuit 30 is connected to the input terminal IN, the second clock terminal CK2, and the third clock terminal CK3. In response to the signals of the input terminal IN, the second clock terminal CK2, and the third clock terminal CK3, it provides signals to the third node N3. The third node N3 is the connection node between the third control circuit 30 and the third output circuit 70.

[0081] For example, the third control circuit 30 can be configured to maintain the potential of the third node N3 in response to the first level signal of the input terminal IN, the second level signal of the second clock terminal CK2 and the second level signal of the third clock terminal CK3; and to provide a first level signal to the third node N3 in response to the second level signal of the input terminal IN, the second level signal of the second clock terminal CK2 and the first level signal of the third clock terminal CK3.

[0082] The first output circuit 50 is connected to the first node N1, the clock power supply terminal CKBO, and the output terminal AZOUT. It is configured to transmit the signal from the clock power supply terminal CKBO to the output terminal AZOUT in response to a first-level signal from the first node N1. The clock power supply terminal CKBO provides the clock signal, which switches between a first-level state and a second-level state.

[0083] The second output circuit 60 is connected to the second node N2, the first power supply terminal V1, and the output terminal AZOUT. It is configured to transmit the signal from the first power supply terminal V1 to the output terminal AZOUT in response to a first level signal from the second node N2. The first power supply terminal V1 is used to provide the first level signal.

[0084] The third output circuit 70 is connected to the third node N3, the output terminal AZOUT, and the second power supply terminal V2. It is configured to transmit the signal from the second power supply terminal V2 to the output terminal AZOUT in response to a first-level signal from the third node N3. The second power supply terminal V2 is used to provide the second-level signal.

[0085] In this embodiment of the disclosure, the operating state of the shift register may include at least five stages. In the first stage, the input terminal IN and the first clock terminal CK1 provide a first level signal, and the second clock terminal CK2 and the third clock terminal CK3 provide a second level signal. The input circuit 80 transmits the signal of the input terminal IN to the seventh node N7, the third control circuit 30 controls the third node N3 to maintain the first level potential of the previous stage, and the third output circuit 70 transmits the signal of the second power supply terminal V2 to the output terminal AZOUT.

[0086] In the second stage, the input terminal IN and the second clock terminal CK2 provide a first level signal, the first clock terminal CK1 and the third clock terminal CK3 provide a second level signal, and the clock power supply terminal CKBO provides a first level signal; the first control circuit 10 transmits the first level signal of the second clock terminal CK2 to the first node N1, and the first output circuit 50 transmits the first level signal of the clock power supply terminal CKBO to the output terminal AZOUT.

[0087] In the third stage, the input terminal IN and the third clock terminal CK3 provide a first level signal, and the first clock terminal CK1 and the second clock terminal CK2 provide a second level signal; the second control circuit 20 transmits the signal from the input terminal IN to the second node N2, and the second output circuit 60 transmits the signal from the first level terminal to the output terminal AZOUT.

[0088] In the fourth stage, the input terminal IN, the first clock terminal CK1, and the third clock terminal CK3 provide a second level signal, the second clock terminal CK2 provides a first level signal, the second node N2 maintains the first level potential of the third stage, and the second output circuit 60 transmits the signal from the first power supply terminal V1 to the output terminal AZOUT.

[0089] In the fifth stage, the input terminal IN, the first clock terminal CK1, and the second clock terminal CK2 provide a second level signal, and the third clock terminal CK3 provides a first level signal; the third control circuit 30 transmits the first level signal of the third clock terminal CK3 to the third node N3, and the third output circuit 70 transmits the signal of the second power supply terminal V2 to the output terminal AZOUT.

[0090] As can be seen, the input terminal IN provides the first level signal from the beginning of the first stage and stops providing the first level signal at the beginning of the fourth stage; while the output terminal AZOUT starts outputting the first level signal at the beginning of the second stage and stops outputting the first level signal at the beginning of the fifth stage, thereby realizing the shift function.

[0091] In this embodiment, the first control circuit 10, the second control circuit 20, and the third control circuit 30 are all controlled by the input terminal IN and at least one of the first clock terminal CK1, the second clock terminal CK2, and the third clock terminal CK3 to control the potentials of the first node N1, the second node N2, and the third node N3, respectively. The first output circuit 50, the second output circuit 60, and the third output circuit 70 respond to the potentials of the first node N1, the second node N2, and the third node N3 to control the output terminal AZOUT. Therefore, by controlling the signals of the input terminal IN, the first clock terminal CK1, the second clock terminal CK2, and the third clock terminal CK3, the pulse width of the output signal at the output terminal AZOUT can be adjusted. Furthermore, when the first node N1 is at the first level potential, the first output circuit 50 does not transmit the signal from the first power supply terminal to the output terminal AZOUT, but instead transmits the signal from the clock power supply terminal CKBO to the output terminal AZOUT, thereby reducing the falling edge time of the scan signal.

[0092] The first output circuit 50 can also be configured to maintain a constant voltage between the output terminal AZOUT and the first node N1 when the first node N1 is floating. Taking a low-level signal as an example, in the second stage, the first node N1 is floating. Therefore, when the low-level signal of the clock power supply terminal CKBO is transmitted to the output terminal AZOUT, the potential of the first node N1 further decreases, thereby ensuring the conduction of the first output circuit 50, ensuring the falling edge output of the output terminal AZOUT, and reducing the falling edge time of the scan signal.

[0093] Figure 2 This is a schematic diagram of a shift register provided in some other embodiments of this disclosure, such as... Figure 2 As shown, the shift register may further include a fourth control circuit 40, which is connected to the first node N1, the second node N2, the first clock terminal CK1, and the second power supply terminal V2. The fourth control circuit 40 is configured to transmit the signal of the first clock terminal CK1 to the seventh node N7 and the signal of the second power supply terminal V2 to the first node N1 in response to the first level signal of the second node N2. This ensures that when the second node N2 is in the first level state, the first node N1 is in the second level state. That is, when the second output circuit 60 connects the second power supply terminal V2 to the output terminal AZOUT, the first output circuit 50 keeps the clock power supply terminal CK1 disconnected from the output terminal AZOUT to prevent interference with the output signal of the output terminal AZOUT.

[0094] Figure 3 This is a schematic diagram of a shift register provided in some other embodiments of this disclosure. Figure 3 The shift register shown is Figure 2 A specific implementation scheme, such as Figure 2 and Figure 3 As shown, the input circuit 80 includes a first transistor T1. The control electrode of the first transistor T1 is connected to the first clock terminal CK1, the first electrode is connected to the input terminal IN, and the second electrode is connected to the seventh node N7. When the first clock terminal CK1 provides a first level signal, the first and second electrodes of the first transistor T1 are turned on, thereby transmitting the signal from the input terminal IN to the seventh node N7.

[0095] In some embodiments, the first control circuit 10 includes a second transistor T2, a third transistor T3, and a fifth capacitor C5. The control electrode of the second transistor T2 is connected to the seventh node N7, the first electrode is connected to the second clock terminal CK2, and the second electrode is connected to the fourth node N4. The control electrode of the third transistor T3 is connected to the second clock terminal CK2, the first electrode is connected to the fourth node N4, and the second electrode is connected to the first node N1. The two ends of the fifth capacitor C5 are connected to the seventh node N7 and the fourth node N4, respectively.

[0096] In some embodiments, the second control circuit 20 includes a sixth transistor T6 and a second capacitor C2. The control electrode of the sixth transistor T6 is connected to the third clock terminal CK3, the first electrode is connected to the input terminal IN, and the second electrode is connected to the second node N2. The two ends of the second capacitor C2 are connected to the second node N2 and the first power supply terminal V1, respectively.

[0097] In some embodiments, the third control circuit 30 includes a first control sub-circuit 31, a second control sub-circuit 32, a third control sub-circuit 33, and a storage sub-circuit 34. The first control sub-circuit 31 is connected to a second clock terminal CK2, a first power supply terminal V1, a second node N2, and a sixth node N6. The first control sub-circuit 31 is configured to transmit a signal from the first power supply terminal V1 to the sixth node N6 in response to a first-level signal from the second clock terminal CK2; and to transmit a signal from the second clock terminal CK2 to the sixth node N6 in response to a first-level signal from the second node N2. The sixth node N6 is the connection node between the first control sub-circuit 31 and the second control sub-circuit 32.

[0098] The second control sub-circuit 32 is connected to the sixth node N6, the third node N3 and the third clock terminal CK3, and is configured to transmit the signal of the third clock terminal CK3 to the third node N3 in response to the first level signal of the sixth node N6 and the first level signal of the third clock terminal CK3.

[0099] The third control sub-circuit 33 is connected to the input terminal IN, the second clock terminal CK2, the second power supply terminal V2 and the third node N3. It is configured to transmit the signal of the second power supply terminal V2 to the third node N3 in response to the first level signal of the input terminal IN and the first level signal of the second clock terminal CK2.

[0100] In the first stage described above, the third node N3 is floating. Under the voltage holding function of the third control sub-circuit 33, the third node N3 maintains the previous first level potential. At this time, the third control sub-circuit 33 transmits the second level signal of the second power supply terminal V2 to the output terminal AZOUT. In the second stage described above, the second output circuit 60 transmits the first level signal of the first power supply terminal V1 to the output terminal AZOUT; at the same time, the third control sub-circuit 33 transmits the second level signal of the second power supply terminal V2 to the third node N3, and the third output circuit 70 disconnects the second power supply terminal V2 from the output terminal AZOUT. In the third stage described above, the second control circuit 20 transmits the first level signal of the input terminal IN to the second node N2, and the second output circuit 60 transmits the first level signal of the first power supply terminal V1 to the output terminal AZOUT; at the same time, the fourth control circuit 40 transmits the second level signal of the second power supply terminal V2 to the first node N1, thereby causing the first output circuit 50 to disconnect the output terminal AZOUT from the clock power supply terminal CKBO; while the third node N3 maintains the second level potential of the previous stage, and the third output circuit 70 maintains the disconnection of the second power supply terminal V2 from the output terminal AZOUT. In the fourth stage described above, the second node N2 maintains the first level potential from the previous stage, and the second output circuit 60 transmits the first level signal of the first power supply terminal V1 to the output terminal AZOUT; simultaneously, the third control sub-circuit 33 transmits the second level signal of the second power supply terminal V2 to the third node N3, and the third output circuit 70 keeps the second power supply terminal V2 disconnected from the output terminal AZOUT. In the fifth stage described above, the second control circuit 20 transmits the second level signal of the input terminal IN to the third node N3, and the second output circuit 60 disconnects the first power supply terminal V1 from the output terminal AZOUT; simultaneously, the third control sub-circuit 33 transmits the first level signal of the third clock terminal CK3 to the third node N3, and the third output circuit 70 transmits the second level signal of the second power supply terminal V2 to the output terminal AZOUT.

[0101] In some embodiments, the first control sub-circuit 31 may include a seventh transistor T7 and a second transistor T2. The control electrode of the seventh transistor T7 is connected to the second clock terminal CK2, its first electrode is connected to the first power supply terminal V1, and its second electrode is connected to the sixth node N6. The control electrode of the eighth transistor T8 is connected to the second node N2, its first electrode is connected to the second clock terminal CK2, and its second electrode is connected to the sixth node N6.

[0102] In some embodiments, the second control sub-circuit 32 may include: a ninth transistor T9, a fourth capacitor C4, and a tenth transistor T10. The control electrode of the ninth transistor T9 is connected to the sixth node N6, the first electrode is connected to the third clock terminal CK3, and the second electrode is connected to the fifth node N5. The two ends of the fourth capacitor C4 are connected to the sixth node N6 and the fifth node N5, respectively. The control electrode of the tenth transistor T10 is connected to the third clock terminal CK3, the first electrode of the tenth transistor T10 is connected to the second electrode of the ninth transistor T9, and the second electrode of the tenth transistor T10 is connected to the third node N3.

[0103] In some embodiments, the third control sub-circuit 33 may include: a fifteenth transistor T15 and an eleventh transistor T11. The control electrode of the fifteenth transistor T15 is connected to the second clock terminal CK2, and its first electrode is connected to the input terminal IN. The control electrode of the eleventh transistor T11 is connected to the second electrode of the fifteenth transistor T15, and the first electrode of the eleventh transistor T11 is connected to the second power supply terminal; the second electrode of the eleventh transistor T11 is connected to the third node N3.

[0104] In some embodiments, the storage sub-circuit 34 includes a third capacitor C3, the two ends of which are respectively connected to the third node N3 and the second power supply terminal V2.

[0105] In some embodiments, the fourth control circuit 40 may include a fourth transistor T4 and a fifth transistor T5. The control electrode of the fourth transistor T4 is connected to the second node N2, the first electrode is connected to the seventh node N7, and the second electrode is connected to the first clock terminal CK1. The control electrode of the fifth transistor T5 is connected to the second node N2, the first electrode of the fifth transistor T5 is connected to the first node N1, and the second electrode of the fifth transistor T5 is connected to the second power supply terminal V2.

[0106] In some embodiments, the first output circuit 50 may include a twelfth transistor T12 and a first capacitor C1, wherein the control electrode of the twelfth transistor T12 is connected to the first node N1, the first electrode is connected to the clock power supply terminal CKBO, and the second electrode is connected to the output terminal AZOUT. The two ends of the first capacitor C1 are connected to the first node N1 and the output terminal AZOUT, respectively.

[0107] The second output circuit 60 may include: a thirteenth transistor T13, whose control electrode is connected to the second node N2, its first electrode is connected to the first power supply terminal V1, and its second electrode is connected to the output terminal AZOUT.

[0108] The third output circuit 70 may include: a fourteenth transistor T14, whose control electrode is connected to the third node N3, its first electrode is connected to the output terminal AZOUT, and its second electrode is connected to the second power supply terminal V2.

[0109] Figure 4 This is a timing diagram of a shift register provided in some embodiments of this disclosure. Figure 5 A schematic diagram of the on / off state of each transistor in a shift register in the first stage, provided for some embodiments of this disclosure. Figure 6 A schematic diagram of the on / off states of each transistor in a shift register in the second stage, provided for some embodiments of this disclosure. Figure 7 A schematic diagram illustrating the on / off states of each transistor in a shift register during the third stage, provided for some embodiments of this disclosure. Figure 8 A schematic diagram illustrating the on / off states of each transistor in a shift register during the fourth stage, provided for some embodiments of this disclosure. Figure 9 This is a schematic diagram illustrating the on / off states of each transistor in a shift register during the fifth stage, provided for some embodiments of this disclosure. The following is in conjunction with... Figures 3 to 9 The operation of the shift register in the embodiments of this disclosure is described below. The example given is that the transistors in the shift register are P-type transistors. In this case, the low-level signal serves as the first-level signal, and the high-level signal serves as the second-level signal. Figures 5 to 9 In the diagram, a slash above a transistor indicates that the transistor is off.

[0110] In the first stage t1, both the input terminal IN and the first clock terminal CK1 provide low-level signals, while the second clock terminal CK2, the third clock terminal CK3, and the clock power supply terminal CKBO all provide high-level signals. At this time, the first transistor T1 is turned on, and the low-level signal at the input terminal IN is transmitted to the seventh node N7, thereby controlling the second transistor T2 to turn on. The high-level signal at the second clock terminal CK2 is transmitted to the fourth node N4. Meanwhile, the first node N1 and the second node N2 maintain the high-level potential from the previous stage; under the voltage regulation of the third capacitor C3, the third node N3 maintains the low-level potential from the previous stage, thereby turning on the fourteenth transistor T14, and the high-level signal at the second power supply terminal V2 is transmitted to the output terminal AZOUT. All other transistors are turned off.

[0111] In the second stage t2, the input terminal IN and the second clock terminal CK2 provide low-level signals, while the first clock terminal CK1 and the third clock terminal CK3 provide high-level signals, and the clock power supply terminal CKBO provides a high-level signal. At this time, the first transistor T1 is off; the seventh node N7 initially maintains the low-level potential of the previous stage, thus turning on the second transistor T2. The low-level signal from the second clock terminal CK2 is transmitted to the fourth node N4. Under the bootstrap effect of the fifth capacitor C5, the potential of the seventh node N7 further decreases, ensuring the second transistor T2 remains on. Additionally, the third transistor T3 is turned on under the control of the low-level signal provided by the second clock terminal CK2, thus transmitting the low-level signal from the fourth node N4 to the first node N1. At this time, the twelfth transistor T12 is turned on, transmitting the low-level signal from the clock power supply terminal CKBO to the output terminal AZOUT. During the phase of the clock power supply terminal CKBO's potential decrease, under the bootstrap effect of the first capacitor C1, the potential of the first node N1 further decreases, ensuring that the output terminal AZOUT outputs a scan signal with a short falling edge time.

[0112] Additionally, in the second stage t2, the seventh transistor T7 is turned on under the control of the low-level signal at the second clock terminal CK2. The low-level signal at the first power supply terminal V1 is transmitted to the sixth node N6, thereby turning on the ninth transistor T9. The fifteenth transistor T15 is turned on under the control of the low-level signal at the second clock terminal CK2, thereby transmitting the low-level signal at the input terminal IN to the control electrode of the eleventh transistor T11, causing the eleventh transistor T11 to turn on. The high-level signal at the second power supply terminal V2 is transmitted to the third node N3, and the fourteenth transistor T14 is turned off, ensuring that the signal at the second power supply terminal V2 does not affect the output terminal AZOUT.

[0113] In the third stage t3, the input terminal IN and the third clock terminal CK3 provide low-level signals, while the first clock terminal CK1, the second clock terminal CK2, and the clock power terminal CKBO provide high-level signals. At this time, the sixth transistor T6 is turned on under the control of the low-level signal at the third clock terminal CK3. The low-level signal at the input terminal IN is transmitted to the second node N2, thereby controlling the fifth transistor T5 to turn on. The high-level signal at the second power terminal V2 is transmitted to the first node N1, thereby controlling the twelfth transistor T12 to turn off, and simultaneously charging the first capacitor C1. Simultaneously, under the control of the low-level signal at the second node N2, the thirteenth transistor T13 is turned on, thereby transmitting the low-level signal at the first power terminal V1 to the output terminal AZOUT. Additionally, the eighth transistor T8 is turned on under the control of the low-level signal at the second node N2, and the high-level signal at the second clock terminal CK2 is transmitted to the sixth node N6. The remaining transistors are turned off.

[0114] During the first hold phase t11, the input terminal IN, the first clock terminal CK1, and the clock power supply terminal CKBO all provide low-level signals, while the second clock terminal CK2 and the third clock terminal CK3 both provide high-level signals. At this time, the first transistor T1 is turned on, and the low-level signal at the input terminal IN is transmitted to the seventh node N7, thereby controlling the second transistor T2 to turn on. The high-level signal at the second clock terminal CK2 is transmitted to the fourth node N4. Meanwhile, the second node N2 maintains the low-level potential from the previous phase, thereby controlling the fifth transistor T5 and the thirteenth transistor T13 to turn on. The high-level signal at the second power supply terminal V2 is transmitted to the first node N1, thereby keeping the twelfth transistor T12 off. Simultaneously, the thirteenth transistor T13 transmits the low-level signal at the first power supply terminal V1 to the output terminal AZOUT. Furthermore, under the control of the second node N2, the eighth transistor T8 is turned on, and the high-level signal at the second clock terminal CK2 is transmitted to the sixth node N6. Meanwhile, the third node N3, under the voltage regulation of the third capacitor C3, maintains the high-level potential from the previous phase, controlling the fourteenth transistor T14 to remain off. During the first holding phase t11, the first transistor T1, the fourth transistor T4, the fifth transistor T5, the eighth transistor T8, and the thirteenth transistor T13 are turned on, while the remaining transistors are turned off.

[0115] During the second hold phase t12, the input terminal IN and the second clock terminal CK2 provide low-level signals, while the first clock terminal CK1, the third clock terminal CK3, and the clock power supply terminal CKBO provide high-level signals. At this time, the second node N2 maintains the low-level potential from the previous phase, thereby turning on the fourth transistor T4, the fifth transistor T5, the eighth transistor T8, and the thirteenth transistor T13. Because the fourth transistor T4 is turned on, the high-level signal of the first clock terminal CK1 is transmitted to the seventh node N7. Because the fifth transistor T5 is turned on, the high-level signal of the second power supply terminal V2 is transmitted to the first node N1, thereby charging the first capacitor C1 and controlling the twelfth transistor T12 to remain off. Simultaneously, the third transistor T3 is turned on under the control of the low-level signal of the second clock terminal CK2, transmitting the high-level signal of the first node N1 to the fourth node N4. Furthermore, because the thirteenth transistor T13 is turned on, the low-level signal of the first power supply terminal V1 is transmitted to the output terminal AZOUT. Because the eighth transistor T8 is turned on, the low-level signal of the second clock terminal CK2 is transmitted to the sixth node N6. Simultaneously, the seventh transistor T7 is turned on under the control of the low-level signal of the second clock terminal CK2, thereby transmitting the low-level signal of the first power supply terminal V1 to the sixth node N6. This controls the ninth transistor T9 to turn on, and subsequently transmits the high-level signal of the third clock terminal CK3 to the fifth node N5, charging the fourth capacitor C4. Furthermore, the fifth transistor T5 is turned on under the control of the low-level signal of the second clock terminal CK2, thereby transmitting the low-level signal of the input terminal IN to the control electrode of the eleventh transistor T11, controlling the eleventh transistor T11 to turn on. This, in turn, transmits the high-level signal of the second power supply terminal V2 to the third node N3, ensuring that the fourteenth transistor T14 is in the off state.

[0116] During the third hold phase t13, the input terminal IN, the third clock terminal CK3, and the clock power supply terminal CKBO provide low-level signals, while the first clock terminal CK1 and the second clock terminal CK2 provide high-level signals. During the third hold phase t13, the switching states of each transistor are the same as in the third phase t3, and the output terminal AZOUT outputs a low-level signal. Further details are omitted here.

[0117] During the fourth hold phase t14, the input terminal IN and the first clock terminal CK1 provide low-level signals, while the second clock terminal CK2, the third clock terminal CK3, and the clock power supply terminal CKBO all provide high-level signals. During the fourth hold phase t14, the switching states of each transistor are the same as in the first hold phase t11, and the output terminal AZOUT outputs a low-level signal. Further details are omitted here.

[0118] During the fifth hold phase t15, the input terminal IN, the second clock terminal CK2, and the clock power supply terminal CKBO provide low-level signals, while the first clock terminal CK1 and the third clock terminal CK3 provide high-level signals. During the fifth hold phase t15, the switching states of each transistor are the same as in the second hold phase t12, and the output terminal AZOUT outputs a low-level signal; further details are omitted here.

[0119] During the sixth hold phase t16, the input terminal IN and the third clock terminal CK3 provide low-level signals, while the first clock terminal CK1, the second clock terminal CK2, and the clock power supply terminal CKBO provide high-level signals. At this time, the switching states of each transistor are the same as in the third phase t3, and the output terminal AZOUT outputs a low-level signal. Further details are omitted here.

[0120] During the seventh hold phase t17, the input terminal IN, the first clock terminal CK1, and the clock power supply terminal CKBO all provide low-level signals, while the second clock terminal CK2 and the third clock terminal CK3 both provide high-level signals. At this time, the switching states of each transistor are the same as in the first hold phase t11, and the output terminal AZOUT outputs a low-level signal. Further details are omitted here.

[0121] In the fourth stage t4, the input terminal IN, the first clock terminal CK1, the third clock terminal CK3, and the clock power terminal CKBO provide high-level signals, while the second clock terminal CK2 provides a low-level signal. At this time, the second node N2 maintains the low-level state of the previous stage, thereby controlling the fourth transistor T4, the fifth transistor T5, the thirteenth transistor T13, and the eighth transistor T8 to conduct. Because the fourth transistor T4 is conducting, the high-level signal of the first clock terminal CK1 is transmitted to the seventh node N7 to control the second transistor T2 to turn off. Because the fifth transistor T5 is conducting, the high-level signal of the second power terminal V2 is transmitted to the first node N1, thereby controlling the twelfth transistor T12 to remain off. Because the thirteenth transistor T13 is conducting, the low-level signal of the first power terminal V1 is transmitted to the output terminal AZOUT. Because the eighth transistor T8 is conducting, the low-level signal of the second clock terminal CK2 is transmitted to the sixth node N6. Simultaneously, transistors T3, T7, and T15 are turned on under the control of the second clock terminal CK2. Transistor T7 transmits the low-level signal from the first power supply terminal V1 to the sixth node N6, thereby controlling transistor T9 to turn on, and the high-level signal from the third power supply terminal is transmitted to the fifth node N5. Transistor T15 transmits the high-level signal from the input terminal IN to the gate of transistor T11, and N3 remains in the high-level state of the previous stage.

[0122] In the fifth stage t5, the input terminal IN, the first clock terminal CK1, and the second clock terminal CK2 provide high-level signals, while the third clock terminal CK3 and the clock power supply terminal CKBO provide low-level signals. At this time, under the control of the low-level signal at the third clock terminal CK3, the sixth transistor T6, the ninth transistor T9, and the tenth transistor T10 are turned on. Because the sixth transistor T6 is turned on, the high-level signal at the input terminal IN is transmitted to the second node N2, thereby controlling the fourth transistor T4, the fifth transistor T5, the thirteenth transistor T13, and the eighth transistor T8 to turn off. Under the voltage holding effect of the fifth capacitor C5, the seventh node N7 maintains the high-level state of the previous stage, thus keeping the second transistor T2 off. The first node N1 maintains the high-level state of the previous stage under the action of the first capacitor C1, thereby controlling the twelfth transistor T12 to remain off. In addition, since both the ninth transistor T9 and the tenth transistor T10 are turned on, the low-level signal of the third clock terminal CK3 is transmitted to the third node N3, thereby controlling the fourteenth transistor T14 to turn on, and then transmitting the high-level signal of the second power supply terminal V2 to the output terminal AZOUT.

[0123] As can be seen from the above working process of the shift register, by controlling the duration of the low-level signal input at the IN terminal, the duration of the low-level signal output at the AZOUT terminal can be controlled. For example, the various holding stages between the third stage t3 and the fourth stage t4 can be set according to actual needs. One or more holding stages can be selected, or each holding stage can be omitted, or more holding stages can be added.

[0124] Figure 10 This is a schematic diagram of a shift register provided in some other embodiments of this disclosure. Figure 11 for Figure 10 The timing diagram of the shift register shown is as follows: Figure 10 As shown, the structure of the shift register is similar to... Figure 3 The shift registers in the text have similar structures, the only difference being that... Figure 10 In this system, all transistors are N-type transistors. Accordingly, in the timing diagram of the shift register, the high-level signal is used as the first-level signal, and the low-level signal is used as the second-level signal. Figure 11 Timing of each signal in the middle Figure 4 The potentials are opposite. Figure 10 The working process of the shift register in Figure 3 The same applies, so I won't go into details here.

[0125] This disclosure also provides a driving method for the above-mentioned shift register. Figure 12 This is a schematic diagram of a shift register driving method provided in some embodiments of this disclosure, such as... Figure 12 As shown, the driving method includes:

[0126] S1. In the first stage, the input terminal and the first clock terminal provide a first level signal, and the second clock terminal and the third clock terminal provide a second level signal; the input circuit transmits the signal from the first clock terminal to the seventh node, the third control circuit controls the third node to maintain the first level potential of the previous stage, and the third output circuit transmits the signal from the second power supply terminal to the output terminal.

[0127] S2. In the second stage, the input terminal and the second clock terminal provide a first level signal, the first clock terminal and the third clock terminal provide a second level signal, and the clock power supply terminal provides a first level signal; the first control circuit transmits the signal from the second clock terminal to the first node N1, and the first output circuit transmits the first level signal from the clock power supply terminal to the output terminal.

[0128] S3. In the third stage, the input terminal and the third clock terminal provide a first level signal, and the first clock terminal and the second clock terminal provide a second level signal; the second control circuit transmits the signal from the input terminal to the second node N2, and the second output circuit transmits the signal from the first level terminal to the output terminal.

[0129] S4. In the fourth stage, the input terminal, the first clock terminal, and the third clock terminal provide a second level signal, the second clock terminal provides a first level signal, and the second output circuit transmits the signal from the first power supply terminal to the output terminal.

[0130] S5. In the fifth stage, the input terminal, the first clock terminal, and the second clock terminal provide a second level signal, and the third clock terminal provides a first level signal; the third control circuit transmits the first level signal of the third clock terminal to the third node, and the third output circuit transmits the signal of the second power supply terminal to the output terminal.

[0131] The specific working process of the shift register is described above and will not be repeated here.

[0132] This disclosure also provides a gate driving circuit comprising multiple cascaded shift registers, each shift register employing the structure described in the above embodiments. In adjacent shift register stages, the output of the previous stage shift register is connected to the input of the next stage shift register.

[0133] In addition, the clock signals input to the clock power supply in adjacent stages are out of phase.

[0134] This disclosure also provides a display device including the gate driving circuit described above. The display device may further include a display substrate, which is particularly suitable for OLED display substrates.

[0135] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. A shift register, characterized in that, include: The input circuit is configured to transmit the input signal to the seventh node in response to a first level signal at the first clock terminal. The first control circuit is configured to transmit the signal from the second clock terminal to the first node in response to the first level signal of the second clock terminal and the first level signal of the seventh node. The second control circuit is configured to transmit the input signal to the second node in response to the first level signal at the third clock terminal. The third control circuit is configured to provide a signal to the third node in response to the signal at the input terminal, the signal at the second clock terminal, and the signal at the third clock terminal. The first output circuit is configured to transmit a signal from the clock power supply terminal to the output terminal in response to a first level signal of the first node. The second output circuit is configured to transmit a signal from the first power supply terminal to the output terminal in response to a first level signal of the second node. The first power supply terminal is used to provide a first level signal; The third output circuit is configured to transmit the signal from the second power supply terminal to the output terminal in response to the first level signal of the third node. The second power supply terminal is used to provide a second level signal.

2. The shift register according to claim 1, characterized in that, The input circuit includes: The first transistor has its control electrode connected to the first clock terminal, its first electrode connected to the input terminal, and its second electrode connected to the seventh node.

3. The shift register according to claim 1, characterized in that, The first control circuit includes: The second transistor has its control electrode connected to the seventh node, its first electrode connected to the second clock terminal, and its second electrode connected to the fourth node. The third transistor has its control electrode connected to the second clock terminal, its first electrode connected to the fourth node, and its second electrode connected to the first node. The fifth capacitor has its two ends connected to the seventh node and the fourth node, respectively.

4. The shift register according to claim 1, characterized in that, The shift register also includes: The fourth control circuit is configured to transmit the signal from the first clock terminal to the seventh node and the signal from the second power supply terminal to the first node in response to the first level signal of the second node.

5. The shift register according to claim 4, characterized in that, The fourth control circuit includes: The fourth transistor has its control electrode connected to the second node, its first electrode connected to the seventh node, and its second electrode connected to the first clock terminal. The fifth transistor has its control electrode connected to the second node, its first electrode connected to the first node, and its second electrode connected to the second power supply terminal.

6. The shift register according to any one of claims 1 to 5, characterized in that, The second control circuit includes: The sixth transistor has its control electrode connected to the third clock terminal, its first electrode connected to the input terminal, and its second electrode connected to the second node; The second capacitor has its two ends connected to the second node and the first power supply terminal, respectively.

7. The shift register according to any one of claims 1 to 5, characterized in that, The third control circuit includes: A first control sub-circuit is configured to transmit a signal from the first power supply terminal to the sixth node in response to a first level signal from the second clock terminal; and to transmit a signal from the second clock terminal to the sixth node in response to a first level signal from the second node. The second control sub-circuit is configured to transmit the signal of the third clock terminal to the third node in response to the first level signal of the sixth node and the first level signal of the third clock terminal. The third control sub-circuit is configured to transmit the signal from the second power supply terminal to the third node in response to the first level signal at the input terminal and the first level signal at the second clock terminal. The storage sub-circuit is configured to maintain the voltage between the third node and the second power supply terminal when the third node is floating.

8. The shift register according to claim 7, characterized in that, The first control sub-circuit includes: The seventh transistor has its control electrode connected to the second clock terminal, its first electrode connected to the first power supply terminal, and its second electrode connected to the sixth node; The eighth transistor has its control electrode connected to the second node, its first electrode connected to the second clock terminal, and its second electrode connected to the sixth node.

9. The shift register according to claim 7, characterized in that, The second control sub-circuit includes: The ninth transistor has its control electrode connected to the sixth node and its first electrode connected to the third clock terminal; The fourth capacitor has its two ends connected to the sixth node and the second terminal of the ninth transistor, respectively. The tenth transistor has its control electrode connected to the third clock terminal, its first electrode connected to the second electrode of the ninth transistor, and its second electrode connected to the third node.

10. The shift register according to claim 7, characterized in that, The third control sub-circuit includes: The fifteenth transistor has its control electrode connected to the second clock terminal and its first electrode connected to the input terminal. The eleventh transistor has its control electrode connected to the second electrode of the fifteenth transistor, and the first electrode of the eleventh transistor is connected to the second power supply terminal; the second electrode of the eleventh transistor is connected to the third node.

11. The shift register according to claim 7, characterized in that, The storage sub-circuit includes a third capacitor, the two ends of which are respectively connected to the third node and the second power supply terminal.

12. The shift register according to any one of claims 1 to 5, characterized in that, The first output circuit includes: The twelfth transistor has its control electrode connected to the first node, its first electrode connected to the clock power supply terminal, and its second electrode connected to the output terminal. The first capacitor has its two ends connected to the first node and the output terminal, respectively.

13. The shift register according to any one of claims 1 to 5, characterized in that, The second output circuit includes a thirteenth transistor, whose control electrode is connected to the second node, its first electrode is connected to the first power supply terminal, and its second electrode is connected to the output terminal.

14. The shift register according to any one of claims 1 to 5, characterized in that, The third output circuit includes: a fourteenth transistor, whose control electrode is connected to the third node, its first electrode is connected to the output terminal, and its second electrode is connected to the second power supply terminal.

15. A method for driving a shift register as described in any one of claims 1 to 14, characterized in that, include: In the first stage, the input terminal and the first clock terminal provide a first level signal, and the second clock terminal and the third clock terminal provide a second level signal; The input circuit transmits the signal from the first clock terminal to the seventh node, and the third output circuit transmits the signal from the second power supply terminal to the output terminal. In the second stage, the input terminal and the second clock terminal provide a first level signal, the first clock terminal and the third clock terminal provide a second level signal, and the clock power supply terminal provides a first level signal; The first control circuit transmits the signal from the second clock terminal to the first node, and the first output circuit transmits the first level signal from the clock power supply terminal to the output terminal. In the third stage, the input terminal and the third clock terminal provide a first level signal, and the first clock terminal and the second clock terminal provide a second level signal; The second control circuit transmits the signal from the input terminal to the second node, and the second output circuit transmits the signal from the first power supply terminal to the output terminal. In the fourth stage, the input terminal, the first clock terminal, and the third clock terminal provide a second level signal, and the second clock terminal provides a first level signal. The second output circuit transmits the signal from the first power supply terminal to the output terminal; In the fifth stage, the input terminal, the first clock terminal, and the second clock terminal provide a second level signal, and the third clock terminal provides a first level signal; The third control circuit transmits the first level signal of the third clock terminal to the third node, and the third output circuit transmits the signal of the second power supply terminal to the output terminal.

16. A gate driving circuit, characterized in that, Includes multiple cascaded shift registers as described in any one of claims 1 to 14.

17. A display device, characterized in that, Includes the gate drive circuit as described in claim 16.

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