Storage system and memory control method

Abstract

Embodiments provide a storage system and a memory control method that enable high-speed reading. The storage system includes a memory that can hold data of a bit number of 2 bits or more in each of a plurality of storage units; and a storage controller that performs control of writing data to each of the storage units and control of reading out data written to each of the storage units, the storage controller performing first write control when a first command is received from a host, the first write control being control of reading out data that is a target of the first command from the memory and writing the read-out data to the memory in a write mode corresponding to a bit number smaller than a bit number corresponding to a write mode at the time of writing the read-out data; and reading out data written to the memory by the first write control and transmitting the data to the host when a read command for data that is a target of the first command is received from the host.

Description

[0001] This application enjoys priority over Japanese Patent Application No. 2021-152518 (filed on September 17, 2021). This application is incorporated herein by reference to the entire contents of that earlier application. Technical Field

[0002] Embodiments of the present invention relate to a storage system and a memory control method. Background Technology

[0003] In recent years, three-dimensional structures have been realized in semiconductor memory devices such as NAND flash memory to meet the requirements of miniaturization and large capacity. Furthermore, in these semiconductor memory devices, there are not only SLC (Single Level Cell) devices where the memory cell transistors can hold 1 bit (2 values) of data, but also MLC (Multi Level Cell) devices that can hold 2 bits (4 values), TLC (Triple Level Cell) devices that can hold 3 bits (8 values), QLC (Quad Level Cell) devices that can hold 4 bits (16 values), and PLC (Penta Level Cell) devices that can hold 5 bits (32 values).

[0004] However, because the memory cell transistors are multi-valued, the maximum read performance is reduced, and sometimes high-speed data transfer is not possible regardless of the increase in host interface speed. Summary of the Invention

[0005] The purpose of this embodiment is to provide a storage system and a memory control method capable of high-speed reading.

[0006] The storage system of the embodiment includes: a memory having multiple storage cells, each of which can hold data of 2 bits or more; and a storage controller that controls writing data to each storage cell in a write mode corresponding to the number of bits of data that can be written to each storage cell of the memory, and controls reading data written to each storage cell. When the storage controller receives a first command from a host, it performs a first write control, which is as follows: reading data that has become the object of the first command from the memory, and writing the read data back into the memory in a write mode corresponding to a number of bits smaller than the number of bits corresponding to the write mode when the read data was written; when receiving a read command from the host for data that has become the object of the first command, reading the data written to the memory by the first write control and transmitting it to the host. Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating a memory system constructed from the semiconductor device of this embodiment.

[0008] Figure 2 It means Figure 1 A block diagram illustrating an example of the specific configuration of the storage controller in the diagram.

[0009] Figure 3 This is a block diagram illustrating an example of the configuration of memory chip 4.

[0010] Figure 4 This is an illustrative diagram showing an example of the command format used to implement the high-speed read preparation command and the write-back command described later.

[0011] Figure 5 This is the timing chart for readout in the first embodiment.

[0012] Figure 6 This is a timing diagram for writing and reading in the comparative example.

[0013] Figure 7 It is a memory map used to describe the memory areas of memory chip 4.

[0014] Figure 8 This is a flowchart illustrating the operation of the first embodiment.

[0015] Figure 9 This is a flowchart illustrating the action flow used in the second embodiment.

[0016] Figure 10 This is a block diagram representing a variation.

[0017] Figure 11 It means Figure 10 The flowchart of the action of the variant example.

[0018] Figure 12 This is a flowchart representing a variation.

[0019] Label Explanation

[0020] 1 Storage system, 2 Host, 2a CPU, 3 Storage controller, 4 Storage chip, 11 CPU, 12 ROM, 13 RAM, 13a LUT, 13b LUTS, 14 ECC circuit, 15 Host I / F circuit, 16 Memory I / F circuit, 17 Internal bus, 21 NAND I / O interface, 22 Control circuit, 23 NAND memory cell array, 24 Bit line driver, 25 Word line driver, 26 Voltage generation circuit. Detailed Implementation

[0021] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0022] This implementation modifies the recorded data to a smaller tR write mode according to the request from the host, thereby improving the performance during reading.

[0023] The amount of information recorded by a single memory cell transistor in NAND flash memory tends to increase from 1 bit (SLC) to 2 bits (MLC), 3 bits (TLC), 4 bits (QLC), and 5 bits (PLC). As the amount of information that can be stored in a single memory cell transistor increases, it becomes possible to ensure the required capacity of the device with a smaller number of cells, thus reducing chip size and cost. However, the more multi-valued the technology becomes—that is, the more bits of information (hereinafter referred to as cell bits) are recorded in a single memory cell transistor—the more types of read voltages are required to read 1 bit of data from a single memory cell transistor. This increases the time (tR) until the data is transmitted to the host in response to a request from the host.

[0024] Furthermore, tR is a parameter of the memory cell transistor corresponding to the type of NAND memory. When tR increases, the limit performance of reading out the amount of data that can be read per unit time (hereinafter referred to as the limit read performance) decreases. The limit read performance of the memory device is determined by the multiplication operations (1) to (3) below.

[0025] (1) For a single read request, determine the amount of data (page size) read from each die of the NAND flash memory.

[0026] (2) The reciprocal of tR

[0027] (3) Number of NAND dies per device

[0028] In recent years, the speed of the interface between storage devices and the host (host interface) has been continuously improving. Conversely, when tR increases due to multi-valued technologies, the maximum read performance of the storage device may be lower than the speed of the host interface. Therefore, data transfer during reads between the host and the storage device is limited by the storage device's maximum read performance.

[0029] Therefore, to improve the ultimate read performance, increasing the page size in (1) or increasing the number of dies in (3) are considered. However, increasing the page size in (1) would increase the cost of NAND flash memory dies, making it difficult to implement. In addition, when increasing the number of dies in (3) is adopted, the capacity of the storage device increases, but increasing the number of dies to increase capacity based on product demand is not an appropriate response. Furthermore, when it is desired to increase the number of dies without changing the device capacity, it would result in the use of NAND flash memory with smaller die capacity, thus increasing costs.

[0030] In addition, to improve the maximum read performance of the storage device, the method of increasing the reciprocal of tR in (2) is also considered. Even for the same storage device, multiple write modes with different numbers of bits per cell can be used. For example, for the same storage device, data can be written using the write mode corresponding to QLC or the write mode corresponding to SLC. Therefore, when recording data, a write mode with a smaller tR, that is, a write mode with a smaller number of bits per cell, is used. However, in order to reduce tR, for example, when using the write mode with the smallest tR (smallest number of bits per cell), i.e., SLC, to record data, there is a problem that the capacity that can be recorded will be reduced.

[0031] Therefore, in this embodiment, a writing method with a larger number of bits per cell than SLC is used for recording during writing, and when reading data, the data is re-recorded according to the request from the host using a writing method with a smaller number of bits per cell, thereby improving the ultimate read performance of the storage device during reading.

[0032] (Storage system composition)

[0033] Figure 1 This is a block diagram illustrating a memory system constructed from the semiconductor device of this embodiment. Additionally, Figure 2 It means Figure 1 A block diagram illustrating an example of the specific configuration of the storage controller in the diagram.

[0034] The storage system 1 of this embodiment includes a storage controller 3 and four storage chips 4A to 4D (hereinafter, without distinguishing between the four storage chips 4A to 4D, they are representatively referred to as storage chips 4). The number of storage chips 4 is not limited to four; any number of storage chips, including one or more, can be used. Furthermore, the storage controller 3 and the storage chips 4 constitute a storage device.

[0035] Storage system 1 can be connected to host 2. Host 2 is an electronic device such as a personal computer, portable terminal, vehicle-mounted device, server, etc. Host 2 has a central processing unit (CPU) 2a as a processor, ROM (not shown), and DRAM 2b. Storage system 1 stores data (hereinafter referred to as data) from host 2 in each memory chip 4 according to requests from host 2, and reads the data stored in each memory chip 4 and outputs it to host 2. Specifically, storage system 1 can write data to each memory chip 4 according to write requests from host 2, and read data from each memory chip 4 according to read requests from host 2.

[0036] Storage system 1 can be either a UFS (Universal Flash Storage) device consisting of a storage controller 3 and multiple storage chips 4 packaged together, or an SSD (Solid State Drive). Figure 1 In the image, storage system 1 is shown connected to host 2.

[0037] Memory chip 4 is a semiconductor storage device composed of NAND flash memory, which stores data non-volatilely. For example... Figure 1 As shown, the storage controller 3 and each storage chip 4 are connected via a NAND bus. The storage controller 3 controls the writing of data to the storage chips 4 based on write requests from the host 2. Additionally, the storage controller 3 controls the reading of data from the storage chips 4 based on read requests from the host 2. Sometimes, the storage controller 3 controls the writing and reading of data from the storage chips 4 spontaneously, not based on requests from the host 2.

[0038] exist Figure 2In this configuration, the storage controller 3 includes a CPU 11, a ROM 12, a RAM (Random Access Memory) 13, an ECC (Error Check and Correct) circuit 14, a host interface (I / F) circuit 15, and a memory I / F circuit 16. The CPU 11, ROM 12, RAM 13, ECC circuit 14, host I / F circuit 15, and memory I / F circuit 16 are interconnected via an internal bus 17.

[0039] The host I / F circuit 15 receives data from the host 2 and outputs requests, write data, etc., contained in the received data to the internal bus 17. Additionally, the host I / F circuit 15 sends data read from the memory chip 4 and responses from the CPU 11 to the host 2. Furthermore, the host 2 also has an I / F circuit (not shown) corresponding to the host I / F circuit 15.

[0040] The host 2 and the host I / F circuit 15 are connected via a predetermined interface. For example, this interface can be a parallel interface of eMMC (embedded Multi Media Card), a serial expansion interface of PCIe (Peripheral Component Interconnect-Express), a high-speed serial interface of M-PHY, or other similar interfaces.

[0041] The memory I / F circuit 16 controls the processes of writing data to each memory chip 4 and reading data from each memory chip 4 based on the instructions of the CPU 11.

[0042] The CPU 11 provides overall control over the memory controller 3. The CPU 11, constituting the control circuit, may be, for example, a CPU (Central Processing Unit) or an MPU (Micro Processing Unit). When the CPU 11 receives a request from the host via the host I / F circuit 15, it performs control according to that request. For example, according to a request from the host, the CPU 11 instructs the memory I / F circuit 16 to write data to each of the memory chips 4. Additionally, according to a request from the host, the CPU 11 instructs the memory I / F circuit 16 to read data from each of the memory chips 4.

[0043] RAM13 temporarily stores data received from the host until it is stored in each of the memory chips 4, and temporarily stores data read from each of the memory chips 4 until it is sent to the host. RAM13 is, for example, a general-purpose memory such as SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory). In addition, a region LUT13a is provided in RAM13 to record the logic-to-physical translation table.

[0044] For data stored in RAM 13, CPU 11 determines the storage area (hereinafter referred to as storage area) on each memory chip 4. Data is stored in RAM 13 via internal bus 17. For example, CPU 11 determines the storage area for page data, which is written in page units.

[0045] Physical addresses are allocated to the storage areas of memory chip 4. CPU 11 uses physical addresses to manage the storage areas where data is written. CPU 11 specifies the physical address of the determined storage area and instructs memory I / F circuit 16 to write data to memory chip 4. CPU 11 stores a logic-to-physical translation table in area LUT13a of RAM 13. This logic-to-physical translation table represents the correspondence between the logical address of data (the logical address managed by the host) and the physical address where the data was written. When CPU 11 receives a read request containing a logical address from the host, it determines the physical address corresponding to the logical address and specifies the physical address to instruct memory I / F circuit 16 to read the data.

[0046] The ECC circuit 14 encodes the data stored in RAM 13 to generate codewords. Additionally, the ECC circuit 14 decodes the codewords read from each memory chip 4.

[0047] exist Figure 2 The diagram shows an example configuration where the memory controller 3 includes an ECC circuit 14 and a memory I / F circuit 16. However, the ECC circuit 14 can also be integrated into the memory I / F circuit 16. Alternatively, the ECC circuit 14 can also be integrated into each memory chip 4.

[0048] Upon receiving a write request based on a write command from host 2, memory controller 3 operates as follows: CPU 11 temporarily stores the write data in RAM 13. CPU 11 reads the data stored in RAM 13 and inputs it to ECC circuit 14. ECC circuit 14 encodes the input data and provides codewords to memory I / F circuit 16. Memory I / F circuit 16 writes the input codewords to each memory chip 4.

[0049] Upon receiving a read request based on a read command from host 2, memory controller 3 operates as follows: Memory I / F circuit 16 provides the codewords read from each memory chip 4 to ECC circuit 14. ECC circuit 14 decodes the input codewords and stores the decoded data in RAM 13. CPU 11 sends the data stored in RAM 13 to host 2 via host I / F circuit 15.

[0050] Figure 3 This is a block diagram illustrating an example configuration of memory chip 4. Memory chip 4 includes a NAND I / O interface 21, control circuitry 22, a NAND memory cell array 23, bit line drivers 24, and word line drivers 25. The NAND I / O interface 21 receives control signals output from the memory controller 3, such as write enable signal WEn, read enable signal REn, address latch enable signal ALE, and command latch enable signal CLE. Additionally, the NAND I / O interface 21 receives commands, addresses, and data output from the memory controller 3.

[0051] Bit line driver 24 is configured to independently apply voltage (or current) to multiple bit lines BL, and to independently detect the voltage (or current) of multiple bit lines BL.

[0052] The word line driver 25 is configured to independently apply voltage to multiple word lines and select gate lines.

[0053] The control circuit 22 receives control signals, commands, addresses, and data from the NAND I / O interface 21, and uses these to control the operation of the memory chip 4. For example, the control circuit 22 controls the word line driver 25 and the bit line driver 24 based on the control signals, commands, addresses, and data, and performs write operations, read operations, erase operations, etc.

[0054] The voltage supplied to the bit line driver 24 and word line driver 25 is generated by the voltage generation circuit 26. The voltage generation circuit 26 is controlled by the control circuit 22 to generate the required voltage. For example, the control circuit 22 controls the voltage generation circuit 26 to set the voltage applied to multiple word lines WL through the word line driver 25 and the voltage applied to multiple bit lines BL through the bit line driver 24 (bit line voltage). In this way, writing to, reading from, and erasing of memory cells (memory cell transistors) MT contained in the NAND memory cell array 23 are performed.

[0055] For example, when a write command is input, the control circuit 22 controls the bit line driver 24 and the word line driver 25 to write the data input along with the write command to the designated address on the NAND memory cell array 23. Conversely, when a read command is input, the control circuit 22 controls the bit line driver 24 and the word line driver 25 to read data from the designated address on the NAND memory cell array 23.

[0056] (Host commands)

[0057] When recording data, CPU2a of host 2 generates a write command, sending the logical address of the data (e.g., the starting address and data size) along with the data and the write command to the storage controller 3. Similarly, when reading data, CPU2a generates a read command, sending the logical address of the data (e.g., the starting address and data size) along with the read command to the storage controller 3. Furthermore, during data recording, write operations are typically performed in a manner that maximizes the number of bits per unit in the storage device.

[0058] Furthermore, in this embodiment, a high-speed read preparation command is generated by CPU2a at a predetermined time before reading data. The first command, the high-speed read preparation command, is a command used in the memory controller 3 to temporarily read data written in a write mode with a larger number of bits per unit, and then re-record it in a write mode with a smaller number of bits per unit (hereinafter referred to as high-speed read preparation mode). When sending the high-speed read preparation command, CPU2a sends information about the logical address of data with a high probability of being read to the memory controller 3.

[0059] For example, in game data, OS (operating system) data, there is data that is frequently used or data that needs to be read at a higher speed than other data. In addition, there are also situations where the data written is likely to be accessed immediately after being written (temporal location), and data whose address is adjacent to the address of the data being read is likely to be accessed (spatial location).

[0060] CPU2a has knowledge related to such data access and specifies the logical address of such data (hereinafter referred to as high-speed read data), and sends it to memory controller 3 along with a high-speed read preparation command.

[0061] Furthermore, recording using a writing method corresponding to SLC is also considered during writing. However, it's not only data that always requires high-speed reading; sometimes, depending on the characteristics of the program, data only needs high-speed reading at a certain time. The high-speed read preparation command in this embodiment is extremely effective when high-speed reading is desired during a specific period.

[0062] Figure 4 This is an illustrative diagram showing an example of the command format used to implement the high-speed read preparation command and the write-back command described later. Figure 4 The example envisions a UFS device.

[0063] In the UFS protocol, commands UPIU (UFS Protocol Information Unit) are used to send commands from the host to the device, but various types of commands are implemented using the CDB (Command Descriptor Block) of bytes

[16] to

[31] (bytes

[16] to

[31] ). Figure 4 The example is a format example of the CDB's high-speed read preparation command and write-back command.

[0064] The OPERATION CODE is the newly assigned command number. The MODE description includes information distinguishing between a "high-speed read preparation command" and a "write-back command." LOGICAL BLOCK ADDRESS represents the logical address. TRANSFER LENGTH represents the data size of the object.

[0065] For example, host 2 sends to storage controller 3 Figure 4 The high-speed read preparation command is shown in the format shown. When the CPU 11 of the memory controller 3 receives the high-speed read preparation command, it executes the high-speed read preparation mode. That is, the CPU 11 refers to the data expanded in LUT 13a and translates the logical address specified by the host 2 into a physical address. The CPU 11 sends the translated address and read command to the memory chip 4. As a result, the control circuit 22 of the memory chip 4 drives the bit line driver 24 and the word line driver 25 to read the data specified by the host 2 from the address specified by the memory controller 3 and send it to the memory controller 3. The CPU 11 stores the read data in RAM 13.

[0066] Furthermore, CPU 11 selects a write mode with a smaller number of bits per cell than the write mode used for high-speed data reading, and writes the data stored in RAM 13 to memory chip 4. In this case, CPU 11 specifies the address corresponding to the write mode. That is, CPU 11 converts the physical address of the read data into the physical address corresponding to the write mode, updates LUT 13a, and sends the physical address and write command to memory chip 4. Based on the specified address, the control circuit 22 of memory chip 4 drives the bit line driver 24 and word line driver 25 to write data in the specified write mode.

[0067] (effect)

[0068] Next, refer to Figures 5-8 The operation of this implementation method will be explained. Figure 5 This is a timing diagram showing the readout process in the first embodiment. Figure 6 This shows the timing diagrams for writing and reading in the comparative example. Additionally, Figure 7 This indicates the memory mapping used to describe the memory regions of memory chip 4. Figure 8 This is a flowchart illustrating the operation of the first embodiment.

[0069] First of all, Figure 6 The write and read operations of the comparative example shown will be explained. When writing, host 2 generates a write command, outputting the logical address (starting address (X) and data size (Y)) of the data to be written and the data to be written (write data) to storage controller 3. Figure 6 (1), (2)). The storage controller 3 updates the LUT13a by converting the logical address of the write data to the physical address through logical-to-physical translation, and sends the write data to the storage chip 4 by specifying the converted physical address. The storage chip 4 writes the write data to the storage area of ​​the NAND storage cell array 23 specified by the physical address. In addition, the storage controller 3 provides instructions to the storage chip 4 to write the write data in a write mode corresponding to a predetermined number of cell bits. For example, in the case of the storage chip 4 corresponding to QLC, the write is performed in the write mode corresponding to QLC ( Figure 6 (3) Multi-valued data writing).

[0070] Next, host 2 reads the data written to memory chip 4. In this case, host 2 generates a read command, outputting the logical address (starting address (X) and data size (Y)) of the data to be read to memory controller 3. Figure 6 (4)). The storage controller 3 refers to the information expanded in LUT13a, converts the logical address of the read data into a physical address, specifies the converted physical address, and reads the data from the storage chip 4. Figure 6 (5) Multi-value data readout). This data is written, for example, in a write mode with a large number of unit bits, such as QLC. The control circuit 22 of the memory chip 4 performs readout control corresponding to this write mode, obtains the read data, and sends it to the memory controller 3. The memory controller 3 transmits the received read data to the host 2 and returns a read response. Figure 6 (6), (7)). As mentioned above, when reading data written in a write mode with a large number of bits per unit, tR increases.

[0071] In this embodiment, the writing operation is the same as in the comparative example. The difference in this embodiment compared to the comparative example is that a high-speed read preparation mode is executed before the actual read operation. Figure 5 Only the actions during reading are shown. During reading, host 2 generates a high-speed read preparation command at a predetermined timing before the actual read. That is, host 2's CPU 2a sends the logical address (start address (X) and data size (Y)) of the data determined to be to be read at high speed (high-speed read data) and the high-speed read preparation command to the memory controller 3. Figure 5 (1)). The CPU11 of the storage controller 3 is in Figure 8 In S1, the CPU 11 is in a standby state indicating a high-speed read preparation mode. When the CPU 11 receives a high-speed read preparation command and a logical address (determined as "yes" in S1), it executes the high-speed read preparation mode. That is, the CPU 11 performs the following control (hereinafter referred to as read preparation control): referring to the information expanded in LUT 13a, it converts the received logical address into a physical address (S2), and specifies the converted physical address to read the data from the memory chip 4. The data to be read is written, for example, in a write mode with a large number of bits per cell, such as QLC, and the control circuit 22 of the memory chip 4 performs a read operation corresponding to this write mode. Figure 5 (2) Multi-value data readout), obtain high-speed read data, and transmit it to storage controller 3 (S4).

[0072] In the read preparation control, CPU 11 stores the received high-speed read data in RAM 13. CPU 11 further writes the high-speed read data (read through the read preparation control) to memory chip 4 using a write method that reduces the number of bits per cell (reducing tR). Figure 5 (3)). For example, if high-speed read data is written in a write mode corresponding to QLC during writing, it is written in a write mode corresponding to TLC, MLC, or SLC. The CPU 11 sets the storage area for rewriting the high-speed read data read by read-read control, and updates the LUT 13a accordingly. The CPU 11 sends the command for rewriting high-speed read data (hereinafter referred to as write-read control) along with the address of the write destination to the memory chip 4 (S6). The control circuit 22 of the memory chip 4 writes high-speed read data to the storage area of ​​the designated NAND memory cell array 23 (S7). In this case, the control circuit 22 controls each part to write in a write mode that reduces tR (reduced cell bit count). For example, it writes in a write mode corresponding to SLC.

[0073] Figure 7 This illustrates the storage areas before and after write control is prepared. Figure 7In the example, the NAND memory cell array 23 is configured with two memory areas: an SLC area for writing in a write mode corresponding to SLC and a QLC area for writing in a write mode corresponding to QLC. Furthermore, SLC / QLC write modes are configured as usage methods, but the areas used for each mode are not completely fixed. The SLC area includes a management area and a LUT area for the storage logic to physical table. For example, high-speed read data is written to area R4 in the QLC area during writing. In high-speed read preparation mode, the high-speed read data written to area R4 is read out by the storage controller 3 via read preparation control, for example, by write preparation control to area R3 in the SLC area. At the point when the high-speed read preparation mode completes, the physical address of the high-speed read data stored in LUT 13a becomes the physical address representing area R3.

[0074] When the readiness write control, which is the first write control, ends, the CPU 11 of the storage controller 3 generates a high-speed read preparation command response indicating that the high-speed read preparation mode has been completed, and sends it to the host 2. Figure 5 (4)). In addition, the high-speed read preparation command response can also be omitted by specifying the host 2.

[0075] Next, host 2 reads the high-speed data written to memory chip 4. In this case, host 2 generates a read command, outputting the logical address (starting address (X) and data size (Y)) of the high-speed data to be read to memory controller 3. Figure 5 (5)). The storage controller 3 is in a read command standby state in S8. When a read command is received (determined as "yes" in S8), referring to the information of LUT13a, the logical address of the high-speed read data is converted into a physical address, and the converted physical address is specified, for example in Figure 7 The value in S9 represents the physical address of region R3, and the data of memory chip 4 is output (S9, ...). Figure 5 (6)). The high-speed read data is written by preparing write control, for example, by a write method with a small number of unit bits such as SLC. The control circuit 22 of the memory chip 4 performs read control corresponding to the write method to obtain the high-speed read data. The control circuit 22 transmits the read high-speed read data to the memory controller 3. The memory controller 3 transmits the received high-speed read data to the host 2 and sends a read response to the host 2. Figure 5 (7), (8)). High-speed read data is written in a small tR (small number of bits per unit) write mode and can be read out at high speed.

[0076] Thus, in this embodiment, by re-recording the recorded data according to the request from the host by changing the write method to a smaller tR, the performance during reading can be improved. This prevents the data transfer speed from the storage device to the host from being limited by tR, thereby enabling high-speed data reading. Furthermore, by only targeting data specified by the host, adverse effects on the device's recordable capacity can be suppressed.

[0077] (Second Implementation)

[0078] Figure 9 This is a flowchart illustrating the action flow used in the second embodiment. Figure 9 China and Figure 8 The same steps are assigned the same labels and descriptions are omitted. The hardware structure of this embodiment is the same as that of the first embodiment, and descriptions are omitted.

[0079] In the first embodiment, read performance is improved by employing a high-speed read preparation mode. However, data recorded using a write method with a large number of bits per cell is re-recorded using a write method with a smaller number of bits per cell. Consequently, the recording density of the memory cell transistors decreases, and the capacity that the storage device can record decreases. Therefore, this embodiment controls the data so that data that no longer requires high-speed reading is written back using a write method with an even larger number of bits per cell.

[0080] Similar to the first embodiment, host 2 can issue a high-speed read preparation command, and issues a write-back command as a second command for writing back data set as high-speed read data in a write mode with a larger tR (larger number of bits per unit), such as a write mode during recording. Furthermore, when the storage area in storage controller 3 where high-speed read data is written via write preparation control is set as a predetermined area, host 2 can issue a write-back command without specifying the logical address corresponding to each individual high-speed read data. Additionally, in storage controller 3, when data is restored to normal read speed for each individual high-speed read data, host 2 issues a logical address specifying the high-speed read data to be written back along with the write-back command.

[0081] CPU11 of storage controller 3 Figure 9 In step S8, it is determined whether a read instruction has been generated. If there is no read request (determined as "No" in S8), step S10 determines whether there is a write-back instruction or a power-off instruction. If there is no write-back instruction or a power-off instruction (determined as "No" in S10), CPU11 returns the process to S8 to determine whether a read request has been generated.

[0082] Now, host 2 generates a write-back command and sends it to storage controller 3. When CPU 11 of storage controller 3 receives the write-back command (determined as "yes" in S10), it performs write-back control to write back the high-speed read data using a write method with a larger number of bits per unit. That is, CPU 11 specifies the physical address of the storage area of ​​the high-speed read data stored in LUT 13a in the write-back control and reads it (S11). CPU 11 saves the read data to RAM 13. Then, CPU 11 converts the physical address of the storage area of ​​the high-speed read data stored in LUT 13a to the physical address of the storage area corresponding to the write method with a larger number of bits per unit, and updates the contents of LUT 13a (S12). CPU 11 specifies the updated physical address and sends a write-back instruction for high-speed read data to storage chip 4 (S13).

[0083] The control circuit 22 of the memory chip 4 writes the data to be written back to the designated storage area of ​​the NAND memory cell array 23 (S14). In this case, the control circuit 22 controls each part to either increase tR (increase the number of bits per cell) or revert to the original writing mode. For example, in the case of the memory chip 4 corresponding to QLC, the writing is performed in the writing mode corresponding to QLC.

[0084] Furthermore, host 2 can also issue a write-back command before the power is disconnected when (instructed) to perform control so that all high-speed read data is re-recorded in a write mode with a larger number of bits per unit. Alternatively, storage controller 3 can also perform control before the power is disconnected when instructed to do so, even without receiving a write-back command, so that all high-speed read data is re-recorded in a write mode with a larger number of bits per unit. Figure 9 S10 represents an example in this case.

[0085] In addition, before the power is turned off, the CPU11 transfers the contents of LUT13a to the memory chip 4, so that it is stored in region R2 of the NAND memory cell array 23.

[0086] Thus, in this embodiment, by using write-back commands, the host can retain only the necessary data in a small tR (small number of bits per unit) write manner during the necessary period. This improves read performance while suppressing the impact on the overall capacity of the storage device.

[0087] (Modified Example)

[0088] Figure 10 This is a block diagram representing a variation. In Figure 10 China and Figure 2 The same constituent elements are assigned the same label and their descriptions are omitted.

[0089] In the second embodiment, by performing read preparation control, high-speed read data recorded in a write mode with a large number of bits per unit is read out in a state where it cannot be used later (hereinafter referred to as read in move mode). However, when considering write-back control, it is also possible to perform read-back in a state where the area is retained and cannot be erased, even for high-speed read data recorded in a write mode with a large number of bits per unit (hereinafter referred to as read in copy mode). Therefore, in this embodiment, during read preparation control, the storage area for high-speed read data recorded in a write mode with a large number of bits per unit is stored; during write-back control, for example, the SLC area where high-speed read data is recorded is made erasable, and the LUT13a is updated using the information of the stored storage area. For example, the CPU11 enables read in copy mode by storing information about the correspondence between the physical address and logical address of the storage area for high-speed read data recorded in a write mode with a large number of bits per unit in the region LUTS13b of RAM13. Furthermore, CPU11 uses information from LUT13b to update LUT13a during write-back control.

[0090] Figure 11 This is a flowchart illustrating the actions taken in this situation. Figure 11 China and Figure 8 The same steps are assigned the same labels and the explanations are omitted.

[0091] like Figure 11 As shown, when performing a read based on read preparation control, CPU 11 registers the correspondence between the physical address and logical address of the read operation in LUTS 13b (S21). Additionally, CPU 11 updates LUT 13a using the physical address of the write destination for write preparation control (S5). Thus, in subsequent high-speed read data reads, high-speed read data written in a small-bit-per-cell write mode is read. On the other hand, when CPU 11 receives a write-back command or a power-off indication (determined as "yes" in S10), it reads the correspondence between the physical address and logical address of the originally written high-speed read data from LUTS 13b and updates the physical address information of the physical address-logical address correspondence stored in LUT 13a (S22). Therefore, high-speed read data stored in the NAND memory cell array 23 in a large-bit-per-cell write mode is read later, mitigating the impact on the storage area capacity.

[0092] Thus, in this variant, by keeping the high-speed read data read through read preparation control in an erasure-free state during high-speed read preparation mode, even when write-back control is implemented, it is possible to deal with the issue by simply rewriting the logic-to-physical translation table, thus omitting the read and write operations used for write-back control.

[0093] Furthermore, in the above description, an example of reading in either the mobile mode or the copy mode was given for the storage controller 3, but these read modes can also be configured to be switchable. For example, the storage controller 3 can also be configured to dynamically switch between reading in copy mode when the free capacity is greater than a predetermined threshold and reading in mobile mode when the free capacity is less than the predetermined threshold.

[0094] Alternatively, for example, host 2 can attach an ID to the data, allowing the storage controller 3 to pre-specify high-speed read data subject to write-back control and high-speed read data not subject to write-back control when the power is off. In this case, storage controller 3 records the correspondence between ID, logical address, and physical address in RAM 13, and when a power-off indication is generated, it determines the high-speed read data subject to write-back control by referring to the ID.

[0095] (Modified Example)

[0096] Figure 12 This is a flowchart illustrating a variation. In the above embodiments, it was explained that when the CPU 11 performs write preparation control, it selects a write mode where tR is smaller (smaller number of bits) than the original write mode of the high-speed read data. This embodiment illustrates an example of this selection.

[0097] exist Figure 12 In this process, the CPU 11 obtains the original writing mode of the high-speed read data, that is, the writing mode of the high-speed read data recorded in the NAND memory cell array 23 before preparing read control (S31). For example, when the writing mode is set to be the writing mode corresponding to QLC, the writing mode corresponding to SLC, MLC or TLC becomes a candidate as the writing mode when preparing write control.

[0098] CPU 11 controls RAM 13 and host I / F circuit 15 to obtain information on host interface speed and free capacity of NAND memory cell array 23 (S32, S33). Based on the obtained information, CPU 11 determines the write mode when preparing write control (S34). That is, CPU 11 adopts a write mode that can obtain the tR (number of bits per cell) required to achieve the maximum read performance higher than the host interface speed. For example, as long as the maximum read performance higher than the host interface speed can be obtained, it does not have to be SLC, but can also adopt a write mode corresponding to TLC or MLC. In addition, if the CPU 11 cannot obtain a sufficiently high maximum read performance, it selects a write mode corresponding to SLC.

[0099] In addition, the CPU11 employs a write method that ensures sufficient free capacity. For example, if a write method corresponding to SLC, MLC, or TLC can achieve maximum read performance that is faster than the host interface speed, a write method with a larger free capacity can also be used depending on the available free capacity.

[0100] Thus, in this variant, it is possible to improve the ultimate read performance while ensuring sufficient free capacity.

[0101] This invention is not limited to the embodiments described above, and various modifications can be made during the implementation phase without departing from its spirit. Furthermore, since the above embodiments include inventions at various stages, various inventions can be extracted through appropriate combinations of multiple technical features. For example, if even if several technical features are deleted from all the technical features shown in the embodiments, the technical problem described in the "Technical Problem to be Solved by the Invention" column can be solved, and the effects described in the "Effects of the Invention" column can be obtained, then the configuration with the deleted technical features can be extracted as an invention.

Claims

1. A storage system comprising: A memory having multiple storage units, each of which can hold more than 2 bits of data; and A storage controller controls the writing of data to each storage cell in a manner corresponding to the number of bits of data that can be written to each storage cell of the memory, and controls the reading of data written to each storage cell. The storage controller When the first command is received from the host, the first write control is performed. The first write control is as follows: the data that has become the object of the first command is read from the memory, and the read data is written to the memory in a write method that is smaller than the number of bits corresponding to the write method when the read data is written. When a read command is received from the host for data that has become the object of the first command, the data written to the memory by the first write control is read and transmitted to the host.

2. The storage system according to claim 1, The storage controller performs a second write control upon receiving a second command from the host or upon receiving a power disconnection instruction. The second write control is as follows: reading the data written to the memory through the first write control, and writing the read data back to the memory using a write method corresponding to a number of bits larger than the number of bits corresponding to the write method in the first write control.

3. The storage system according to claim 1, The memory has storage areas corresponding to different writing methods. The storage controller writes the data read according to the first command to the storage area corresponding to the write mode in the first write control.

4. The storage system according to claim 3, The storage controller has a logic-to-physical translation table that translates the logical address of data specified by the host to the physical address of the memory, and the logic-to-physical translation table is updated in the first write control.

5. The storage system according to claim 2, The storage controller has a logic-to-physical translation table that translates the logical address of data specified by the host to the physical address of the memory, maintains the physical address of the storage area storing the data read according to the first command, updates the logic-to-physical translation table in the first write control, and updates the logic-to-physical translation table using the maintained physical address in the second write control.

6. The storage system according to claim 1, The storage controller determines the write mode in the first write control based on the data transmission speed of the host interface for sending and receiving data with the host and the free capacity of the memory.

7. The storage system according to claim 1, The first command is a command used to implement the following mode: read out the data written in a write mode with a large number of bits per unit, and then re-record it in a write mode with a smaller number of bits per unit than when it was written.

8. A memory control method, implemented by a memory controller, wherein the memory controller controls a memory having multiple memory cells, each of which can hold more than 2 bits of data, the memory control method comprising: Data is written to each storage cell in a writing method corresponding to the number of bits of data that can be written to each storage cell of the memory; When the first command is received from the host, the first write control is performed as follows: the data that has become the object of the first command is read from the memory, and the read data is written to the memory in a write method that is smaller than the number of bits corresponding to the write method when the read data is written. as well as When a read command is received from the host for data that has become the object of the first command, the data written to the memory by the first write control is read and transmitted to the host.

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