A method for manufacturing a vertical conductive channel enhancement mode Si-based GaN-HEMT device

Abstract

The application relates to a preparation method of a vertical conductive channel enhanced Si-based GaN-HEMT device, and relates to the technical field of semiconductors. The method comprises the following steps: S100, preparing a U-shaped groove extending to a Si substrate on an epitaxial wafer; S200, preparing P-type Si and N-type Si on the inner side wall of the U-shaped groove from bottom to top; S300, preparing a first isolation layer on the groove bottom of the U-shaped groove; S400, preparing polycrystalline silicon above the first isolation layer in the U-shaped groove, and filling the U-shaped groove; S500, etching from the edge of the top surface of the polycrystalline silicon downwards to form an isolation cavity extending vertically downwards to the P-type Si side, and preparing a second isolation layer in the isolation cavity; S600, preparing a gate electrode above the polycrystalline silicon; S700, etching a drain electrode area and preparing a drain electrode; and S800, back surface processing and preparing a source electrode. The SiO2 film of the device has a small depth-width ratio, requires a smaller process, and the process is simpler.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for fabricating a vertically conductive enhanced Si-based GaN-HEMT device. Background Technology

[0002] In the field of power electronic device technology, as the mainstream Si devices are approaching the performance limits determined by their material properties, third-generation semiconductors represented by GaN and SiC are receiving more and more attention. GaN has advantages such as a large bandgap, high critical breakdown field strength and high electron mobility, and has strong application potential in power device markets such as fast charging, data centers, OBCs and solar inverters.

[0003] Currently, the main application of GaN in power devices is GaN HEMT devices. Since Khan et al. fabricated the first AlGaN / GaN high electron mobility transistor (HEMT) in 1993, horizontal GaN HEMT devices have attracted widespread attention due to their superior electrical performance and lower power consumption compared to Si devices. In 2005, Nitronex launched the first commercially available depletion-mode RF GaN HEMT device grown on a Si substrate, and in 2009, EPC launched the first enhancement-mode Si-based GaN HEMT device.

[0004] Although GaN HEMT devices have superior performance compared to traditional Si devices, some problems still limit their application. For example, the mainstream P GaN enhancement-mode devices require etching the P GaN layer on top of AlGaN. The interface state problems caused by etching can seriously affect the device's performance at high frequencies and cause severe current collapse. Other types, such as F ion implantation enhancement-mode GaN HEMT and cascode hybrid enhancement-mode GaN HEMT, also have drawbacks such as difficulty in controlling process conditions.

[0005] To address the aforementioned issues, the applicant filed a patent application in June 2022 entitled "A Novel Si-based GaN Groove Gate Vertical Conductive Device," comprising a source electrode, a Si substrate, a buffer layer, a GaN intrinsic layer, and an AlGaN barrier layer connected sequentially from bottom to top. The drain electrode is located at the end of the device, extending from top to bottom through the AlGaN barrier layer and into the GaN intrinsic layer. A U-shaped groove extending from the AlGaN barrier layer to the substrate is provided in the middle of the device. A SiO2 thin film is provided within the U-shaped groove. P-type Si and N-type Si are sequentially arranged from bottom to top between the SiO2 thin film and the inner wall of the U-shaped groove. Polycrystalline silicon is provided in the middle of the SiO2 thin film. This structure places the device source at the bottom, which not only saves the area of ​​the source PAD region on the chip surface but also avoids the interface state problems and high-frequency current collapse effects caused by etching in current mainstream P-GaN enhancement-mode devices. However, as research and development progressed, the applicant discovered the following problems with this device in application:

[0006] 1. This device is limited by the thickness of the inversion layer formed on the P-type Si surface and the critical breakdown field strength that the SiO2 thin film can withstand. Generally, the gate voltage can withstand 0-8V, the threshold voltage is between 3-5V, and the gate voltage is around 6V when the device is working normally. Although it has good applications in power switching circuits, it cannot be used in amplifier circuits due to the limited range of gate voltage regulation and the small linear gain coefficient, which limits the application range of this type of device.

[0007] 2. The SiO2 thin film of this device has a large aspect ratio, and the SiO2 thin film deposition process is difficult, which may lead to deposition defects and requires high process conditions. Summary of the Invention

[0008] To address the above problems, this invention proposes a method for fabricating a vertically conductive enhancement-type Si-based GaN-HEMT device by adjusting the gate voltage to regulate the current between the substrate and the P-type Si, thereby controlling the current from the drain to the source. This method can be applied to power circuits for switching purposes as well as to amplifier circuits.

[0009] The technical solution of this invention is: a method for fabricating a vertical conductive channel enhancement-mode Si-based GaN-HEMT device, characterized by comprising the following steps:

[0010] S100, a U-shaped groove extending to the Si substrate is prepared on the epitaxial wafer;

[0011] S200, P-type Si and N-type Si are sequentially prepared from bottom to top on the inner sidewall of the U-shaped groove;

[0012] S300, the first isolation layer is prepared at the bottom of the U-shaped groove;

[0013] S400, polycrystalline silicon is prepared above the first isolation layer in the U-shaped groove to fill the U-shaped groove;

[0014] S500, etching downwards from the edge of the top surface of polysilicon to form an isolation cavity extending vertically downwards to the P-type Si side, and fabricating a second isolation layer within the isolation cavity;

[0015] S600, a gate electrode is fabricated on top of polycrystalline silicon;

[0016] S700, etch the drain electrode region and fabricate the drain electrode;

[0017] S800, backside processing, and fabrication of source electrodes.

[0018] Specifically, in step S100, the epitaxial wafer includes a buffer layer, a GaN intrinsic layer, and an AlGaN barrier layer formed sequentially on a Si substrate.

[0019] Specifically, the method for preparing the U-shaped groove in step S100 includes:

[0020] The epitaxial wafer is sequentially cleaned, coated with photoresist, photolithographically etched, and developed. Then, U-shaped grooves of the designed depth are etched on the epitaxial wafer using ICP dry etching. Finally, the photoresist is cleaned off.

[0021] Specifically, the preparation methods for P-type Si and N-type Si in step S200 include:

[0022] S210 uses photoresist to protect the area outside the U-shaped groove through coating, photolithography and development processes;

[0023] S220 uses CVD technology to first deposit P-type Si in a U-shaped groove;

[0024] S230, and then N-type Si is deposited on P-type Si using CVD process;

[0025] S240: After cleaning away the photoresist from step S210, the coating, photolithography, and development processes are repeated sequentially to protect the P-type Si and N-type Si that need to be retained in the area outside the U-groove and inside the U-groove. Then, the excess P-type Si and N-type Si in the U-groove are removed by ICP dry etching, and the photoresist is cleaned away.

[0026] Specifically, the first isolation layer is a SiN isolation layer or a SiO2 isolation layer.

[0027] Specifically, the method for preparing the first isolation layer includes:

[0028] S310 uses photoresist to protect the areas outside the U-groove and the P-type Si and N-type Si areas inside the U-groove that have been fabricated, through coating, photolithography and development.

[0029] S320, the first isolation layer is deposited in the remaining area of ​​the U-shaped groove using CVD process, and the photoresist in step S310 is cleaned away.

[0030] Specifically, the polycrystalline silicon preparation method in step S400 includes:

[0031] S410 uses photoresist to protect the area outside the U-shaped groove, the P-type Si and N-type Si inside the U-shaped groove, and the first isolation layer through coating, photolithography, and development processes;

[0032] S420: Polysilicon is deposited in a U-shaped trench using CVD process, and then the photoresist from step S410 is cleaned off.

[0033] Specifically, the preparation method of the second isolation layer in step S500 includes:

[0034] The S510 uses a coating, photolithography, and development process to protect the non-etched area on the top surface of the epitaxial wafer. Then, ICP dry etching is used to remove the area at the edge of the polysilicon to form an isolation cavity.

[0035] S520 protects the area that needs to be preserved on the top surface of the epitaxial wafer, deposits a second isolation layer in the isolation cavity, and then washes away the photoresist.

[0036] Specifically, the method for fabricating the gate electrode in step S600 includes:

[0037] S610 uses photoresist to protect the area outside the U-shaped groove, the N-type Si already prepared inside the U-shaped groove, and the second isolation layer through coating, photolithography, and development processes.

[0038] S620 uses MOCVD or metal ion sputtering deposition to fabricate gate electrodes on polycrystalline silicon, followed by cleaning off the photoresist.

[0039] Specifically, the method for preparing the drain electrode in step S700 includes:

[0040] S710 uses photoresist to protect the area where the drain electrode is located through coating, photolithography and development processes;

[0041] S720 uses ICP dry etching to etch drain electrode trenches of the designed depth on the epitaxial wafer;

[0042] S730, after cleaning away the photoresist in step S710, the coating, photolithography and development processes are repeated to protect the area where the drain electrode is located with photoresist.

[0043] S740 uses MOCVD or metal ion sputtering deposition to prepare the drain electrode in the drain electrode trench area, and then washes away the photoresist.

[0044] This invention improves the structure of the composite gate of the device, with P-type Si in direct contact with the gate polysilicon. In the blocking state, P-type Si and N-type Si are reverse biased, and the entire device is not conductive. When a forward gate voltage exceeding a certain value is applied to the gate electrode, P-type Si and the substrate are forward biased, and electrons flow from the substrate to P-type Si. At this time, N-type Si and the drain electrode are at a high potential. The high concentration of electrons at P-type Si is attracted to the N-type Si region and flows to the drain electrode through a two-dimensional electron flow, forming an electron channel from the source to the drain electrode, thereby turning on the device.

[0045] Moreover, this design places the device source at the bottom, and the vertical conductive structure saves the area of ​​the source PAD region on the chip surface, thereby increasing the power density of the device. It avoids the interface state problems and high-frequency current collapse effects caused by etching of the current mainstream P-GaN enhancement devices, thus promoting the development and application of Si-based GaN HEMTs in the field of power electronics.

[0046] Compared with the patent application filed in June 2022 for "A Novel Si-based GaN Groove Gate Vertical Conductive Device", this case has the following advantages:

[0047] 1. The threshold voltage of the device of the present invention is generally between 0.6-1V. The low threshold voltage makes it easier to drive, and the gate turn-on voltage can be adjusted by controlling the doping concentration of P-type Si and substrate.

[0048] 2. The device of the present invention can adjust the current between the substrate and the P-type Si by adjusting the gate voltage, thereby controlling the current from the drain to the source. Furthermore, the device has a large linear gain coefficient. By reasonably adjusting the doping concentration of N-type Si, P-type Si and the substrate, the amplification factor of the device can be between 50 and 10,000 times. It can be used in power circuits as a switch or in amplification circuits.

[0049] 3. The SiO2 thin film of the device of the present invention has a small aspect ratio, which reduces the requirements for the process and makes the process simpler. Attached Figure Description

[0050] Figure 1 This is a process flow diagram of the present invention.

[0051] Figure 2 This is a schematic diagram of step S100.

[0052] Figure 3 This is a schematic diagram of step S200.

[0053] Figure 4 This is a schematic diagram of step S300.

[0054] Figure 5 This is a schematic diagram of step S400.

[0055] Figure 6 This is a schematic diagram of step S500.

[0056] Figure 7 This is a schematic diagram of step S600.

[0057] Figure 8 This is a schematic diagram of step S700.

[0058] Figure 9 This is a schematic diagram of step S800.

[0059] Figure 10 This is a test graph showing the ratio of actual current to saturation current at high frequencies for samples 1, 2, and the device in this case after the current collapse effect occurs at high frequencies.

[0060] Figure 11 The graph shows the thermal resistance test values ​​of the junction-to-case of Sample 1, Sample 2, and the device in this case under 100% duty cycle conditions.

[0061] In the figure, 1 is the source electrode, 2 is the Si substrate, 3 is the buffer layer, 4 is the GaN intrinsic layer, 5 is the drain electrode, 6 is the AlGaN barrier layer, 7 is N-type Si, 8 is the gate electrode, 9 is polysilicon, 101 is the first isolation layer, 102 is the second isolation layer, and 11 is P-type Si. Detailed Implementation

[0062] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0063] The present invention is as follows Figure 1-10 As shown; a method for fabricating a vertical conductive channel enhancement-mode Si-based GaN-HEMT device includes the following steps:

[0064] S100, a U-shaped groove extending to the Si substrate 2 is fabricated on the epitaxial wafer; reference Figure 2 As shown;

[0065] S200, P-type Si11 and N-type Si7 are sequentially prepared from bottom to top on the inner wall of the U-shaped groove; refer to Figure 3 As shown;

[0066] S300, a first isolation layer 101 is prepared at the bottom of the U-shaped groove; refer to Figure 4 As shown;

[0067] S400, polycrystalline silicon 9 is fabricated above the first isolation layer 101 within the U-shaped groove, filling the U-shaped groove; refer to Figure 5 As shown;

[0068] S500, etching downwards from the edge of the top surface of polysilicon 9 to form an isolation cavity extending vertically downwards to the P-type Si11 side, and fabricating a second isolation layer 102 within the isolation cavity; in this case, the second isolation layer 102 is a SiN isolation layer or a SiO2 isolation layer; see reference. Figure 6 As shown;

[0069] S600, a gate electrode 8 is fabricated above the polysilicon 9; refer to Figure 7 As shown;

[0070] S700, etch the drain electrode region and fabricate drain electrode 5; refer to Figure 8 As shown;

[0071] S800, backside processing, and fabrication of source electrode 1, reference. Figure 9 As shown;

[0072] Further specifying, in step S100, the epitaxial wafer includes a buffer layer 3, a GaN intrinsic layer 4, and an AlGaN barrier layer 6 sequentially formed on the Si substrate 2.

[0073] Further specifying, the method for preparing the U-shaped groove in step S100 includes:

[0074] The epitaxial wafer is sequentially cleaned, coated with photoresist, photolithographically etched, and developed. Then, U-shaped grooves of the designed depth are etched on the epitaxial wafer using ICP dry etching. Finally, the photoresist is cleaned off.

[0075] Further specifying, the preparation methods of P-type Si11 and N-type Si7 in step S200 include:

[0076] S210 uses photoresist to protect the area outside the U-shaped groove through coating, photolithography and development processes;

[0077] S220 uses CVD process to first deposit P-type Si11 in a U-shaped groove;

[0078] S230, and then N-type Si7 is deposited on P-type Si11 using CVD process;

[0079] S240: After cleaning away the photoresist from step S210, the coating, photolithography, and development processes are repeated sequentially to protect the P-type Si11 and N-type Si7 that need to be retained in the area outside the U-shaped groove and inside the U-shaped groove. Then, the excess P-type Si11 and N-type Si7 in the U-shaped groove are removed by ICP dry etching, and the photoresist is cleaned away.

[0080] Further specifying, the first isolation layer is a SiN isolation layer or a SiO2 isolation layer.

[0081] Further specifying, the method for preparing the first isolation layer 101 includes:

[0082] S310 uses photoresist to protect the areas outside the U-shaped groove and the areas inside the U-shaped groove that have been prepared with P-type Si11 and N-type Si7 by coating, photolithography and development;

[0083] S320, the first isolation layer 10 is deposited in the remaining area of ​​the U-shaped groove using CVD process, and the photoresist in step S310 is cleaned away.

[0084] Further specifying, the preparation method of polycrystalline silicon 9 in step S400 includes:

[0085] S410 uses photoresist to protect the area outside the U-shaped groove, the P-type Si11 and N-type Si7 already prepared inside the U-shaped groove, and the first isolation layer 101 within the U-shaped groove through a coating, photolithography, and development process;

[0086] S420: Polysilicon 9 is deposited in a U-shaped trench using CVD process, and then the photoresist from step S410 is cleaned off.

[0087] Further specifying, the preparation method of the second isolation layer 10 in step S500 includes:

[0088] S510 protects the non-etched area on the top surface of the epitaxial wafer through coating, photolithography and development processes, and then uses ICP dry etching to remove the area at the edge of the polysilicon 9 to form an isolation cavity;

[0089] S520, the area to be preserved on the top surface of the epitaxial wafer is protected, a second isolation layer 102 is deposited in the isolation cavity, and then the photoresist is washed away.

[0090] Further specifying, the method for fabricating the gate electrode 8 in step S600 includes:

[0091] S610 uses photoresist to protect the area outside the U-shaped groove, the N-type Si 7 already prepared inside the U-shaped groove, and the second isolation layer 102 in the U-shaped groove through coating, photolithography, and development processes;

[0092] S620, using MOCVD or metal ion sputtering deposition process to fabricate gate electrode 8 on polysilicon 9, and then cleaning off photoresist.

[0093] Further specifying, the method for preparing the drain electrode 5 in step S700 includes:

[0094] S710 uses photoresist to protect the area where the drain electrode 5 is located through coating, photolithography and development processes;

[0095] S720 uses ICP dry etching to etch drain electrode trenches of the designed depth on the epitaxial wafer;

[0096] S730, after cleaning away the photoresist in step S710, the coating, photolithography and development processes are repeated to protect the area where the drain electrode 5 is located with photoresist.

[0097] S740 uses MOCVD or metal ion sputtering deposition to prepare drain electrode 5 in the drain electrode trench area, and then cleans off the photoresist.

[0098] The preparation method of source electrode 1 in step S800 includes:

[0099] S810 uses a UV film to protect the front of the chip;

[0100] The S820 thins the back of the chip through grinding and polishing processes.

[0101] For S830, source electrode 1 is fabricated on the back side of the chip using MOCVD or metal ion sputtering deposition process, followed by removal of the UV film, thus completing the fabrication.

[0102] A vertical conductive channel enhancement-mode Si-based GaN-HEMT device includes:

[0103] An epitaxial wafer, wherein the epitaxial wafer has a U-shaped groove extending to the Si substrate 2;

[0104] P-type Si11, wherein the P-type Si11 is prepared on the inner sidewall of a U-shaped groove and extends upward from the bottom of the U-shaped groove to the intrinsic GaN layer 4 of the epitaxial wafer.

[0105] N-type Si7, which extends upward from the top of P-type Si11 to the opening of the U-shaped groove;

[0106] The first isolation layer 101 is disposed at the bottom of the U-shaped groove and located inside the P-type Si11;

[0107] Polycrystalline silicon 9 extends upward from the top surface of the first isolation layer 101 to the opening of the U-shaped groove; an isolation cavity extending downward to the side of the P-type Si11 is provided between the polycrystalline silicon 9 and the N-type Si7.

[0108] The second isolation layer 102 is disposed in the isolation cavity; the first isolation layer serves to isolate the Si substrate 2 from the polysilicon 9, and the second isolation layer serves to isolate the N-type Si 7 from the polysilicon 9.

[0109] A gate electrode 8 is disposed above the polycrystalline silicon 9; the lower surface of the gate electrode 8 contacts the upper surface of the polycrystalline silicon 9, forming an ohmic contact. The gate electrode 8 is a Ti / Al metal layer, ensuring a good ohmic contact between the gate electrode 8 and the polycrystalline silicon 9; and

[0110] Electrode 5 is disposed at the end of the epitaxial wafer and extends upward from within the GaN intrinsic layer 4 to ensure good ohmic contact with the two-dimensional electron gas.

[0111] Further specifying, the epitaxial wafer includes a buffer layer 3, a GaN intrinsic layer 4, and an AlGaN barrier layer 6 sequentially formed on a Si substrate 2.

[0112] Furthermore, the bottom of the Si substrate 2 is provided with a source electrode 1.

[0113] Further specified, the lateral width of N-type Si 7 is equal to that of P-type Si 11, and they are on the same plane and form good contact. The lateral width of P-type Si 11 is 10nm-1um, ensuring that P-type Si 11 and N-type Si 7 can form a saturated current channel. The sum of the vertical heights of P-type Si 11 and N-type Si 7 is the U-groove etching depth. The upper surface of P-type Si 11 is lower than the horizontal plane where the two-dimensional electron gas of the GaN HEMT device is located, and the upper surface of N-type Si 7 is flush with the upper surface of the AlGaN layer.

[0114] In this case, the U-shaped trench and the composite gate within the trench (including the first isolation layer 101, polysilicon 9, the second isolation layer 102, P-type Si 11, N-type Si 7 and the gate electrode 8) constitute the gate structure of the device. The U-shaped trench is formed by etching to provide a vertical conductive channel for the device. The U-shaped trench needs to be etched down to the Si substrate layer of the epitaxial wafer. The bottom of the U-shaped trench can be located on any horizontal plane of the Si substrate layer according to the actual process conditions and electrical parameters. The width of the U-shaped trench is 100nm-5um, which can be determined according to the specific process conditions and machine precision.

[0115] The first isolation layer 101 is further defined;

[0116] The thickness of the first isolation layer at the bottom of the U-shaped groove in the vertical direction is 10nm-1um. The thinner the better, while ensuring good isolation performance.

[0117] The width of the second isolation layer in the U-shaped groove is the same as the thickness of the first isolation layer in the vertical direction. The bottom surface of the second isolation layer is parallel to or lower than the bottom surface of the N-type Si 7, but it should provide a sufficiently large contact window for the P-type Si 11 and polysilicon 9.

[0118] Further limit polycrystalline silicon 9;

[0119] Polysilicon 9 is filled inside the U-shaped groove. Its upper surface is flush with the AlGaN barrier layer 6, and its lower surface is in contact with the first isolation layer. There are isolation layers (first isolation layer 101 and second isolation layer 102) between polysilicon 9 and N-type Si 7 and Si substrate 2, ensuring good interface contact between polysilicon 9 and P-type Si 11. There are no voids or obvious defects inside polysilicon 9, ensuring good conductivity.

[0120] This invention proposes a vertical conductive channel enhancement-mode Si-based GaN HEMT device and its fabrication method. This device and method avoid the P GaN etching step required for P GaN enhancement-mode devices, effectively reducing interface state problems caused by P GaN etching. Interface state problems caused by etching can severely affect the device's performance at high frequencies, leading to severe current collapse effects. (Refer to...) Figure 10 As shown in the figure, Sample1 and Sample2 on the horizontal axis represent commonly used P GaN enhancement-mode devices on the market, and the vertical axis represents the ratio of actual current to saturation current at high frequencies. The actual current of commercially available P GaN enhancement-mode devices at high frequencies is generally 50%-85% of the static saturation current. The novel vertical conductive channel enhancement-mode Si-based GaN HEMT device proposed in this invention exhibits extremely low current collapse effect, with the actual current at high frequencies reaching 89% of the static saturation current. Furthermore, the gate adopts a vertical conductive structure, and the source is located below the chip and directly connected to the package frame, enhancing the device's heat dissipation capability. This solves the problem that most mainstream GaN HEMT devices are horizontal structures, which are prone to self-heating under high-power conditions, resulting in poor heat dissipation. Figure 11 As shown in the figure, Rthjc represents the junction-to-case thermal resistance under 100% duty cycle conditions. Under the same packaging conditions (DFN5*6), the typical value of the junction-to-package thermal resistance Rthjc of the novel vertical conductive channel enhancement-type Si-based GaN HEMT device proposed in this invention is 0.52℃ / W. The thermal resistance Rthjc of commercially available P GaN enhancement-type devices is between 1.1 and 1.6. The thermal resistance Rthjc of the vertical conductive structure enhancement-type Si-based GaN HEMT device proposed in this invention is significantly improved.

[0121] Regarding the information disclosed in this case, the following points need to be clarified:

[0122] (1) The accompanying drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case. Other structures can refer to the general design.

[0123] (2) Where there is no conflict, the embodiments and features disclosed in this case can be combined with each other to obtain new embodiments;

[0124] The above are merely specific embodiments disclosed in this case, but the scope of protection of this disclosure is not limited thereto. The scope of protection disclosed in this case shall be determined by the scope of protection of the claims.

Claims

1. A method for fabricating a vertical conductive channel enhancement-mode Si-based GaN-HEMT device, characterized in that, Includes the following steps: S100, a U-shaped groove extending to the Si substrate (2) is prepared on the epitaxial wafer; S200, P-type Si (11) and N-type Si (7) are sequentially prepared from bottom to top on the inner sidewall of the U-shaped groove. S300, a first isolation layer (101) is prepared at the bottom of the U-shaped groove; S400, polysilicon (9) is prepared above the first isolation layer (101) in the U-shaped groove to fill the U-shaped groove; S500, etching downwards from the edge of the top surface of polysilicon (9) to form an isolation cavity extending vertically downwards to the side of P-type Si (11), and fabricating a second isolation layer (102) inside the isolation cavity. S600, a gate electrode (8) is fabricated above the polycrystalline silicon (9); S700, etch the drain electrode region and fabricate the drain electrode (5); S800, backside processing, and fabrication of source electrode (1); In step S100, the epitaxial wafer includes a buffer layer (3), a GaN intrinsic layer (4), and an AlGaN barrier layer (6) formed sequentially on a Si substrate (2); the upper surface of the P-type Si (11) is lower than the horizontal plane where the two-dimensional electron gas of the GaN HEMT device is located, and the upper surface of the N-type Si (7) is flush with the upper surface of the AlGaN layer.

2. The method for fabricating a vertical conductive channel enhancement-type Si-based GaN-HEMT device according to claim 1, characterized in that, The method for preparing the U-shaped groove in step S100 includes: The epitaxial wafer is sequentially cleaned, coated with photoresist, photolithographically etched, and developed. Then, U-shaped grooves of the designed depth are etched on the epitaxial wafer using ICP dry etching. Finally, the photoresist is cleaned off.

3. The method for fabricating a vertical conductive channel enhancement-type Si-based GaN-HEMT device according to claim 1, characterized in that, The preparation methods of P-type Si (11) and N-type Si (7) in step S200 include: S210 uses photoresist to protect the area outside the U-shaped groove through coating, photolithography and development processes; S220, deposit P-type Si in a U-shaped groove (11); S230, and then N-type Si (7) is deposited on P-type Si (11); S240, after cleaning away the photoresist in step S210, the coating, photolithography and development processes are repeated in sequence to protect the P-type Si (11) and N-type Si (7) that need to be retained in the U-shaped groove area and inside the U-shaped groove; then, the excess P-type Si (11) and N-type Si (7) in the U-shaped groove are removed by ICP dry etching and the photoresist is cleaned away.

4. The method for fabricating a vertical conductive channel enhancement-mode Si-based GaN-HEMT device according to claim 1, characterized in that, The first isolation layer is a SiN isolation layer or a SiO2 isolation layer.

5. A method for fabricating a vertical conductive channel enhancement-type Si-based GaN-HEMT device according to claim 1 or 4, characterized in that, The method for preparing the first isolation layer (101) includes: S310, the regions outside the U-shaped groove and the regions inside the U-shaped groove where P-type Si (11) and N-type Si (7) have been prepared are protected with photoresist by coating, photolithography and development; S320, the first isolation layer (101) deposited in the remaining area within the U-shaped groove is cleaned to remove the photoresist from step S310.

6. The method for fabricating a vertical conductive channel enhancement-mode Si-based GaN-HEMT device according to claim 1, characterized in that, The preparation method of polycrystalline silicon (9) in step S400 includes: S410, the area outside the U-shaped groove, the P-type Si (11), N-type Si (7) and the first isolation layer (101) already prepared inside the U-shaped groove are protected with photoresist through coating, photolithography and development processes; S420, after depositing polysilicon (9) in the U-shaped groove, the photoresist in step S410 is cleaned off.

7. The method for fabricating a vertical conductive channel enhancement-mode Si-based GaN-HEMT device according to claim 1, characterized in that, The preparation method of the second isolation layer (102) in step S500 includes: S510 protects the non-etched area on the top surface of the epitaxial wafer through coating, photolithography and development processes, and then removes the area at the edge of the polysilicon (9) by ICP dry etching to form an isolation cavity; S520, the area to be preserved on the top surface of the epitaxial wafer is protected, a second isolation layer (102) is deposited in the isolation cavity, and then the photoresist is washed away.

8. The method for fabricating a vertical conductive channel enhancement-mode Si-based GaN-HEMT device according to claim 1, characterized in that, The preparation method of the gate electrode (8) in step S600 includes: S610, the N-type Si (7) and the second isolation layer (102) prepared in the U-shaped groove are protected with photoresist through coating, photolithography and development processes; S620, a gate electrode (8) is fabricated on polysilicon (9), and then the photoresist is washed away.

9. The method for fabricating a vertical conductive channel enhancement-mode Si-based GaN-HEMT device according to claim 1, characterized in that, The preparation method of the drain electrode (5) in step S700 includes: S710, the area where the drain electrode (5) is located is protected with photoresist through coating, photolithography and development processes; S720 uses ICP dry etching to etch drain electrode trenches of the designed depth on the epitaxial wafer; S730, after cleaning off the photoresist in step S710, re-coating, photolithography and development processes are performed to protect the area where the drain electrode (5) is located with photoresist. S740, a drain electrode (5) is prepared in the drain electrode trench area, and then the photoresist is cleaned off.

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