Method and apparatus for locating open points within integrated circuit chips

By physically grinding and measuring the electrical characteristics of the conductive layer, the problem of locating open circuit points within integrated circuit chips has been solved, enabling rapid and non-destructive open circuit point location, simplifying the operation process and improving accuracy.

CN115831788BActive Publication Date: 2026-07-03JIANGYIN SHENGBANG MICROELECTRONICS MFG CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
JIANGYIN SHENGBANG MICROELECTRONICS MFG CO LTD
Filing Date
2022-09-28
Publication Date
2026-07-03

AI Technical Summary

Technical Problem

Existing technologies make it difficult to quickly and non-destructively locate open circuits within integrated circuit chips, especially to accurately determine whether the open circuit occurs at the first or second bonding point. Furthermore, chemical etching methods may cause secondary damage and contaminant residues.

Method used

Physical grinding is used to remove the molding compound from the top layer of the integrated circuit chip package, forming a conductive layer to cover the target wire bonding. Electrical characteristics are measured to determine the location of open circuits. Coarse sandpaper is used for preliminary grinding, which simplifies the operation accuracy requirements.

Benefits of technology

It enables rapid and accurate location of the breakthrough point, avoiding secondary damage and pollution caused by chemical corrosion, and improving positioning efficiency and accuracy.

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Abstract

Embodiments of the present disclosure provide a method and apparatus for locating an open point within an integrated circuit chip. In the method, at least a portion of molding compound of a top layer of a package of the integrated circuit chip is removed to expose a target wire bond inside the integrated circuit chip. The target wire bond corresponds to an open pin of the integrated circuit chip. A conductive layer is formed on a surface of the integrated circuit chip where the molding compound is removed. The conductive layer covers the exposed portion of the target wire bond. An electrical characteristic between the conductive layer and the open pin is measured. If a short occurs between the conductive layer and the open pin, it is determined that the open point is located at a first bond point between the target wire bond and a wafer chip of the integrated circuit chip or at the wafer chip. If an open occurs between the conductive layer and the open pin, it is determined that the open point is located at a second bond point between the target wire bond and the open pin.
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