An adaptive high-voltage and low-loss power device

Abstract

The present invention belongs to the field of power semiconductor technology and relates to an adaptive high-voltage low-loss power device. Compared with the traditional LIGBT structure, the present invention introduces an adaptive NMOS structure at the anode end of the LIGBT, and the gate of the NMOS structure is controlled by an integrated diode. When forward-conducting, the NMOS channel is closed, and the electron extraction path is blocked, thereby eliminating the snapback (voltage foldback) effect. During the shutdown process, as the anode voltage rises, the NMOS channel is adaptively turned on, and the electrons in the drift region are extracted from the N+ collector region through the anode NMOS channel; at the same time, the P+ collector region and the N-type buffer layer are almost short-circuited at the same potential, which inhibits the P+ collector region from injecting holes into the drift region, and the two together accelerate the shutdown of the device to reduce the shutdown loss. During reverse freewheeling, the top layer P-type 10 second N drift region of the diode end of the new device forms a superjunction structure, which shortens the reverse recovery time of the new device and reduces the reverse recovery charge. Therefore, the present invention has a faster shutdown speed, smaller shutdown loss and lower reverse recovery loss.

Description

Technical Field

[0001] The invention belongs to the technical field of power semiconductors and relates to an adaptive SOILIGBT (Lateral Insulated Gate Bipolar Transistor) integrated with a freewheeling diode. Background Art

[0002] The insulated gate bipolar transistor (IGBT) is a gate-controlled bipolar conductive device. Its gate-controlled characteristics give it the advantages of high input impedance and easy driving. Its bipolar conductivity makes it easy to achieve low on-state voltage drop and high current density, making it very suitable for use in high-voltage and high-power power electronics technology fields such as smart grids, rail transportation, and industrial control. Semiconductor devices based on SOI technology are easy to achieve full dielectric isolation, with lower leakage current and smaller parasitic effects.

[0003] When the LIGBT device is forward-conducted, the conductivity modulation effect occurs in the drift region and a large number of excess carriers are stored, which is beneficial to reduce the forward on-state voltage drop (Von) of the device. However, this will lead to a longer tail current when it is turned off, resulting in a larger turning off loss (Eoff). At the same time, due to the conductivity modulation effect, the voltage divider of the channel resistance accounts for a larger proportion of the forward on-state voltage drop of the IGBT.

[0004] In order to improve the contradictory relationship between the turn-off loss and the conduction voltage drop of the LIGBT device, the literature (MR Simpson, PAGough, FIH shieh, et al. Anlysis of the lateral insulated gate transistor [C]. IEEE International Electron Devices Meeting, Washington, 1985, 740-743) proposed a short-circuit anode structure, that is, introducing a short-circuited anode N+ region next to the anode P+ region to accelerate the extraction of electrons stored in the drift region during the device shutdown process. However, the short-circuit anode structure causes the device to have a snapback effect caused by the conversion from the unipolar conduction mode to the bipolar conduction mode when it is turned on, which reduces the reliability of the device in parallel. The literature (NKUdugampola, RAMcMahon, F.Udrea, et al. Analysis and design of the dual-gate inversion layer emitter transistor [J]. IEEE Transactions on Electron Devices, 2005, 52 (1): 99-105) proposed a dual-gate inversion layer injection type LIGBT; when forward conducting, the anode gate of this structure is negatively potentialed relative to the anode, and the drift region below the anode gate and the surface of the N-buffer layer will form a hole inversion layer connected to the P+ anode, which is equivalent to increasing the length of the P+ anode and the anode distributed resistance, thereby suppressing the snapback phenomenon; during the shutdown process, the anode gate is short-circuited with the anode, and the hole inversion layer under the anode gate disappears. At this time, under the action of the short-circuited anode, the P+ anode will stop injecting holes into the drift region, while the N+ anode will quickly extract electrons in the drift region, thereby accelerating the device shutdown and significantly reducing the shutdown loss value. However, this structure requires the introduction of an additional gate drive control circuit, which increases the device design cost and control difficulty. Summary of the invention

[0005] In view of the above problems, the present invention proposes an adaptive high-voltage and low-loss power device.

[0006] The technical solution of the present invention is an adaptive high-voltage low-loss power device, comprising a P-type substrate 1, an insulating dielectric layer 2 and an N-type semiconductor layer stacked in sequence from bottom to top, wherein the N-type semiconductor is divided into a first N drift region 31 and a second N drift region 32 by isolation grooves Ι and Ⅱ, which are used to form a LIGBT part and a diode part respectively.

[0007] The isolation trench I is composed of a first isolation trench dielectric layer 92 and a first isolation trench polysilicon layer 91 located in the first isolation trench dielectric layer 92; the isolation trench II is composed of a second isolation trench dielectric layer 94 and a second isolation trench polysilicon layer 93 located in the second isolation trench dielectric layer 94; the isolation trench I and the isolation trench II are both in contact with the upper surface of the insulating dielectric layer 2;

[0008] The diode part forms a diode cathode structure, a top P-type region 101 and a diode anode structure on the surface of the second N drift region 32 along the lateral direction; the diode cathode structure includes a second P-type well region 42 and a second P+ body contact region 52 located on the upper layer of the second P-type well region 42; the diode anode structure includes a second N-type buffer layer 8 and an N+ collector region 62 located on the upper layer of the second N-type buffer layer 8; the top P-type region 101 is located between the diode cathode structure and the diode anode structure, and its side surfaces are in contact with the second N-type buffer layer 8 and the second P-well region 42 respectively; the lead-out end of the second P+ body contact region is the diode cathode, and the lead-out end of the N+ collector region 62 is the diode anode;

[0009] The LIGBT portion forms a LIGBT cathode structure, a gate structure and a LIGBT anode structure on the surface of the first N drift region 31 along the lateral direction; the LIGBT cathode structure includes a first P-type well region 41 and a first P+ body contact region 51 and an N+ emitter region 61 located on the upper layer of the first P-type well region 41 and arranged in sequence; the gate structure is a planar gate structure, including a gate dielectric layer 15 and a polysilicon material 16 covering the upper surface of the gate dielectric layer, the gate dielectric layer 15 is located in the first P between the N+ emitter region 61 and the first N drift region 31. The upper layer of the type well region, one end of which is in contact with the upper surface of the N+ emitter region 61, and the other end of which is in contact with the first N drift region 31; the LIGBT anode structure includes a first N-type buffer layer 71 and a P+ collector region 72, and the P+ collector region 72 is located on the upper surface of the first N-type buffer region 71; the common lead-out end of the first P+ body contact region 51 and the N+ emitter region 61 is the LIGBT cathode, and is short-circuited with the diode cathode, the lead-out end of the polysilicon material 16 is the gate, and the lead-out end of the P+ collector region 72 is the LIGBT anode, and is short-circuited with the diode anode;

[0010] Features:

[0011] The LIGBT anode structure also has an NMOS structure, including an anode gate, the first N-type buffer layer 71, a third P-type well region 74, an N+ collector region 73, a third P+ body contact region 75 and an electrode 11; the anode gate is a trench gate structure, located in the first N-type buffer region 71, and in contact with the side of the P+ collector region 72 away from the first N drift region 31, and the anode gate is composed of a gate dielectric layer 76 and a polysilicon electrode 77 located in the gate dielectric layer 76; the third P-type well region 74 is located on the side of the anode gate away from the first N drift region 31, and its junction depth is lower than the anode gate depth; the N+ collector region 73 and the third P+ body contact region 75 are respectively located at two ends of the upper layer of the third P-type well region 74, wherein the N+ collector region 73 is in contact with the anode gate, the polysilicon electrode 77 and the lead-out ends of the N+ collector region 73 are connected to the anode, and the lead-out end of the third P+ body contact region 75 is the electrode 11;

[0012] The surface of the top P-type region 101 in the diode part is provided with an electrode 12 near the N+ collector region 62, and the electrode 12 is short-circuited with the electrode 11 in the LIGBT anode;

[0013] Furthermore, the LIGBT portion has a top P-type region 102 , which is located on the first N drift region 31 , between the LIGBT cathode structure and the LIGBT anode structure, and whose side surface does not contact the first P well region 41 .

[0014] Further, the LIGBT partial gate structure is a trench gate structure, which includes a trench gate dielectric layer 17 and a polysilicon material 18 located in the trench gate dielectric layer 17, and the two sides of the LIGBT partial gate structure are in contact with the N+ emitter region 61 and the first N drift region 31 respectively, and penetrate the P well region 41 along the vertical direction of the device and then extend into the first N drift region 31;

[0015] Furthermore, the semiconductor material used in the device is one of Si, SiC, SiGe, GaAs, GaO and GaN.

[0016] The beneficial effects of the present invention are as follows: compared with the traditional LIGBT structure, the NMOS structure in the LIGBT anode of the present invention provides a carrier extraction path when shutting down, which can improve the shutdown speed of the device, reduce the shutdown loss, and will not introduce the snapback phenomenon; the top P region 10 of the integrated freewheeling diode in the present invention and the second N drift region 32 form a super junction, which is beneficial to reduce the reverse recovery loss of the device during reverse recovery, and provides a low potential for the third P-type well region 74 to turn on the NMOS during the shutdown process, effectively reducing the shutdown loss without the need for an additional control circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1This is a structural diagram of Example 1

[0018] Figure 2 The structural diagram of Example 2

[0019] Figure 3 The structural diagram of Example 3 DETAILED DESCRIPTION

[0020] The technical solution of the present invention is described in detail below in conjunction with the accompanying drawings and embodiments:

[0021] Example 1

[0022] like Figure 1 As shown, an adaptive SOI LIGBT with an integrated freewheeling diode is shown in this example.

[0023] This example works like this:

[0024] When the new device is forward-conducted, the potential difference between the anode and the electrode 12 of the diode part is small, and an inversion layer cannot be formed on the side of the third p-type well region 74 close to the anode gate. The LIGBT anode NMOS structure is in an off state, resulting in the conductive path between the N+ collector region 73 and the first N-type buffer layer 71 and the first N drift region 31 being blocked, and the device cannot enter the unipolar conductive mode, thereby eliminating the snapback effect.

[0025] During the shutdown process of the new device, the diode part enters the reverse blocking state, and the potential difference between the anode and the electrode 12 of the diode part increases as the anode voltage rises. When the anode voltage rises further, the potential difference between the anode and the electrode 12 is large enough, and the corresponding anode NMOS channel is turned on, so that the N+ collector region 73 is short-circuited with the first N-type buffer layer 71, and then the P+ collector region 72 is short-circuited with the first N-type buffer layer 71 at almost the same potential, causing the P+ collector region 72 to stop injecting holes into the drift region. At the same time, the electrons in the drift region are quickly extracted by the N+ collector region 73 through the anode NMOS channel, further accelerating the shutdown of the device and reducing the shutdown loss.

[0026] In the reverse freewheeling state, the P-type region 10 at the top of the diode and the second N drift region 32 form a super junction structure, which accelerates the exhaustion speed of the drift region of the diode structure and shortens the reverse recovery time t of the new device. rr , reduces the reverse recovery charge Q rr .

[0027] When the new device is in the forward blocking state, the potential difference between the anode and the electrode 12 is large enough, the corresponding anode NMOS channel is turned on, and the P+ collector region 72 and the first N-type buffer layer 71 are almost short-circuited at the same potential, causing the P+ collector region 72 to stop injecting holes into the drift region, and only the N+ collector region 73 injects electrons into the drift region through the anode NMOS channel. Therefore, the breakdown mode of the new device is MOS-like breakdown, which improves the breakdown voltage of the device, and the breakdown voltage of the new device does not change with the doping concentration of the P+ collector region 72.

[0028] The beneficial effects of the present invention are that, compared with the traditional LIGBT structure, the present invention can accelerate the device shutdown to reduce the shutdown loss without the need for an additional control circuit, eliminate the snapback effect, have reverse freewheeling capability, and have a low reverse recovery time and reverse recovery loss, and improve the device withstand voltage.

[0029] Embodiment 2:

[0030] like Figure 2 As shown, the difference between this embodiment and embodiment 1 is that a top P-type region 102 is further provided on the upper layer of the first N drift region 31, between the LIGBT cathode structure and the LIGBT anode structure, and the side of the top P-type region 102 is not in contact with the first P well region 41. Compared with embodiment 1, the top P-type region 102 and the first N drift region 31 form a super junction, which improves the device withstand voltage, accelerates the depletion speed of the drift region of the LIGBT part during the device shutdown process, and reduces the device shutdown loss.

[0031] Embodiment 3:

[0032] like Figure 3 As shown, the difference between this embodiment and embodiment 1 is that the partial gate structure of the LIGBT is a trench gate structure, the trench gate structure includes a trench gate dielectric layer 17 and a polysilicon material 18 located in the trench gate dielectric layer 17, and the two sides of the partial gate structure of the LIGBT are in contact with the N+ emitter region 61 and the first N drift region 31 respectively, and extend into the first N drift region 31 after penetrating the P well region 41 along the vertical direction of the device. Compared with embodiment 1, the trench gate structure has a physical blocking effect, and when the device is turned on, it can prevent the holes stored in the first N drift region 31 from being quickly drawn away by the first P+ body contact region 51 through the first P well region 41, which is beneficial to improve the carrier concentration and current capacity of the drift region to obtain a low conduction voltage drop, and when the device is forward blocked, it blocks the lateral surface leakage current of the device and improves the withstand voltage of the device.

Claims

1. An adaptive high-voltage low-loss power device, comprising a P-type substrate (1), an insulating dielectric layer (2) and an N-type semiconductor layer stacked in sequence from bottom to top, wherein the N-type semiconductor is divided into a first N drift region (31) and a second N drift region (32) by a first isolation trench and a second isolation trench, which are used to form a LIGBT part and a diode part respectively; The first isolation trench is composed of a first isolation trench dielectric layer (92) and a first isolation trench polysilicon layer (91) located in the first isolation trench dielectric layer (92); the second isolation trench is composed of a second isolation trench dielectric layer (94) and a second isolation trench polysilicon layer (93) located in the second isolation trench dielectric layer (94); the first isolation trench and the second isolation trench are both in contact with the upper surface of the insulating dielectric layer (2); The diode portion forms a diode cathode structure, a top P-type region (101) and a diode anode structure on the surface of the second N-drift region (32) along the lateral direction; the diode cathode structure comprises a second P-type well region (42) and a second P+ body contact region (52) located on the upper layer of the second P-type well region (42); the diode anode structure comprises a second N-type buffer layer (8) and a first N+ collector region (62) located on the upper layer of the second N-type buffer layer (8); the top P-type region (101) is located between the diode cathode structure and the diode anode structure, and its side surfaces are respectively in contact with the second N-type buffer layer (8) and the second P-type well region (42); the lead-out end of the second P+ body contact region is the diode cathode, and the lead-out end of the first N+ collector region (62) is the diode anode; The LIGBT portion forms a LIGBT cathode structure, a gate structure and a LIGBT anode structure on the surface of the first N drift region (31) along the lateral direction; the LIGBT cathode structure comprises a first P-type well region (41) and a first P+ body contact region (51) and an N+ emitter region (61) located on the upper layer of the first P-type well region (41) and arranged in sequence; the gate structure is a planar gate structure, comprising a gate dielectric layer (15) and a polysilicon material (16) covering the upper surface of the gate dielectric layer; the gate dielectric layer (15) is located on the first P between the N+ emitter region (61) and the first N drift region (31). The upper layer of the type well region has one end in contact with the upper surface of the N+ emitter region (61), and the other end in contact with the first N drift region (31); the LIGBT anode structure comprises a first N-type buffer layer (71) and a P+ collector region (72), and the P+ collector region (72) is located on the upper surface of the first N-type buffer layer (71); the common lead-out end of the first P+ body contact region (51) and the N+ emitter region (61) is the LIGBT cathode and is short-circuited with the diode cathode, the lead-out end of the polysilicon material (16) is the gate, and the lead-out end of the P+ collector region (72) is the LIGBT anode and is short-circuited with the diode anode; Features: The LIGBT anode structure also has an NMOS structure, comprising an anode gate, the first N-type buffer layer (71), a third P-type well region (74), a second N+ collector region (73), a third P+ body contact region (75) and a first electrode (11); the anode gate is a trench gate structure, located in the first N-type buffer layer (71), in contact with a side surface of the P+ collector region (72) away from the first N drift region (31), and the anode gate is composed of a gate dielectric layer (76) and a polysilicon electrode located in the gate dielectric layer (76). The third P-type well region (74) is located on the side of the anode gate away from the first N drift region (31), and its junction depth is lower than the anode gate depth; the second N+ collector region (73) and the third P+ body contact region (75) are respectively located at two ends of the upper layer of the third P-type well region (74), wherein the second N+ collector region (73) is in contact with the anode gate, the polysilicon electrode (77) and the lead-out ends of the second N+ collector region (73) are connected to the anode, and the lead-out end of the third P+ body contact region (75) is the first electrode (11); A second electrode (12) is provided on a side of the surface of the top P-type region (101) in the diode portion close to the first N+ collector region (62), and the second electrode (12) is short-circuited with the first electrode (11) in the LIGBT anode.

2. The adaptive high-voltage low-loss power device according to claim 1, characterized in that: The LIGBT portion has a top P-type region (102), the top P-type region (102) of the LIGBT is located on the upper layer of the first N drift region (31), between the LIGBT cathode structure and the LIGBT anode structure, and its side surface is not in contact with the first P-type well region (41).

3. The adaptive high-voltage low-loss power device according to claim 1, wherein the semiconductor material used in the device is one of Si, SiC, SiGe, GaAs, GaO and GaN.

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