Drive control circuit and drive method of a switching converter

Abstract

Disclose a driving control circuit and a driving method for a switching converter. The driving control circuit includes a loop control module, a lower transistor driving current regulating circuit, and a lower transistor driving circuit. The lower transistor driving current regulating circuit generates a driving current regulating signal according to a current sampling signal representing the current flowing through the lower transistor and a lower transistor control signal. The lower transistor driving circuit generates a lower transistor driving signal according to the lower transistor control signal and the driving current regulating signal. During the turn-off period of the lower transistor, if the current sampling signal is greater than the current reverse threshold, the driving current regulating signal reduces the lower transistor driving signal from a first value to a second value. During the turn-off period of the lower transistor, the lower transistor driving signal will change with the current value flowing through the lower transistor, without causing too large a voltage stress on the lower transistor, ensuring that the entire converter operates in a safe operating area.

Description

Technical Field

[0001] The present invention relates to electronic circuits, and more particularly, to a drive control circuit and method for a switching converter. Background Art

[0002] In the design of power supply chips, it is usually necessary to ensure that the power switch tube operates in the safe operating area. For example, in a buck switching converter, in order to prevent the problem that the lower transistor is coupled by the turn-on action of the upper transistor and becomes high, resulting in shoot-through, it is generally preferred to use a strong pull-down drive to turn off the lower transistor. However, in some applications, in order to pursue lower current, the buck switching converter will be controlled to operate in the forced continuous conduction mode (FCCM) under light load, that is: when the inductor current drops to zero, the lower transistor is not turned off, and the output capacitor at the load end will charge the inductor in reverse, and the current flowing through the lower transistor will reverse, that is, the current will flow from the drain of the lower transistor to its source. When the reverse current reaches a certain value and the lower transistor needs to be turned off, if the pull-down ability of the lower transistor is too strong at this time, it will cause too much voltage stress on the lower transistor, which does not meet the safe operating area, and even burn out in extreme cases. Summary of the Invention

[0003] The object of the present disclosure is to solve the above problems in the prior art, and proposes a drive control circuit and method for a switching converter. The present invention proposes a drive control circuit, which optimizes the above problems by detecting the magnitude of the current before the lower transistor is turned off to change the pull-down ability of the lower transistor during turn-off.

[0004] On the one hand, the present disclosure discloses a drive control circuit for a switching converter, the converter including an upper transistor and a lower transistor. The drive control circuit includes: a loop control module, configured to receive a voltage feedback signal and a current sampling signal, and generate an upper transistor control signal and a lower transistor control signal according to the voltage feedback signal and the current sampling signal, wherein the voltage feedback signal represents the output voltage signal of the converter, and the current sampling signal represents the current flowing through the lower transistor; a lower transistor drive current adjustment circuit, configured to receive the current sampling signal and the lower transistor control signal, and generate a drive current adjustment signal according to the current sampling signal and the lower transistor control signal; and a lower transistor drive circuit, configured to receive the lower transistor control signal and the drive current adjustment signal, and generate a lower transistor drive signal according to the lower transistor control signal and the drive current adjustment signal, wherein the lower transistor drive signal is used to drive the lower transistor to conduct and turn off, and during the turn-off of the lower transistor, if the current sampling signal is greater than a current reverse threshold, the drive current adjustment signal reduces the lower transistor drive signal from a first value to a second value.

[0005] Another aspect of the present disclosure discloses a driving method for the lower switch of a switching converter, including: sampling the current flowing through the lower switch to generate a current sampling signal; during the turn-off period of the lower switch, comparing the current sampling signal with a current reverse threshold; and if the current sampling signal is greater than the current reverse threshold, reducing the driving signal for turning off the lower switch from a first value to a second value. Description of the Drawings

[0006] Figure 1 The circuit schematic diagram of a switching converter according to an embodiment of the present disclosure is shown.

[0007] Figure 2 The circuit schematic diagrams of the lower switch driving current regulating circuit 14 and the lower switch driving circuit 15 according to an embodiment of the present disclosure are shown.

[0008] Figure 3 Shown is a circuit schematic diagram of the lower switch driving current regulating circuit 14 based on Figure 2 the lower switch driving circuit according to another embodiment of the present disclosure.

[0009] Figure 4 Shown is a circuit schematic diagram of the lower switch driving current regulating circuit 14 based on Figure 2 the lower switch driving circuit according to another embodiment of the present disclosure.

[0010] Figure 5 The circuit schematic diagrams of the lower switch driving current regulating circuit 14 and the lower switch driving circuit 15 according to another embodiment of the present disclosure are shown.

[0011] Figure 6 Shown is a circuit schematic diagram of the lower switch driving current regulating circuit 14 based on Figure 5 the lower switch driving circuit according to another embodiment of the present disclosure.

[0012] Figure 7 Shown is a driving method for turning off the lower switch of a switching converter according to an embodiment of the present invention.

[0013] As shown in the drawings, in all different views, the same reference numerals refer to the same parts. The drawings provided here are all for the purpose of illustrating embodiments, principles, concepts, etc., and are not drawn to scale. Detailed Description of the Embodiments

[0014] Next, specific embodiments of the present invention will be described non - restrictively with reference to the accompanying drawings. References to "an embodiment" or "an embodiment" throughout the specification mean that the particular features, structures, or characteristics described in connection with that embodiment are included in at least one embodiment of the present invention. Thus, the phrases "in an embodiment" or "in an embodiment" that appear throughout the specification do not necessarily all refer to the same embodiment. The verbs "comprise" and "have" are used herein as open limitations, which neither exclude nor require the presence of additional unrecited features. Unless otherwise expressly stated, the features recited in the dependent claims may be freely combined with each other. Elements defined with the use of "a" or "an" (i.e., in the singular form) throughout the document do not exclude the possibility of a plurality of such elements. Further, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Unless otherwise specified, the term "connected" is used to designate a direct electrical connection between circuit elements, while the term "coupled" is used to designate an electrical connection between circuit elements that may be direct or may be via one or more other elements. Conversely, when an element is said to be "directly connected to" or "directly coupled to" another element, there is no intermediate element. The term "and / or" used herein includes any and all combinations of one or more of the related listed items. When referring to the voltage of a node or terminal, unless otherwise indicated, the voltage is considered to be the voltage between that node and a reference potential (usually ground). Further, when referring to the potential of a node or terminal, unless otherwise indicated, the potential is considered to refer to the reference potential. The voltage and potential of a given node or given terminal will be further designated with the same reference numeral. A signal that alternates between a first logical state (e.g., a logical low state) and a second logical state (e.g., a logical high state) is called a "logic signal". The high and low states of different logic signals in the same electronic circuit may be different. In particular, the high and low states of a logic signal may correspond to voltages or currents that may not be completely constant in the high or low state.

[0015] Figure 1 FIG. shows a schematic circuit diagram of a switching converter according to an embodiment of the present disclosure. In Figure 1 the illustrated embodiment, the switching converter includes a switching circuit, an output inductor L, an output capacitor Cout, and a drive control circuit. The input terminal of the switching circuit receives an input voltage signal VIN; the output terminal of the switching circuit is coupled to one end of the output inductor L. The other end of the output inductor L is coupled to the output terminal of the switching converter; the capacitor Cout is coupled between the output terminal of the switching converter and the reference ground to provide an output voltage signal VOUT. By controlling the on - off switching of the controllable switch in the switching circuit, the input voltage signal VIN is converted into the output voltage signal VOUT.

[0016] In Figure 1In the illustrated embodiment, the switching circuit is shown as a switching circuit of a BUCK topology. The high-side transistor HS and the low-side transistor LS are serially coupled between the input terminal of the switching circuit 10 and the reference ground, and the common node of the high-side transistor HS and the low-side transistor LS is marked as the switching node SW. The output inductor L is coupled between the switching node SW and the output terminal of the switching converter. In Figure 1 In the illustrated embodiment, the high-side transistor HS and the low-side transistor LS are shown as N-type metal oxide semiconductor field effect transistors. Those of ordinary skill in the art can understand that in other embodiments, the high-side transistor HS and the low-side transistor LS may also include other suitable types of semiconductor switching devices, such as junction field effect transistors, insulated gate bipolar transistors, and double-diffused metal oxide semiconductors, etc.

[0017] In Figure 1 the illustrated embodiment, the drive control circuit of the switching converter includes an output voltage sampling circuit 2, a low-side transistor current sampling circuit 3, and a drive control circuit.

[0018] In Figure 1 the illustrated embodiment, the output voltage sampling circuit 2 is coupled to the output terminal of the switching converter for sampling the output voltage signal VOUT and generating a voltage feedback signal VFB, where the voltage feedback signal VFB represents the output voltage signal VOUT. In one embodiment, the output voltage sampling circuit 2 includes a voltage divider composed of resistors. In other embodiments, the output voltage sampling circuit 2 may also directly sample the output voltage signal VOUT.

[0019] In Figure 1 the illustrated embodiment, the low-side transistor current sampling circuit 3 is used to sample the current flowing through the low-side transistor LS and generate a current sampling signal VCS, where the current sampling signal VCS represents the current flowing through the low-side transistor LS. In one embodiment, the low-side transistor current sampling circuit 3 may include a sampling resistor serially connected to the low-side transistor LS, and the voltage across the sampling resistor can represent the current value flowing through the low-side transistor LS. In another embodiment, the switching converter may not include the low-side transistor current sampling circuit 3. After the low-side transistor LS is turned on, the voltage signal on the node SW (the voltage VSW generated by the on-resistance of the low-side transistor LS) can represent the current value flowing through the low-side transistor LS. That is to say, after the low-side transistor LS is turned on, the voltage signal VSW on the node SW is the current sampling signal VCS.

[0020] Continuing to refer to Figure 1 , in Figure 1In the illustrated embodiment, the drive control circuit includes a loop control module, a lower transistor drive current regulation circuit 14, a lower transistor drive circuit 15, and an upper transistor drive circuit 16. The loop control module controls the switching converter to operate in the FCCM mode in the light load mode, that is, after the inductor current drops to zero, the output capacitor Cout will continue to discharge through the lower transistor LS, and the inductor current increases in the reverse direction. Specifically, the loop control module includes a PWM control module 11, a comparison circuit 12, and a logic circuit 13

[0021] The PWM control module 11 receives the voltage feedback signal VFB and generates the upper transistor control signal CH and the inverted signal CL of the upper transistor control signal CH according to the voltage feedback signal VFB. The inverted signal CL of the upper transistor control signal CH is logically complementary to the upper transistor control signal CH, that is, when the upper transistor control signal CH is at a logical high level, the inverted signal CL is at a logical low level, and vice versa. The upper transistor control signal CH is used to control the conduction and turn-off of the upper transistor HS.

[0022] The comparison circuit 12 has a first input terminal, a second input terminal, and an output terminal. Its first input terminal receives the current sampling signal VCS; its second input terminal receives the maximum reverse current reference signal Vneg-max; the comparison circuit 12 compares the current sampling signal VCS and the maximum reverse current reference signal Vneg-max and generates a reverse current indication signal RES at the output terminal. Among them, the maximum reverse current reference signal Vneg-max represents the maximum reverse current allowed to flow through the lower transistor LS. Those of ordinary skill in the art can understand that in one embodiment, during the process of the inductor current dropping, the current will flow from the source electrode to the drain electrode of the lower transistor LS, and the current flowing in this direction is called "positive current"; when operating in the FCCM mode, after the inductor current drops to zero, the output capacitor Cout will continue to discharge through the lower transistor LS, and at this time the current will increase and flow from the drain electrode to the source electrode of the lower transistor LS, and the current flowing in this direction is called "reverse current". In one embodiment, the reverse current indication signal RES is a logical high and low level signal, having a first logical state (such as logical high) and a second logical state (such as logical low). In one embodiment, when the current sampling signal VCS is less than or equal to the maximum reverse current reference signal Vneg-max, the reverse current indication signal RES has a first logical state; when the current sampling signal VCS is greater than the maximum reverse current reference signal Vneg-max, the reverse current indication signal RES has a second logical state. In one embodiment, the comparison circuit 12 includes a voltage comparator, where the first input terminal of the comparison circuit 12 is the inverting input terminal of the voltage comparator; the second input terminal of the comparison circuit 12 is the non-inverting input terminal of the voltage comparator.

[0023] The logic circuit 13 receives the inverted signal CL and the reverse current indication signal RES, and performs a logic operation on the inverted signal CL and the reverse current indication signal RES to generate a lower transistor control signal CTL. The lower transistor control signal CTL is used to control the conduction and cutoff of the lower transistor LS. In one embodiment, when either the inverted signal CL or the reverse current indication signal RES has a second logic state (e.g., logic low), the lower transistor control signal CTL has a second logic state (e.g., logic low). In one embodiment, when the lower transistor control signal CTL has a first logic state, the lower transistor LS is turned on; when the lower transistor control signal CTL has a second logic state, the lower transistor LS is turned off. In one embodiment, the logic circuit 13 includes a logic AND gate circuit.

[0024] The lower transistor drive current regulation circuit 14 receives the lower transistor control signal CTL and the current sampling signal VCS, and generates a drive current regulation signal Reg according to the lower transistor control signal CTL and the current sampling signal VCS. The lower transistor drive current regulation circuit 14 generates the drive current regulation signal Reg according to the value of the current sampling signal VCS during the cutoff period of the lower transistor LS. The drive current regulation signal Reg is used to regulate the drive pull-down current when the lower transistor LS is turned off. Those of ordinary skill in the art can understand that: turning off the lower transistor LS requires a process and has a certain cutoff time. In one embodiment, the moment when the lower transistor control signal CTL changes from the first logic state to the second logic state (e.g., the falling edge moment) is the starting moment when the lower transistor starts to turn off.

[0025] In one embodiment, the drive current regulation signal Reg includes a logic high and low level signal, having a first logic state (e.g., logic high) and a second logic state (e.g., logic low). In one embodiment, the effective state of the drive current regulation signal Reg is the second logic state (logic low). In one embodiment, when the drive current regulation signal Reg is in the effective state, it is used to reduce the pull-down current when the lower transistor LS is turned off from a first value to a second value.

[0026] In yet another embodiment, the drive current regulation signal Reg includes an analog voltage signal. When the value of the current sampling signal VCS at the cutoff moment of the lower transistor LS is greater than the current reverse threshold (i.e., the lower transistor LS conducts a reverse current), the value of the drive current regulation signal Reg is inversely proportional to the value of the current sampling signal VCS, that is, the larger the amplitude of the current sampling signal VCS, the smaller the drive current regulation signal Reg, and thus the smaller the pull-down current of the lower transistor is regulated.

[0027] The lower transistor drive circuit 15 receives the lower transistor control signal CTL and the drive current regulation signal Reg, and generates a lower transistor drive signal DRVL according to the lower transistor control signal CTL and the drive current regulation signal Reg to drive the lower transistor LS to turn on and off. When controlling the lower transistor LS to turn off, the value of the lower transistor drive signal DRVL is regulated by the drive current regulation signal Reg, and its value will change with the value of the current sampling signal VCS.

[0028] The upper transistor drive circuit 16 receives the upper transistor control signal CH, and generates an upper transistor drive signal DRVH according to the upper transistor control signal CH to drive the upper transistor HS to turn on and off.

[0029] In Figure 1 the disclosed embodiment, the lower transistor drive signal DRVL (i.e., the pull-down current for turning off the lower transistor) will change with the current value flowing through the lower transistor. When the converter operates in the FCCM mode, the pull-down current for controlling the lower transistor to turn off automatically decreases, which will not cause too large a voltage stress on the lower transistor, ensuring that the entire converter operates in the safe operating area.

[0030] Figure 2 According to the embodiment of the present disclosure, the circuit schematic diagrams of the lower transistor drive current regulation circuit 14 and the lower transistor drive circuit 15 are further illustrated, and at the same time, the circuit schematic block diagram of the PWM control module 11 is illustrated.

[0031] Exemplarily, the lower transistor drive current regulation circuit 14 includes a sample and hold module 141 and a comparison circuit 142. The drive current regulation signal Reg includes a first drive current regulation signal Reg1

[0032] The sample and hold module 141 receives the lower transistor control signal CTL and the current sampling signal VCS, samples and holds the value of the current sampling signal VCS at the moment when the lower transistor control signal CTL changes from the first logic state to the second logic state (i.e., the starting moment when the lower transistor starts to turn off), and generates a sample and hold signal S / H.

[0033] The comparison circuit 142 has a first input terminal, a second input terminal, and an output terminal. Its first input terminal receives the sample-and-hold signal S / H; its second input terminal receives the current reverse threshold Vth1; the comparison circuit 12 compares the sample-and-hold signal S / H with the current reverse threshold Vth1 and generates a first drive current regulation signal Reg1 at the output terminal. Among them, the current reverse threshold Vth1 represents the zero-crossing point of the current flowing through the lower transistor LS. When the sample-and-hold signal S / H is less than or equal to the current reverse threshold Vth1, it represents that the lower transistor LS is flowing a positive current; when the sample-and-hold signal S / H is greater than the current reverse threshold Vth1, it represents that the lower transistor LS is flowing a reverse current. The amplitude of the current reverse threshold Vth1 is less than the amplitude of the maximum reverse current reference signal Vneg-max. In one embodiment, the current reverse threshold Vth1 includes a voltage signal, and its voltage value is equal to or approximately equal to the voltage value of the reference ground potential. Here, "approximately equal to" means slightly higher or slightly lower than the voltage value of the reference ground potential, and the error value is usually in the millivolt range. In one embodiment, the error value is determined by the bias voltage of the comparison circuit 142. In one embodiment, the first drive current regulation signal Reg1 is used to reduce the drive signal of the lower transistor LS from a first value to a second value. In one embodiment, the comparison circuit 142 includes a voltage comparator, where the first input terminal of the comparison circuit 142 is the inverting input terminal of the voltage comparator; the second input terminal of the comparison circuit 142 is the non-inverting input terminal of the voltage comparator.

[0034] Continuing to refer to Figure 2 , the lower transistor drive circuit 15 includes an inverter, pull-up transistors P0 and P1, pull-down transistors N0 and N1, and a first regulation switch transistor NM1.

[0035] The first end of the pull-up transistor P0 is coupled to the supply voltage VCC, the second end of the pull-up transistor P0 serves as the output terminal of the lower transistor drive circuit 15, and the control end of the pull-up transistor P0 receives the lower transistor control signal CTL through an inverter. The first end of the pull-up transistor P1 is coupled to the supply voltage VCC, the second end of the pull-up transistor P1 is coupled to the second end of the pull-up transistor P0, and the control end of the pull-up transistor P1 receives the lower transistor control signal CTL through an inverter. The first end of the pull-down transistor N0 is coupled to the second end of the pull-up transistor P0, the second end of the pull-down transistor N0 is electrically connected to the reference ground, and the control end of the pull-down transistor N0 receives the lower transistor control signal CTL through an inverter. The first end of the pull-down transistor N1 is coupled to the second end of the pull-up transistor P1, the control end of the pull-down transistor N1 receives the lower transistor control signal CTL through an inverter. The first end of the first regulation switch transistor NM1 is coupled to the second end of the pull-down transistor N1, the second end of the first regulation switch transistor NM1 is electrically connected to the reference ground, and the control end of the first regulation switch transistor NM1 receives the first drive current regulation signal Reg1.

[0036] When the lower transistor control signal CTL is at a logic low level, if the first drive current regulation signal Reg1 is at a logic high level, the pull-up transistors P0 and P1 are turned off, and the pull-down transistors N0 and N1 and the first regulation switch transistor NM1 are all turned on. The gate-source capacitance of the lower transistor LS discharges through the pull-down transistors N0 and N1 and the first regulation switch transistor NM1, and the pull-down current is strong, with a value of ibase + i1, and the lower transistor LS will be quickly turned off. When the lower transistor control signal CTL is at a logic low level, and at this time if the first drive current regulation signal Reg1 is at a logic low level, the pull-up transistors P0 and P1 and the first regulation switch transistor NM1 are all turned off, the pull-down transistors N0 and N1 are turned on, and the gate-source capacitance of the lower transistor LS discharges only through the pull-down transistor N0, and the pull-down current is ibase, the pull-down current is weak, and the lower transistor LS will slow down the turn-off speed. Therefore, the voltage stress on the lower transistor is not large, and it will not cause the upper and lower transistors to conduct directly, meeting the reliability requirements of the safe operating area. In the embodiment, the lower transistor drive signal DRVL includes a current signal. When the lower transistor LS is turned off, the current direction of the lower transistor drive signal DRVL is: from the gate of the lower transistor LS to the drive circuit 15 and then to the reference ground, and the lower transistor drive signal DRVL is the pull-down current of the lower transistor; when the lower transistor LS is turned on, the current direction of the lower transistor drive signal DRVL is: from the drive circuit 15 to the gate of the lower transistor LS.

[0037] In another embodiment, the lower transistor drive current regulation circuit 14 may also include other implementation manners. For example, as Figure 3 shown, the lower transistor drive current regulation circuit 14 is shown as a combination of a comparison circuit 142 and a first flip-flop 144, and the sample-and-hold module 141 is omitted.

[0038] In Figure 3 the example, the comparison circuit 142 further includes an enable terminal EN for receiving the lower transistor control signal CTL. During the turn-off period of the lower transistor starting from the moment when the lower transistor control signal CTL changes from the first logic state to the second logic state, the comparison circuit 142 is enabled. The comparison circuit 142 receives the current sampling signal VCS and the current reverse threshold Vth1, and compares the current sampling signal VCS with the current reverse threshold Vth1 to generate a first comparison signal CA1. The first flip-flop 144 receives the first comparison signal CA1 and outputs the first drive current regulation signal Reg1 at the moment when the valid edge of the first comparison signal CA1 arrives. The first drive current regulation signal Reg1 is used to turn off the first regulation switch transistor NM1 starting from the moment when the valid edge of the first comparison signal CA1 arrives.

[0039] In yet another embodiment, as Figure 4As shown, the lower transistor drive current regulation circuit 14 may also include a comparison circuit 142 and an amplitude amplification circuit 146. The comparison circuit 142 is enabled at the moment when the lower transistor control signal CTL changes from the first logic state to the second logic state. The comparison circuit 142 receives the current sampling signal VCS and the current reverse threshold Vth1, and compares the current sampling signal VCS with the current reverse threshold Vth1 to generate a first comparison signal CA1. The first comparison signal CA1 is used to enable the amplitude amplification circuit 146. After the amplitude amplification circuit 146 is enabled, it receives the current sampling signal VCS, and amplifies the amplitude of the current sampling signal VCS to generate a drive current regulation signal Reg.

[0040] In Figure 4 the embodiment, the drive current regulation signal Reg is an analog signal rather than a logic high or low level signal. The drive current regulation signal Reg is sent to the control terminal of the first regulation switch transistor NM1. When the current sampling signal VCS is greater than the current reverse threshold Vth1, the value of the drive current regulation signal Reg changes with the value of the current sampling signal VCS. Specifically: when the first comparison signal CA1 is valid, the amplitude amplification circuit 146 is enabled, and the value of the drive current regulation signal Reg changes with the value of the current sampling signal VCS. The higher the value of the current sampling signal VCS, the smaller the value of the drive current regulation signal Reg, the greater the on-resistance of the first regulation switch transistor NM1, and the smaller the current i1 flowing through it; when the first comparison signal CA1 is invalid, the amplitude amplification circuit 146 controls the drive current regulation signal Reg to have only a fixed voltage value, which is used to turn on the first regulation switch transistor NM1.

[0041] Continue to refer to Figure 2 , Figure 2 The circuit schematic diagram of the PWM control module 11 is also shown according to the embodiment of the present invention. In Figure 2 the example, the PWM control module 11 adopts a constant on-time control method, and includes an on-time control module 111, an off-time control module 112, and an RS flip-flop 113.

[0042] The on-time control module 111 is used to generate an on-time control signal TON, which is used to control the on-time of the upper transistor HS. The on-time control signal TON includes a logic signal with high and low logic levels. In one embodiment, when the on-time control signal TON changes from logic low to logic high, the conduction of the upper transistor HS ends and it is turned off.

[0043] The turn-off duration control module 112 receives the voltage feedback signal VFB and the voltage reference signal, and generates a turn-off duration control signal TOFF according to the voltage feedback signal VFB and the voltage reference signal. Among them, the voltage feedback signal VFB represents the output voltage signal VOUT of the switching converter. The turn-off duration control signal TOFF is used to control the turn-off duration of the high-side transistor HS. The turn-off duration control signal TOFF includes a logic signal with high and low logic levels. In one embodiment, when the turn-off duration control signal TOFF changes from logic low to logic high, the turn-off of the high-side transistor HS ends and it is turned on, and at the same time, the low-side transistor LS is turned off.

[0044] The set terminal S of the RS flip-flop 113 receives the turn-off duration control signal TOFF, the reset terminal R of the RS flip-flop receives the turn-on duration control signal TON, and the RS flip-flop outputs the high-side transistor control signal CH at the first output terminal Q, and at the second output terminal outputs the inverted signal CL of the high-side transistor control signal CH.

[0045] Those of ordinary skill in the art can understand that Figure 2 The PWM control module 11 in the example is only exemplary. In other embodiments, the switching converter can also adopt other control methods to generate the high-side transistor control signal CH and the inverted signal CL. The PWM control module 11 can select different modules according to different control methods.

[0046] Next, the detailed circuit principle of the control circuit in another embodiment of the present disclosure will be described in conjunction with Figure 5 Compared with the embodiment shown in Figure 2 In the shown embodiment, the low-side transistor drive current adjustment circuit 14 further adds a comparison circuit 143. At the same time, a pair of pull-up transistors P2 and pull-down transistors N2 and a second adjustment switch transistor NM2 are further added to the low-side transistor drive circuit 15. Next, the connection method and circuit principle of the newly added components will be described. In Figure 4 In the example, the drive current adjustment signal Reg includes a first drive current adjustment signal Reg1 and a second drive current adjustment signal Reg2

[0047] The comparison circuit 143 has a first input terminal, a second input terminal, and an output terminal. Its first input terminal receives the sample-and-hold signal S / H; its second input terminal receives the second threshold Vth2; the comparison circuit 143 compares the sample-and-hold signal S / H with the second threshold Vth2 and generates a second drive current regulation signal Reg2 at the output terminal. Among them, the amplitude of the second threshold Vth2 is greater than the amplitude of the current reverse threshold Vth1 and less than the amplitude of the maximum reverse current reference signal Vneg-max, that is: Vth1 < Vth2 < Vneg-max. In one embodiment, the comparison circuit 143 includes a voltage comparator, where the first input terminal of the comparison circuit 143 is the inverting input terminal of the voltage comparator; the second input terminal of the comparison circuit 143 is the non-inverting input terminal of the voltage comparator.

[0048] In the lower transistor driving circuit 15, the first end of the pull-up transistor P2 is coupled to the supply voltage VCC, the second end of the pull-up transistor P2 is coupled to the second end of the pull-up transistor P0, and the control end of the pull-up transistor P2 receives the lower transistor control signal CTL through an inverter. The first end of the pull-down transistor N2 is coupled to the second end of the pull-up transistor P2, and the control end of the pull-down transistor N2 receives the lower transistor control signal CTL through an inverter. The first end of the second regulating switch transistor NM2 is coupled to the second end of the pull-down transistor N2, the control end of the second regulating switch transistor NM2 receives the second drive current regulation signal Reg2, and the second end of the second regulating switch transistor NM2 is electrically connected to the reference ground.

[0049] When the lower transistor control signal CTL is logic low, if the first drive current regulation signal Reg1 is logic high, the pull-up transistors P0, P1, and P2 are turned off, and the pull-down transistors N0, N1, and N2 and the regulation switch transistors NM1 and NM2 are all turned on. The gate-source capacitance of the lower transistor LS discharges through the pull-down transistors N0, N1, and N2 and the regulation switch transistors NM1 and NM2, and the pull-down current is strong, with a value of ibase + i1 + i2, and the lower transistor LS will be quickly turned off. When the lower transistor control signal CTL is logic low, and at this time Vth1 < ICS < Vth2, then the first drive current regulation signal Reg1 is logic low while the second drive current regulation signal Reg2 is logic high, the pull-up transistors P0, P1, and P2 and the first regulation switch transistor NM1 are all turned off, the pull-down transistors N0, N1, and N2 and the second regulation switch transistor NM2 are turned on, and the gate-source capacitance of the lower transistor LS will discharge through the pull-down transistors N0 and N2 and NM2, and the pull-down current is ibase + i2, the pull-down current weakens, and the lower transistor LS will slow down the turn-off speed. When the lower transistor control signal CTL is logic low, and at this time Vth2 < ICS, the drive current regulation signals Reg1 and Reg2 are both logic low, the pull-up transistors P0, P1, and P2 and the regulation switch transistors NM1 and NM2 are all turned off, the pull-down transistors N0, N1, and N2 are turned on, and the gate-source capacitance of the lower transistor LS will only discharge through the pull-down transistor N0, and the pull-down current is further reduced to ibase, and the lower transistor LS will further slow down the turn-off speed. Therefore, the entire pull-down current of the lower transistor drive circuit 15 changes adaptively and is inversely proportional to the sampled voltage ICS. The larger the value of the current sampling signal VCS, the smaller the pull-down current, the slower the turn-off of the lower transistor LS, and the better the reliability.

[0050] Those of ordinary skill in the art should understand that although only three pairs of pull-up and pull-down transistors and two regulation switch transistors NM1 and NM2 are disclosed in the Figure 5 illustrated embodiment, in order to make the pull-down current better adapt to the change of the current sampling signal VCS, the lower transistor drive circuit 15 may include N (N is an integer greater than 3) pairs of pull-up and pull-down transistors and N - 1 regulation switch transistors, all of which are within the protection scope disclosed in this application.

[0051] Similarly, in another embodiment, Figure 5 the lower transistor drive current regulation circuit 14 in Figure 6 may also include other implementation manners. For example, as

[0052] Figure 6Both the comparison circuits 142 and 143 have an enable terminal EN for receiving the lower transistor control signal CTL. At the moment when the lower transistor control signal CTL changes from the first logic state to the second logic state, the comparison circuits 142 and 143 are enabled. The comparison circuit 142 receives the current sampling signal VCS and the current reverse threshold Vth1, and compares the current sampling signal VCS with the current reverse threshold Vth1 to generate a first comparison signal CA1. The comparison circuit 143 receives the current sampling signal VCS and the second threshold Vth2, and compares the current sampling signal VCS with the second threshold Vth2 to generate a second comparison signal CA2. The first flip-flop 144 receives the first comparison signal CA1 and outputs a first drive current regulation signal Reg1 at the effective edge of the first comparison signal CA1. The second flip-flop 145 receives the second comparison signal CA2 and outputs a second drive current regulation signal Reg2 at the effective edge of the second comparison signal CA2. The first drive current regulation signal Reg1 is also used to turn off the first regulating switch transistor NM1 starting from the effective edge of the first comparison signal CA1. The second drive current regulation signal Reg2 is also used to turn off the second regulating switch transistor NM2 starting from the effective edge of the second comparison signal CA2. The drive current regulation signal Reg includes the first drive current regulation signal Reg1 and the second drive current regulation signal Reg2.

[0053] In some other embodiments, it is also possible to Figure 5 the embodiment shown and Figure 4 the embodiment shown are used in combination. For example, while adjusting the current value i1 flowing through the first regulating switch transistor NM1, it is also possible to introduce and cut off the current value i2 flowing through the second regulating switch transistor NM2. To avoid obscuring the key points of the invention, no illustration and detailed description are provided here, but this does not affect that these are all within the protection scope of the present disclosure.

[0054] Figure 7 Shown is a driving method for turning off the lower transistor of a driving switch converter according to an embodiment of the present invention. This driving method can be used in the Figure 1-6 switch converter mentioned above. The switch converter adopting this driving method operates in the FCCM mode under light load. This turning-off method includes steps S1 - S3.

[0055] Step S1, sample the current flowing through the lower transistor and generate a current sampling signal VCS. In one embodiment, sampling the current flowing through the lower transistor includes sampling and holding the current flowing through the lower transistor at the moment when the lower transistor is turned off and generating a current sampling signal VCS (i.e., at this time, the current sampling signal VCS is also the aforementioned sample and hold signal H / S). In another embodiment, sampling the current flowing through the lower transistor includes sampling the current flowing through the lower transistor during the turn-off period of the lower transistor. In one embodiment, the turn-off moment of the lower transistor refers to the starting moment when the lower transistor starts to turn off. For example, when the control signal CTL of the lower transistor changes from the first logic state to the second logic state (e.g., the falling edge moment), it is the turn-off moment of the lower transistor; the turn-off period of the lower transistor refers to the time between the starting moment when the lower transistor starts to turn off and the ending moment.

[0056] Step S2, during the turn-off period of the lower transistor, compare the current sampling signal VCS with a current reverse threshold Vth1, and determine whether the current sampling signal VCS is greater than the current reverse threshold Vth1. If the current sampling signal VCS is greater than the current reverse threshold Vth1, proceed to step S3; if the current sampling signal VCS is less than the current reverse threshold Vth1, continue with step S2.

[0057] Step S3, reduce the lower transistor drive signal DRVL from the first value to the second value. In one embodiment, the lower transistor drive signal DRVL includes a drive current for turning off the lower transistor. In one embodiment, the second value is inversely proportional to the current sampling signal VCS, and the larger the current sampling signal VCS, the smaller the second value.

[0058] In addition, in step S2, if the current sampling signal VCS is less than the current reverse threshold Vth1, in addition to continuing to compare the current sampling signal VCS with the current reverse threshold Vth1, the lower transistor drive signal DRVL is also kept at the first value unchanged.

[0059] In another embodiment, the turn-off method further includes steps S4 - S5.

[0060] Step S4, compare the current sampling signal VCS with a second threshold signal Vth2, and determine whether the current sampling signal VCS is greater than the second threshold Vth2. If the current sampling signal VCS is greater than the second threshold Vth2, proceed to step S5; if the current sampling signal VCS is less than the second threshold Vth2, continue with step S4. In one embodiment, the second threshold Vth2 is greater than the current reverse threshold Vth1.

[0061] Step S5, reduce the lower transistor drive signal DRVL from the second value to the third value. In one embodiment, the second value is greater than the third value. In one embodiment, the third value is inversely proportional to the current sampling signal VCS, and the larger the current sampling signal VCS, the smaller the third value.

[0062] In addition, in step S4, if the current sampling signal VCS is less than the second threshold Vth2, in addition to continuing to compare the current sampling signal VCS with the second threshold Vth2, the lower transistor drive signal DRVL is also kept unchanged at the second value.

[0063] It should be noted that although the above embodiments have been described in detail based on the BUCK converter, the control circuits and methods disclosed above can also be used in other suitable topologies to prevent the upper and lower transistors from being directly connected when the lower transistor is turned off. Although the present invention has been described with reference to several exemplary embodiments, those of ordinary skill in the relevant art should understand that the terms used in the disclosed embodiments are illustrative and exemplary, rather than restrictive. They are only used to describe specific embodiments and do not limit the present invention. In addition, various modifications made by those of ordinary skill in the art to the disclosed embodiments in form and detail without departing from the principles and concepts of the present invention fall within the protection scope defined by the claims of this application or their equivalent scope.

Claims

1. A driving control circuit for a switching converter, the switching converter including an upper transistor and a lower transistor, characterized in that, The drive control circuit includes: A loop control module, configured to receive a voltage feedback signal and a current sampling signal, and generate an upper transistor control signal and a lower transistor control signal according to the voltage feedback signal and the current sampling signal, wherein the voltage feedback signal represents the output voltage signal of the switching converter, and the current sampling signal represents the current flowing through the lower transistor; A lower transistor drive current regulation circuit, configured to receive the current sampling signal and the lower transistor control signal, and generate a drive current regulation signal according to the current sampling signal and the lower transistor control signal; and A lower transistor drive circuit, configured to receive the lower transistor control signal and the drive current regulation signal, and generate a lower transistor drive signal according to the lower transistor control signal and the drive current regulation signal, wherein the lower transistor drive signal is used to drive the lower transistor to turn on and off. During the off period of the lower transistor, if the current sampling signal is greater than the current reverse threshold, the drive current regulation signal reduces the lower transistor drive signal from a first value to a second value.

2. The drive control circuit according to claim 1, characterized in that During the off period of the lower transistor, if the current sampling signal is greater than a second threshold, the drive current regulation signal reduces the lower transistor drive signal from the second value to a third value, wherein the second threshold is greater than the current reverse threshold.

3. The drive control circuit according to claim 1, wherein The second value is inversely proportional to the current sampling signal.

4. The drive control circuit according to claim 1, wherein The drive current regulation signal includes a first drive current regulation signal, and the drive current regulation circuit includes: A sample and hold module, configured to receive the lower transistor control signal and the current sampling signal, sample and hold the value of the current sampling signal at the moment when the lower transistor control signal changes from a first logic state to a second logic state, and generate a sample and hold signal; and A first comparison circuit, configured to receive the sample and hold signal, and compare the sample and hold signal with the current reverse threshold to generate a first drive current regulation signal.

5. The drive control circuit according to claim 1, characterized in that The drive current regulation signal includes a first drive current regulation signal, and the drive current regulation circuit includes: A first comparison circuit, having a first input terminal, a second input terminal, an enable terminal and an output terminal. The first input terminal of the first comparison circuit receives the current sampling signal, the second input terminal of the first comparison circuit receives the current reverse threshold, the enable terminal of the first comparison circuit receives the lower transistor control signal. After being enabled by the lower transistor control signal, the first comparison circuit compares the current sampling signal with the current reverse threshold to generate a first comparison signal; and A first flip-flop, configured to receive the first comparison signal, and generate a first drive current regulation signal at the effective edge of the first comparison signal CA1.

6. The drive control circuit according to claim 1, wherein The drive current regulation signal includes a first drive current regulation signal, and the drive current regulation circuit further includes: A first comparison circuit, having a first input terminal, a second input terminal, an enable terminal and an output terminal. The first input terminal of the first comparison circuit receives the current sampling signal, the second input terminal of the first comparison circuit receives the current reverse threshold, the enable terminal of the first comparison circuit receives the lower transistor control signal. After being enabled by the lower transistor control signal, the first comparison circuit compares the current sampling signal with the current reverse threshold to generate a first comparison signal; and The amplitude amplification circuit has an enable terminal, an input terminal, and an output terminal. The enable terminal of the amplitude amplification circuit receives a first comparison signal, and the input terminal of the amplitude amplification circuit receives a current sampling signal. After being enabled by the first comparison signal, the amplitude amplification circuit amplifies the amplitude of the current sampling signal and generates a first drive current adjustment signal at the output terminal.

7. The drive control circuit according to claim 4, characterized in that, The drive current adjustment signal includes a first drive current adjustment signal and a second drive current adjustment signal. The drive current adjustment circuit further includes: A second comparison circuit for receiving a sample-and-hold signal and comparing the sample-and-hold signal with a second threshold to generate a second drive current adjustment signal, where the second threshold is greater than the current reverse threshold.

8. The drive control circuit according to any one of claims 4-6, characterized in that, The lower transistor drive circuit includes: A first pull-up transistor, the first end of the first pull-up transistor is coupled to the supply voltage, the second end of the first pull-up transistor serves as the output terminal of the lower transistor drive circuit, and the control end of the first pull-up transistor receives the lower transistor control signal through an inverter; A second pull-up transistor, the first end of the second pull-up transistor is coupled to the supply voltage, the second end of the second pull-up transistor is coupled to the second end of the first pull-up transistor, and the control end of the second pull-up transistor receives the lower transistor control signal through an inverter; A first pull-down transistor, the first end of the first pull-down transistor is coupled to the second end of the first pull-up transistor, the second end of the first pull-down transistor is electrically connected to the reference ground, and the control end of the first pull-down transistor receives the lower transistor control signal through an inverter; A second pull-down transistor, the first end of the second pull-down transistor is coupled to the second end of the second pull-up transistor, and the control end of the second pull-down transistor receives the lower transistor control signal through an inverter; and A first adjustment switch transistor, the first end of the first adjustment switch transistor is coupled to the second end of the second pull-down transistor, the second end of the first adjustment switch transistor is electrically connected to the reference ground, and the control end of the first adjustment switch transistor receives the first drive current adjustment signal.

9. The drive control circuit according to claim 7, characterized in that, The lower transistor drive circuit includes: A first pull-up transistor, the first end of the first pull-up transistor is coupled to the supply voltage, the second end of the first pull-up transistor serves as the output terminal of the lower transistor drive circuit, and the control end of the first pull-up transistor receives the lower transistor control signal through an inverter; A second pull-up transistor, the first end of the second pull-up transistor is coupled to the supply voltage, the second end of the second pull-up transistor is coupled to the second end of the first pull-up transistor, and the control end of the second pull-up transistor receives the lower transistor control signal through an inverter; A third pull-up transistor, the first end of the third pull-up transistor is coupled to the supply voltage, the second end of the third pull-up transistor is coupled to the second end of the first pull-up transistor, and the control end of the third pull-up transistor receives the lower transistor control signal through an inverter; A first pull-down transistor, the first end of the first pull-down transistor is coupled to the second end of the first pull-up transistor, the second end of the first pull-down transistor is electrically connected to the reference ground, and the control end of the first pull-down transistor receives the lower transistor control signal through an inverter; A second pull-down transistor, the first end of the second pull-down transistor is coupled to the second end of the second pull-up transistor, and the control end of the second pull-down transistor receives the lower transistor control signal through an inverter; A third pull-down transistor, the first end of the third pull-down transistor is coupled to the second end of the third pull-up transistor, and the control end of the third pull-down transistor receives the lower transistor control signal through an inverter; A first regulating switch transistor, a first end of the first regulating switch transistor is coupled to a second end of a second pull-down transistor, a second end of the first regulating switch transistor is electrically connected to a reference ground, and a control end of the first regulating switch transistor receives a first drive current regulating signal; and A second regulating switch transistor, a first end of the second regulating switch transistor is coupled to a second end of a third pull-down transistor, a second end of the second regulating switch transistor is electrically connected to a reference ground, and a control end of the second regulating switch transistor receives a second drive current regulating signal.

10. The drive control circuit according to claim 1, wherein The loop control module includes: A PWM control module, configured to receive a voltage feedback signal and generate an upper transistor control signal and an inverted signal of the upper transistor control signal according to the voltage feedback signal; A third comparison circuit, configured to receive a current sampling signal and a maximum reverse current reference signal, and compare the current sampling signal with the maximum reverse current reference signal to generate a reverse current indication signal, wherein the maximum reverse current reference signal is greater than a current reverse threshold; and A logic circuit, configured to receive the inverted signal of the upper transistor control signal and the reverse current indication signal, and perform a logic operation on the inverted signal of the upper transistor control signal and the reverse current indication signal to generate a lower transistor control signal.

11. A driving method applied to a lower transistor of a switching converter, including: Sampling the current flowing through the lower transistor and generating a current sampling signal; During the turn-off period of the lower transistor, comparing the current sampling signal with a current reverse threshold; And If the current sampling signal is greater than the current reverse threshold, reducing the driving signal for turning off the lower transistor from a first value to a second value.

12. The driving method according to claim 11, characterized in that, The driving method further includes: During the turn-off period of the lower transistor, comparing the current sampling signal with a second threshold, wherein the second threshold is greater than the current reverse threshold; and If the current sampling signal is greater than the second threshold, reducing the driving signal for turning off the lower transistor from the second value to a third value.

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