A data preprocessing unit for broadband digital array radar

Abstract

The present invention discloses a data preprocessing unit for a broadband digital array radar, comprising: a phase-locked loop module, which generates a system clock and an operating clock required by an analog-to-digital conversion module based on an input reference signal; an analog-to-digital conversion module, which receives the intermediate frequency signal of the broadband digital array radar and converts it into a digital signal; a bus module, which interconnects and exchanges signals between the various modules of the data preprocessing unit; a control information decoding module, which parses the control information received by the data preprocessing unit to obtain operating parameter configuration information and outputs it to the corresponding module via the bus module; and a down-conversion module, which performs speed reduction, amplitude and phase compensation, frequency conversion, and / or beamforming on the data converted by the analog-to-digital conversion module. Based on the concept of integration, the present invention integrates the modules into an integrated design, and can achieve different operating modes by externally changing the control information, greatly improving the flexibility and scope of application.

Description

Technical Field

[0001] The present invention relates to the field of radar receiver chip design, and more particularly to a data preprocessing unit for a broadband digital array radar. Background Art

[0002] With the advancement of digital technology and integrated circuit processing, digital TR components are increasingly being used in systems such as radar and satellite communications. Simultaneously, with the continuous increase in radar bandwidth and the development of high-speed signal processing technology, radar systems have higher demands for the speed and efficiency of large-scale data transmission. In wideband digital array radars, due to the large number of array elements, using traditional FPGA-based digital components to complete digital array transceiver processing is costly and bulky. The digitization and chip-based implementation of transceiver components are the future development trends of radar technology. Therefore, for wideband radar reception, it is essential to implement chip-based, highly integrated receive links and data preprocessing. Summary of the Invention

[0003] One objective of the present invention is to provide a data preprocessing unit for a broadband digital array radar, addressing the high cost and large footprint of existing FPGA (field programmable gate array) chips when used on a large scale. By integrating the downconversion link and data preprocessing into a single chip and integrating the analog ADC (analog-to-digital converter) core into a hybrid digital-analog integration, the system achieves a 640Msps sampling rate for radar received data, effectively reducing system cost and chip size while also offering low power consumption and high integration.

[0004] In order to achieve the above object, the present invention adopts the following technical solutions:

[0005] A data preprocessing unit for a broadband digital array radar comprises a phase-locked loop module, an analog-to-digital conversion module, a bus module, a synchronization pulse module, a control information decoding module and a plurality of down-conversion modules; wherein,

[0006] The phase-locked loop module generates the system clock and the working clock required by the analog-to-digital conversion module based on the input reference signal;

[0007] An analog-to-digital conversion module is used to receive the intermediate frequency signal of the broadband digital array radar and convert it into a digital signal;

[0008] Bus module, used for interconnection and signal interaction among various modules of the data preprocessing unit;

[0009] A control information decoding module, configured to parse the control information received by the data preprocessing unit to obtain working parameter configuration information and output the information to a corresponding module via a bus module;

[0010] The down-conversion module is used to perform speed reduction, amplitude and phase compensation, frequency conversion and / or beamforming on the data converted by the analog-to-digital conversion module.

[0011] Preferably, the phase-locked loop module generates a 640 MHz sampling clock for ADC (analog-to-digital conversion) and a 640 MHz system clock for internal digital logic through an 80 MHz reference clock.

[0012] Preferably, the analog-to-digital conversion module adopts a 65nm process to be a 4-channel 16-bit analog-to-digital converter, supports differential signals, and has a maximum sampling rate of 1 Gbps.

[0013] Preferably, the data pre-processing unit further comprises: a mode configuration module, configured to configure the working mode of the down-conversion module according to the control information parsed by the control information decoding module.

[0014] Preferably, the bus module adopts a virtual cross-interconnected network, and two transmission paths that do not interfere with each other can occupy the bus for data transmission at the same time.

[0015] Preferably, the data pre-processing unit further comprises: a synchronization pulse module, configured to perform anti-collision edge adjustment based on a phase relationship between an external synchronization signal and a system clock.

[0016] The synchronization pulse module completes the detection of the phase relationship between the external input synchronization signal and the system 640MHz clock and outputs the detection result, and can adjust the reference synchronization pulse delay according to the control information analyzed by the control information decoding module to avoid collision with the system clock.

[0017] Preferably, the down-conversion module comprises a plurality of down-conversion channels, each of which comprises: an extraction module, an IQ (in-phase orthogonal signal) bias module, an NCO (digital oscillator) module, an equalization filter module and an FIR (finite impulse response filter) filter module;

[0018] The extraction module is used to reduce the speed of the data output by the analog-to-digital conversion module;

[0019] An IQ (in-phase quadrature signal) bias module, configured to perform quadrature correction and DC bias on the down-scaling data;

[0020] The FIR (Finite Length Unit Impulse Response Filter) filtering module is used to perform FIR (Finite Length Unit Impulse Response Filter) filtering on the processed data;

[0021] The equalization filter module is used to perform amplitude and phase equalization processing on the data after the FIR (finite impulse response filter) filtering processing.

[0022] Preferably, the down-conversion module further comprises: a DBF (digital beamforming) module for performing a synthesis operation on data output by any down-conversion channel to generate a baseband signal of beam pointing information.

[0023] Preferably, the NCO (digital oscillator) module is used to perform frequency conversion on the data into a baseband signal;

[0024] The NCO (digital oscillator) module outputs sinusoidal waveform data and is driven by a 640 MHz clock during down-conversion to generate an orthogonal digital waveform of a configured frequency and mix the input digital signal so that the baseband signal contains phase information.

[0025] Preferably, the down-conversion channel further comprises: a de-dithering module for performing a descrambling operation on the data output by the analog-to-digital conversion module to restore the original data.

[0026] Preferably, the down-conversion channel further comprises: a CIC (Integrator-Comb Filter) filtering module, which is used for filtering and sampling the input data.

[0027] Preferably, the system operating clock can be up to 640M.

[0028] The data pre-processing unit is designed using a 28nm process and is integrated with an ADC (analog-to-digital conversion) core via a SIP (system-in-package).

[0029] The operating voltages of the analog-to-digital conversion module include: 0.9V, 1.8V, 1.2V, and 1V.

[0030] The beneficial effects of the present invention are as follows:

[0031] The present invention is based on a high-sampling-rate ADC (analog-to-digital conversion) core using a 65nm advanced process and adopts a mixed-analog SOC (system-on-chip) design method to achieve a highly integrated, chip-based design of a broadband data pre-processing unit. This allows the processing of data received by a broadband radar and outputs it as 16-channel digital baseband IQ signals (co-directional and quadrature signals). This has the advantages of high integration, low power consumption, low cost, and miniaturization for mass production applications. Furthermore, the present invention can be integrated into other chips as a third-party IP, and its operating mode can be flexibly configured by externally modifying control information. This makes the present invention widely applicable to fields such as digital array radars and communication systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0033] Figure 1 A schematic diagram of a data preprocessing unit provided in an embodiment of the present invention;

[0034] Figure 2 A schematic diagram of a phase-locked loop module provided in an embodiment of the present invention;

[0035] Figure 3 A schematic diagram of an analog-to-digital conversion module provided in an embodiment of the present invention;

[0036] Figure 4 A schematic diagram of a bus module provided in an embodiment of the present invention;

[0037] Figure 5 A schematic diagram of a synchronization pulse provided by an embodiment of the present invention;

[0038] Figure 6 A diagram of a delay link of an electrical synchronization signal provided by an embodiment of the present invention;

[0039] Figure 7 A structural diagram of a down-conversion module provided in an embodiment of the present invention;

[0040] Figure 8 A schematic diagram of a CIC filter module provided in an embodiment of the present invention;

[0041] Figure 9 A schematic diagram of an FIR filter module provided in an embodiment of the present invention;

[0042] Figure 10 A schematic diagram of an NCO module provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0043] In order to explain the present invention more clearly, the following is a summary of the preferred embodiments and the accompanying drawings. Figure 1-10 The present invention will be further described. Similar components in the accompanying drawings are denoted by the same reference numerals. Those skilled in the art will appreciate that the following detailed description is illustrative and non-restrictive and should not be construed to limit the scope of protection of the present invention. The present invention provides a data preprocessing unit for a broadband digital array radar, which addresses the high cost and bulkiness associated with the existing large-scale use of FPGAs.

[0044] A data preprocessing unit for a broadband digital array radar comprises a phase-locked loop module, an analog-to-digital conversion module, a bus module, a synchronization pulse module, a control information decoding module and a plurality of down-conversion modules; wherein,

[0045] The phase-locked loop module generates the system clock and the working clock required by the analog-to-digital conversion module based on the input reference signal;

[0046] An analog-to-digital conversion module is used to receive the intermediate frequency signal of the broadband digital array radar and convert it into a digital signal;

[0047] Bus module, used for interconnection and signal interaction among various modules of the data preprocessing unit;

[0048] A control information decoding module, configured to parse the control information received by the data preprocessing unit to obtain working parameter configuration information and output the information to a corresponding module via a bus module;

[0049] The down-conversion module is used to perform speed reduction, amplitude and phase compensation, frequency conversion and / or beamforming on the data converted by the analog-to-digital conversion module.

[0050] Preferably, the phase-locked loop module generates a 640 MHz sampling clock for ADC (analog-to-digital conversion) and a 640 MHz system clock for internal digital logic through an 80 MHz reference clock.

[0051] Preferably, the analog-to-digital conversion module adopts a 65nm process to be a 4-channel 16-bit analog-to-digital converter, supports differential signals, and has a maximum sampling rate of 1 Gbps.

[0052] Preferably, the data pre-processing unit further comprises a mode configuration module, configured to configure the working mode of the down-conversion module according to the control information parsed by the control information decoding module.

[0053] Preferably, the bus module adopts a virtual cross-interconnection network, and two transmission paths that do not interfere with each other can occupy the bus for data transmission at the same time.

[0054] Preferably, the data pre-processing unit further comprises a synchronization pulse module for performing anti-collision edge adjustment based on the phase relationship between the external synchronization signal and the system clock.

[0055] The synchronization pulse module completes the detection of the phase relationship between the external input synchronization signal and the system 640MHz clock and outputs the detection result, and can adjust the reference synchronization pulse delay according to the control information analyzed by the control information decoding module to avoid collision with the system clock.

[0056] Preferably, the down-conversion module comprises a plurality of down-conversion channels, each of which comprises: an extraction module, an IQ (in-phase orthogonal signal) bias module, an NCO (digital oscillator) module, an equalization filter module and an FIR (finite impulse response filter) filter module;

[0057] The extraction module is used to reduce the speed of the data output by the analog-to-digital conversion module;

[0058] An IQ (in-phase quadrature signal) bias module, configured to perform quadrature correction and DC bias on the down-scaling data;

[0059] The FIR (Finite Length Unit Impulse Response Filter) filtering module is used to perform FIR (Finite Length Unit Impulse Response Filter) filtering on the processed data;

[0060] The equalization filter module is used to perform amplitude and phase equalization processing on the data after the FIR (finite impulse response filter) filtering processing.

[0061] Preferably, the down-conversion module further comprises a DBF (digital beamforming) module for performing a synthesis operation on the data output by any down-conversion channel to generate a baseband signal of beam pointing information.

[0062] Preferably, the NCO (digital oscillator) module is used to perform frequency conversion on the data into a baseband signal;

[0063] The NCO (digital oscillator) module outputs sinusoidal waveform data and is driven by a 640 MHz clock during down-conversion to generate an orthogonal digital waveform of a configured frequency and mix the input digital signal so that the baseband signal contains phase information.

[0064] Preferably, the down-conversion channel further comprises: a de-dithering module for performing a descrambling operation on the data output by the analog-to-digital conversion module to restore the original data.

[0065] Preferably, the down-conversion channel further comprises: a CIC (Integrator-Comb Filter) filtering module, which is used for filtering and sampling the input data.

[0066] Preferably, the system operating clock can be up to 640M.

[0067] The data pre-processing unit is designed using a 28nm process and is integrated with an ADC (analog-to-digital conversion) core via a SIP (system-in-package) package.

[0068] The operating voltages of the digital-to-analog conversion module include: 0.9V, 1.8V, 1.2V, and 1V.

[0069] The present invention is a digital-analog hybrid SOC chip, comprising a phase-locked loop module, an analog-to-digital conversion module, a bus module, a synchronization pulse module, a control information decoding module, and four identical down-conversion modules. The phase-locked loop module generates the system clock and the operating clock required by the analog-to-digital conversion module. The analog-to-digital conversion module receives the intermediate frequency signal and converts it into a digital signal. The bus module is used to interconnect the various modules and transmit control words and data between the modules. The synchronization pulse module completes the detection of the phase relationship between the external synchronization signal and the system clock and outputs the detection result. It can also adjust the reference synchronization pulse delay according to the control word to avoid collision with the system clock. The control information decoding module parses the received control word information according to a certain protocol to obtain the parameter configuration required for the operation of each module and outputs it to the specified module interface. The down-conversion module realizes the speed reduction, amplitude and phase compensation, frequency conversion and beamforming of the broadband radar received data.

[0070] A specific embodiment:

[0071] The present invention is further described in detail by taking the receiving working state of a broadband digital array radar under a 640Mhz system clock as an example.

[0072] like Figure 1 As shown, the present invention includes a phase-locked loop module, an analog-to-digital conversion module, a bus module, a synchronization pulse module, a control information decoding module and four identical down-conversion modules.

[0073] After the module is powered on, the phase-locked loop (PLL) starts up first. Based on the default configuration, it generates a 640MHz sampling clock for the analog-to-digital conversion module and a 640MHz system clock for the digital logic, as well as 80MHz and 160MHz clocks, from an external 240MHz clock. This is the foundation for the entire chip's operation. The ADC module receives an external differential intermediate frequency (IF) signal, performs analog-to-digital conversion, and outputs a 16-bit differential digital signal to the internal digital logic. The bus module interconnects the various modules within the chip, transmitting control words and data between them. When a synchronization pulse signal arrives, the synchronization pulse module detects the phase relationship between the external synchronization signal and the system 640MHz clock and outputs the result. It also adjusts the reference synchronization pulse delay based on the control word to avoid edge collision with the system clock. The control information decoding module identifies the received control word data stream and parses it according to a specific digital protocol. It obtains the operating parameter configuration information for each module and stores it in registers. All control word information takes effect on the rising edge of the synchronization pulse signal, completing the configuration.

[0074] like Figure 2 As shown, the phase-locked loop module includes a phase detector, loop filter, voltage-controlled oscillator, and frequency divider. This circuit uses an external reference signal to control the frequency and phase of the loop's internal oscillator signal, creating a feedback control circuit. After the system is powered on, the module's external 240MHz reference clock is fed back and divided by a fractional frequency divider to produce 80MHz, 160MHz, and 640MHz clocks with fixed phase relationships. The 80MHz and 160MHz clocks are used by the synchronization pulse module to align and phase-adjust the synchronization pulse signals. The 640MHz clock provides the sampling clock for the analog-to-digital conversion module and serves as the system clock for the digital logic.

[0075] like Figure 3As shown, the analog-to-digital conversion module consists of a reference bias module, an efuse (programmable memory) module, an SPI module, a buffer module, an ADC (analog-to-digital conversion) core module, and a digital calibration module. The ADC core utilizes a low-power pipeline architecture and a 65nm CMOS process, offering a resolution of 12 bits and a maximum conversion speed of 1Gbps. It also includes an input buffer and a reference buffer. The output interface is differential, with supply voltages of 1.8V / 1.2V / 1.0V. Power consumption per channel is approximately 200mW. After power-on, the ADC core's internal registers can be read and written via the SPI module interface to configure the module's operating mode.

[0076] like Figure 4 As shown, the bus utilizes a virtual crossbar interconnection network, allowing two independent transmission paths to simultaneously occupy the bus for data transmission. The physical implementation of the bus does not utilize a real crossbar network; instead, a virtual crossbar interconnection is implemented within the bus arbiter, saving space and reducing power consumption. Specifically, the arbiter maintains two record tables: the input port table and the output port occupation table. Each input port in the input port table occupies one row, containing the port occupation and output destination port. Each output port in the output port table occupies one row, containing the port occupation flag. When a new data packet header appears at the input, the output port occupation table searches for the corresponding interface bit. If the port is occupied, a waiting signal is returned. If the output port is unoccupied, the bit flag is set to 1, and both the input port occupation and output destination port values ​​in the input table are set to 1. This successfully establishes a virtual connection between the input and output ports. When multiple virtual connections are successfully established, the actual bus occupation is determined by the arbiter. The fiber input port assigned by the arbiter has the highest priority, and all fiber-based input information is immediately output to the bus in the next cycle. Other input ports use a round-robin approach to determine the next bus connection to occupy, ensuring fair port usage and increasing bus utilization. When an input packet is transmitted, the input port is disconnected, and the input table entry for the port occupied is cleared. The output port occupied bit corresponding to the output destination port stored in that entry is then cleared.

[0077] like Figure 5As shown, there are two input modes for synchronization pulse signals: an optical synchronization signal input from an optical fiber, and an electrical synchronization signal provided from a chip pin. These two synchronization signals together generate an on-chip synchronization trigger signal, with all other timing information aligned to this synchronization signal. The synchronization signal input from the optical fiber is converted to the 640MHz master clock domain via an asynchronous FIFO (first-in, first-out buffer). Due to unstable timing, the optical synchronization signal is subjected to a fixed delay adjustment. The shift length is set by the control word configuration register, with a step size of one 640MHz clock.

[0078] For electrical synchronization signals input from outside the chip, such as Figure 6 As shown, the monitoring circuit uses multiple DELAY units to construct a delay line for the synchronization signal chain, generating multiple synchronization signal replicas with defined delay relationships. Since the 80MHz, 160MHz, and 640MHz clocks output by the PLL have a fixed phase relationship, phase monitoring and adjustment of the synchronization signal with the 80MHz clock is sufficient. The delays of the four modules D5, D6, D7, and D8 are each set to approximately 3.125ns, or 1 / 4 of the 80MHz clock period. Therefore, the phase difference between the synchronization signal replicas Trig1-Trig5 is 1 / 4 of the 80MHz clock period, or 90 degrees. The 80MHz sampling values ​​of the synchronization signal replicas Trig1-Trig5 can be used to determine the phase relationship between the Trig1 signal (i.e., the synchronization output signal) and the 80MHz clock signal. Based on this phase relationship, the monitoring circuit outputs four phase relationship indicators: 0-90 degrees, 90-180 degrees, 180-270 degrees, and 270-360 degrees.

[0079] The adjustment circuit can adjust the delay of Trig1 to Trig5 synchronization signals by selecting the output of D0 to D4, changing their phase relationship relative to 80MHz, thereby achieving the purpose of adjustment.

[0080] like Figure 7 As shown in the figure, the digital down-conversion module includes a de-dithering module, an amplitude adjustment module, a delay module, an NCO module, a CIC module, an FIR module, an equalization filter module, a decimation module, and a DBF module. This module receives the 640MHz sampled data output by the analog-to-digital conversion module and performs digital orthogonal down-conversion, filtering, and decimation on the intermediate frequency digital signal based on the contents of relevant registers. It supports dual-frequency operation and outputs four digital baseband IQ signals.

[0081] The module can configure the FIR filter coefficients, data decimation rate, and whether to use the CIC filter according to different operating modes. It can also dynamically control the frequency, frequency increment, and phase of the NCO. It also has the ability to simulate down-converted signals. Under relevant control, it uses sequential or random numbers instead of baseband data to check the sampling range, the number of data sent, and the correctness of the data transmission.

[0082] After the data output from the A / D converter enters the signal processing module, it can be optionally dithered. The amplitude gain and DC offset are then adjusted based on the control word, and input delay is adjusted. The NCO generates a quadrature IF signal, which is multiplied and mixed with the IF digital signal input from the A / D converter. The signal then passes through the bypassable CIC module, which is 6th-order and defaults to decimation by 2. This is suitable for applications with limited bandwidth where using only the FIR would be resource-intensive. The FIR is a fixed-order 63-order lowpass filter with programmable coefficients. Both the I / Q signals pass through the same FIR filter to achieve complex filtering. After lowpass filtering, the I / Q signals are decimated by a factor of n based on the control word. Finally, the DBF module centrally weights and packages the data from the selected channels for output to the radar digital signal processor.

[0083] like Figure 8 As shown, the CIC module filters and samples the input data. The transfer function is: (1-z^(-R))^6 / (1-z^(-1))^6. Where R is the undersampling rate. The sampling function is approximately a low-pass filter with a low-pass bandwidth less than fclk / R, where fclk is the 640MHz system clock frequency. Out-of-band rejection is related to the order. At 6th order, out-of-band rejection is greater than 40dB. The module uses 6th-order CIC with an undersampling rate of 2 or 4. Six first-order IIR feedbacks are performed before the undersampling module, followed by six first-order FIR filters. In actual implementation, the transfer function is expanded to obtain the transfer function for the first half: The transfer function of the second half is 1-6z -1 +15z -2 -20z -3 +15z -4 -6z -5 The front and back halves are implemented using fixed coefficient multipliers constructed using the expanded transfer function.

[0084] like Figure 9As shown in the figure, the FIR filter is designed as a lowpass filter. During downconversion, it filters the mixed and CIC-sampled signal to obtain a clean baseband signal. A 63-tap FIR filter is used. The FIR coefficients can be selected from internal defaults or configured externally. The 32nd coefficient is a 16-bit unsigned number, and the remaining 62 coefficients are signed. This filter is symmetrical, with symmetrical FIR coefficients. Only 32 coefficients need to be entered during configuration. After FIR filtering, the result must be normalized. When using internal coefficients, select the corresponding normalization coefficients. When configuring the filter coefficients externally, both the normalization coefficient and the truncation coefficient must be written to the final register.

[0085] like Figure 10 As shown, the NCO contains two sets of frequency / frequency increment registers, and the initial values ​​of these two sets of registers are set externally. The registers can be switched by the control bit, and the unused registers will keep the value unchanged when switching. The high 16-bit result after rounding the decimal places used in the lookup table. The first two bits determine the output sign, the third bit determines the sin / cos exchange, and the remaining 13 bits of data are used for lookup. Lookup table 1 records the sin and cos results in the range of (π / 8,π / 4], and lookup table 2 records the non-sin / cos results near π / 8. The accuracy of the two lookup tables is 17 decimal places. The phase of the results is then added using the sum angle formula to output a result with 16 decimal places of accuracy. A total of 192 items are used in the sin / cos function table, each 32 bits, sin and cos each occupy 16 bits, and the 1st to 16th decimal places are recorded. The integer part of Sin and the first decimal place are all 0, with the integer portion and first decimal place of cos being 0 and 1, respectively. The NCO phase lookup table entry uses a total of 16 bits, corresponding to a phase noise spur of approximately -96dBc. The quadratic interpolation term uses the remaining decimal places after the phase lookup digits. Since dsin(x) / dx = cos(x) and dcos(x) / dx = -sin(x), the resulting sin / cos value and the remaining decimal places of the phase can be used to calculate the compensation value, increasing output accuracy.

[0086] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not limitations on the implementation methods of the present invention. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made based on the above description. It is impossible to list all the implementation methods here. All obvious changes or modifications derived from the technical solution of the present invention are still within the scope of protection of the present invention.

Claims

1. A data preprocessing unit for a broadband digital array radar, characterized in that: It includes a phase-locked loop module, an analog-to-digital conversion module, a bus module, a synchronization pulse module, a control information decoding module and multiple down-conversion modules; wherein, The phase-locked loop module generates the system clock and the working clock required by the analog-to-digital conversion module based on the input reference signal; An analog-to-digital conversion module is used to receive the intermediate frequency signal of the broadband digital array radar and convert it into a digital signal; Bus module, used for interconnection and signal interaction among various modules of the data preprocessing unit; A control information decoding module, configured to parse the control information received by the data preprocessing unit to obtain working parameter configuration information and output the information to the synchronization pulse module through the bus module; Synchronous pulse module, used for anti-collision edge adjustment based on the phase relationship between the external synchronization signal and the system clock; a down-conversion module, configured to perform speed reduction, amplitude and phase compensation, frequency conversion, and / or beamforming on the data converted by the analog-to-digital conversion module; The down-conversion module includes multiple down-conversion channels, each of which includes: an NCO module, an FIR filter module, an equalization filter module and an extraction module; in, The NCO module is used to perform frequency conversion on the data output by the analog-to-digital conversion module into a baseband signal; The FIR filtering module is used to perform FIR filtering on the data processed by the NCO module; The extraction module is used to reduce the speed of the data obtained by the FIR filtering module; The equalization filter module is used to perform amplitude and phase equalization processing on the data after the FIR filtering processing.

2. The data preprocessing unit according to claim 1, wherein: The data preprocessing unit further includes: a mode configuration module, configured to configure the working mode of the down-conversion module according to the working parameter configuration information parsed by the control information decoding module.

3. The data preprocessing unit according to claim 1, wherein: The bus module adopts a virtual cross-interconnection network, and two transmission paths that do not interfere with each other can occupy the bus for data transmission at the same time.

4. The data preprocessing unit according to claim 1, wherein: The down-conversion module further includes: a DBF module, which is used to perform a synthesis operation on the data output by any down-conversion channel to generate a baseband signal of beam pointing information.

5. The data pre-processing unit according to claim 1, wherein: The down-conversion channel also includes: a de-dithering module, which is used to perform a descrambling operation on the data output by the analog-to-digital conversion module, and restore the original data so that the NCO module is used to perform frequency conversion on the data output by the analog-to-digital conversion module after the descrambling operation by the de-dithering module into a baseband signal.

6. The data pre-processing unit according to claim 1, wherein: The down-conversion channel further includes: a CIC filter module, which is used to filter and sample the baseband signal converted by the NCO module.

7. The data pre-processing unit according to claim 1, wherein: The system clock is up to 640MHz.

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